2 * mma8452.c - Support for Freescale MMA8452Q 3-axis 12-bit accelerometer
4 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
6 * This file is subject to the terms and conditions of version 2 of
7 * the GNU General Public License. See the file COPYING in the main
8 * directory of this archive for more details.
10 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
12 * TODO: orientation / freefall events, autosleep
15 #include <linux/module.h>
16 #include <linux/i2c.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/sysfs.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/buffer.h>
21 #include <linux/iio/triggered_buffer.h>
22 #include <linux/iio/events.h>
23 #include <linux/delay.h>
25 #define MMA8452_STATUS 0x00
26 #define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */
27 #define MMA8452_OUT_Y 0x03
28 #define MMA8452_OUT_Z 0x05
29 #define MMA8452_INT_SRC 0x0c
30 #define MMA8452_WHO_AM_I 0x0d
31 #define MMA8452_DATA_CFG 0x0e
32 #define MMA8452_HP_FILTER_CUTOFF 0x0f
33 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK (BIT(0) | BIT(1))
34 #define MMA8452_TRANSIENT_CFG 0x1d
35 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
36 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
37 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
38 #define MMA8452_TRANSIENT_SRC 0x1e
39 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
40 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
41 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
42 #define MMA8452_TRANSIENT_THS 0x1f
43 #define MMA8452_TRANSIENT_THS_MASK 0x7f
44 #define MMA8452_TRANSIENT_COUNT 0x20
45 #define MMA8452_OFF_X 0x2f
46 #define MMA8452_OFF_Y 0x30
47 #define MMA8452_OFF_Z 0x31
48 #define MMA8452_CTRL_REG1 0x2a
49 #define MMA8452_CTRL_REG2 0x2b
50 #define MMA8452_CTRL_REG2_RST BIT(6)
51 #define MMA8452_CTRL_REG4 0x2d
52 #define MMA8452_CTRL_REG5 0x2e
54 #define MMA8452_MAX_REG 0x31
56 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
58 #define MMA8452_CTRL_DR_MASK (BIT(5) | BIT(4) | BIT(3))
59 #define MMA8452_CTRL_DR_SHIFT 3
60 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
61 #define MMA8452_CTRL_ACTIVE BIT(0)
63 #define MMA8452_DATA_CFG_FS_MASK (BIT(1) | BIT(0))
64 #define MMA8452_DATA_CFG_FS_2G 0
65 #define MMA8452_DATA_CFG_FS_4G 1
66 #define MMA8452_DATA_CFG_FS_8G 2
67 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
69 #define MMA8452_INT_TRANS BIT(5)
71 #define MMA8452_DEVICE_ID 0x2a
74 struct i2c_client *client;
80 static int mma8452_drdy(struct mma8452_data *data)
85 int ret = i2c_smbus_read_byte_data(data->client,
89 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
94 dev_err(&data->client->dev, "data not ready\n");
98 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
100 int ret = mma8452_drdy(data);
103 return i2c_smbus_read_i2c_block_data(data->client,
104 MMA8452_OUT_X, 3 * sizeof(__be16), (u8 *) buf);
107 static ssize_t mma8452_show_int_plus_micros(char *buf,
108 const int (*vals)[2], int n)
113 len += scnprintf(buf + len, PAGE_SIZE - len,
114 "%d.%06d ", vals[n][0], vals[n][1]);
116 /* replace trailing space by newline */
122 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
126 if (val == vals[n][0] && val2 == vals[n][1])
132 static int mma8452_get_odr_index(struct mma8452_data *data)
134 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
135 MMA8452_CTRL_DR_SHIFT;
138 static const int mma8452_samp_freq[8][2] = {
139 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
140 {6, 250000}, {1, 560000}
144 * Hardware has fullscale of -2G, -4G, -8G corresponding to raw value -2048
145 * The userspace interface uses m/s^2 and we declare micro units
146 * So scale factor is given by:
147 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
149 static const int mma8452_scales[3][2] = {
150 {0, 9577}, {0, 19154}, {0, 38307}
153 /* Datasheet table 35 (step time vs sample frequency) */
154 static const int mma8452_transient_time_step_us[8] = {
165 /* Datasheet table 18 (normal mode) */
166 static const int mma8452_hp_filter_cutoff[8][4][2] = {
167 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
168 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
169 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
170 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
171 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
172 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
173 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
174 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
177 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
178 struct device_attribute *attr, char *buf)
180 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
181 ARRAY_SIZE(mma8452_samp_freq));
184 static ssize_t mma8452_show_scale_avail(struct device *dev,
185 struct device_attribute *attr, char *buf)
187 return mma8452_show_int_plus_micros(buf, mma8452_scales,
188 ARRAY_SIZE(mma8452_scales));
191 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
192 struct device_attribute *attr,
195 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
196 struct mma8452_data *data = iio_priv(indio_dev);
197 int i = mma8452_get_odr_index(data);
199 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
200 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
203 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
204 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
205 mma8452_show_scale_avail, NULL, 0);
206 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
207 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
209 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
212 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
213 ARRAY_SIZE(mma8452_samp_freq), val, val2);
216 static int mma8452_get_scale_index(struct mma8452_data *data,
219 return mma8452_get_int_plus_micros_index(mma8452_scales,
220 ARRAY_SIZE(mma8452_scales), val, val2);
223 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
226 int i = mma8452_get_odr_index(data);
228 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
229 ARRAY_SIZE(mma8452_scales[0]), val, val2);
232 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
236 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
240 i = mma8452_get_odr_index(data);
241 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
242 *hz = mma8452_hp_filter_cutoff[i][ret][0];
243 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
248 static int mma8452_read_raw(struct iio_dev *indio_dev,
249 struct iio_chan_spec const *chan,
250 int *val, int *val2, long mask)
252 struct mma8452_data *data = iio_priv(indio_dev);
257 case IIO_CHAN_INFO_RAW:
258 if (iio_buffer_enabled(indio_dev))
261 mutex_lock(&data->lock);
262 ret = mma8452_read(data, buffer);
263 mutex_unlock(&data->lock);
266 *val = sign_extend32(
267 be16_to_cpu(buffer[chan->scan_index]) >> 4, 11);
269 case IIO_CHAN_INFO_SCALE:
270 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
271 *val = mma8452_scales[i][0];
272 *val2 = mma8452_scales[i][1];
273 return IIO_VAL_INT_PLUS_MICRO;
274 case IIO_CHAN_INFO_SAMP_FREQ:
275 i = mma8452_get_odr_index(data);
276 *val = mma8452_samp_freq[i][0];
277 *val2 = mma8452_samp_freq[i][1];
278 return IIO_VAL_INT_PLUS_MICRO;
279 case IIO_CHAN_INFO_CALIBBIAS:
280 ret = i2c_smbus_read_byte_data(data->client, MMA8452_OFF_X +
284 *val = sign_extend32(ret, 7);
286 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
287 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
288 ret = mma8452_read_hp_filter(data, val, val2);
295 return IIO_VAL_INT_PLUS_MICRO;
300 static int mma8452_standby(struct mma8452_data *data)
302 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
303 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
306 static int mma8452_active(struct mma8452_data *data)
308 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
312 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
316 mutex_lock(&data->lock);
318 /* config can only be changed when in standby */
319 ret = mma8452_standby(data);
323 ret = i2c_smbus_write_byte_data(data->client, reg, val);
327 ret = mma8452_active(data);
333 mutex_unlock(&data->lock);
337 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
342 i = mma8452_get_hp_filter_index(data, val, val2);
346 reg = i2c_smbus_read_byte_data(data->client,
347 MMA8452_HP_FILTER_CUTOFF);
350 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
353 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
356 static int mma8452_write_raw(struct iio_dev *indio_dev,
357 struct iio_chan_spec const *chan,
358 int val, int val2, long mask)
360 struct mma8452_data *data = iio_priv(indio_dev);
363 if (iio_buffer_enabled(indio_dev))
367 case IIO_CHAN_INFO_SAMP_FREQ:
368 i = mma8452_get_samp_freq_index(data, val, val2);
372 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
373 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
374 return mma8452_change_config(data, MMA8452_CTRL_REG1,
376 case IIO_CHAN_INFO_SCALE:
377 i = mma8452_get_scale_index(data, val, val2);
380 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
382 return mma8452_change_config(data, MMA8452_DATA_CFG,
384 case IIO_CHAN_INFO_CALIBBIAS:
385 if (val < -128 || val > 127)
387 return mma8452_change_config(data, MMA8452_OFF_X +
388 chan->scan_index, val);
390 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
391 if (val == 0 && val2 == 0) {
392 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
394 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
395 ret = mma8452_set_hp_filter_frequency(data, val, val2);
399 return mma8452_change_config(data, MMA8452_DATA_CFG,
407 static int mma8452_read_thresh(struct iio_dev *indio_dev,
408 const struct iio_chan_spec *chan,
409 enum iio_event_type type,
410 enum iio_event_direction dir,
411 enum iio_event_info info,
414 struct mma8452_data *data = iio_priv(indio_dev);
418 case IIO_EV_INFO_VALUE:
419 ret = i2c_smbus_read_byte_data(data->client,
420 MMA8452_TRANSIENT_THS);
424 *val = ret & MMA8452_TRANSIENT_THS_MASK;
427 case IIO_EV_INFO_PERIOD:
428 ret = i2c_smbus_read_byte_data(data->client,
429 MMA8452_TRANSIENT_COUNT);
433 us = ret * mma8452_transient_time_step_us[
434 mma8452_get_odr_index(data)];
435 *val = us / USEC_PER_SEC;
436 *val2 = us % USEC_PER_SEC;
437 return IIO_VAL_INT_PLUS_MICRO;
439 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
440 ret = i2c_smbus_read_byte_data(data->client,
441 MMA8452_TRANSIENT_CFG);
445 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
449 ret = mma8452_read_hp_filter(data, val, val2);
453 return IIO_VAL_INT_PLUS_MICRO;
460 static int mma8452_write_thresh(struct iio_dev *indio_dev,
461 const struct iio_chan_spec *chan,
462 enum iio_event_type type,
463 enum iio_event_direction dir,
464 enum iio_event_info info,
467 struct mma8452_data *data = iio_priv(indio_dev);
471 case IIO_EV_INFO_VALUE:
472 return mma8452_change_config(data, MMA8452_TRANSIENT_THS,
473 val & MMA8452_TRANSIENT_THS_MASK);
475 case IIO_EV_INFO_PERIOD:
476 steps = (val * USEC_PER_SEC + val2) /
477 mma8452_transient_time_step_us[
478 mma8452_get_odr_index(data)];
483 return mma8452_change_config(data, MMA8452_TRANSIENT_COUNT,
485 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
486 reg = i2c_smbus_read_byte_data(data->client,
487 MMA8452_TRANSIENT_CFG);
491 if (val == 0 && val2 == 0) {
492 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
494 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
495 ret = mma8452_set_hp_filter_frequency(data, val, val2);
499 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
506 static int mma8452_read_event_config(struct iio_dev *indio_dev,
507 const struct iio_chan_spec *chan,
508 enum iio_event_type type,
509 enum iio_event_direction dir)
511 struct mma8452_data *data = iio_priv(indio_dev);
514 ret = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
518 return ret & MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index) ? 1 : 0;
521 static int mma8452_write_event_config(struct iio_dev *indio_dev,
522 const struct iio_chan_spec *chan,
523 enum iio_event_type type,
524 enum iio_event_direction dir,
527 struct mma8452_data *data = iio_priv(indio_dev);
530 val = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
535 val |= MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
537 val &= ~MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
539 val |= MMA8452_TRANSIENT_CFG_ELE;
541 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, val);
544 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
546 struct mma8452_data *data = iio_priv(indio_dev);
547 s64 ts = iio_get_time_ns();
550 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
554 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
555 iio_push_event(indio_dev,
556 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
561 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
562 iio_push_event(indio_dev,
563 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
568 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
569 iio_push_event(indio_dev,
570 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
576 static irqreturn_t mma8452_interrupt(int irq, void *p)
578 struct iio_dev *indio_dev = p;
579 struct mma8452_data *data = iio_priv(indio_dev);
582 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
586 if (src & MMA8452_INT_TRANS) {
587 mma8452_transient_interrupt(indio_dev);
594 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
596 struct iio_poll_func *pf = p;
597 struct iio_dev *indio_dev = pf->indio_dev;
598 struct mma8452_data *data = iio_priv(indio_dev);
599 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
602 ret = mma8452_read(data, (__be16 *) buffer);
606 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
610 iio_trigger_notify_done(indio_dev->trig);
614 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
615 unsigned reg, unsigned writeval,
619 struct mma8452_data *data = iio_priv(indio_dev);
621 if (reg > MMA8452_MAX_REG)
625 return mma8452_change_config(data, reg, writeval);
627 ret = i2c_smbus_read_byte_data(data->client, reg);
636 static const struct iio_event_spec mma8452_transient_event[] = {
638 .type = IIO_EV_TYPE_THRESH,
639 .dir = IIO_EV_DIR_RISING,
640 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
641 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
642 BIT(IIO_EV_INFO_PERIOD) |
643 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
648 * Threshold is configured in fixed 8G/127 steps regardless of
649 * currently selected scale for measurement.
651 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
653 static struct attribute *mma8452_event_attributes[] = {
654 &iio_const_attr_accel_transient_scale.dev_attr.attr,
658 static struct attribute_group mma8452_event_attribute_group = {
659 .attrs = mma8452_event_attributes,
663 #define MMA8452_CHANNEL(axis, idx) { \
666 .channel2 = IIO_MOD_##axis, \
667 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
668 BIT(IIO_CHAN_INFO_CALIBBIAS), \
669 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
670 BIT(IIO_CHAN_INFO_SCALE) | \
671 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
678 .endianness = IIO_BE, \
680 .event_spec = mma8452_transient_event, \
681 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
684 static const struct iio_chan_spec mma8452_channels[] = {
685 MMA8452_CHANNEL(X, 0),
686 MMA8452_CHANNEL(Y, 1),
687 MMA8452_CHANNEL(Z, 2),
688 IIO_CHAN_SOFT_TIMESTAMP(3),
691 static struct attribute *mma8452_attributes[] = {
692 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
693 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
694 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
698 static const struct attribute_group mma8452_group = {
699 .attrs = mma8452_attributes,
702 static const struct iio_info mma8452_info = {
703 .attrs = &mma8452_group,
704 .read_raw = &mma8452_read_raw,
705 .write_raw = &mma8452_write_raw,
706 .event_attrs = &mma8452_event_attribute_group,
707 .read_event_value = &mma8452_read_thresh,
708 .write_event_value = &mma8452_write_thresh,
709 .read_event_config = &mma8452_read_event_config,
710 .write_event_config = &mma8452_write_event_config,
711 .debugfs_reg_access = &mma8452_reg_access_dbg,
712 .driver_module = THIS_MODULE,
715 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
717 static int mma8452_reset(struct i2c_client *client)
722 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
723 MMA8452_CTRL_REG2_RST);
727 for (i = 0; i < 10; i++) {
728 usleep_range(100, 200);
729 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
731 continue; /* I2C comm reset */
734 if (!(ret & MMA8452_CTRL_REG2_RST))
741 static int mma8452_probe(struct i2c_client *client,
742 const struct i2c_device_id *id)
744 struct mma8452_data *data;
745 struct iio_dev *indio_dev;
748 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
751 if (ret != MMA8452_DEVICE_ID)
754 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
758 data = iio_priv(indio_dev);
759 data->client = client;
760 mutex_init(&data->lock);
762 i2c_set_clientdata(client, indio_dev);
763 indio_dev->info = &mma8452_info;
764 indio_dev->name = id->name;
765 indio_dev->dev.parent = &client->dev;
766 indio_dev->modes = INDIO_DIRECT_MODE;
767 indio_dev->channels = mma8452_channels;
768 indio_dev->num_channels = ARRAY_SIZE(mma8452_channels);
769 indio_dev->available_scan_masks = mma8452_scan_masks;
771 ret = mma8452_reset(client);
775 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
776 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
782 * By default set transient threshold to max to avoid events if
783 * enabling without configuring threshold.
785 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
786 MMA8452_TRANSIENT_THS_MASK);
792 * Although we enable the transient interrupt source once and
793 * for all here the transient event detection itself is not
794 * enabled until userspace asks for it by
795 * mma8452_write_event_config()
797 int supported_interrupts = MMA8452_INT_TRANS;
799 /* Assume wired to INT1 pin */
800 ret = i2c_smbus_write_byte_data(client,
802 supported_interrupts);
806 ret = i2c_smbus_write_byte_data(client,
808 supported_interrupts);
813 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
814 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
815 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
820 ret = iio_triggered_buffer_setup(indio_dev, NULL,
821 mma8452_trigger_handler, NULL);
826 ret = devm_request_threaded_irq(&client->dev,
828 NULL, mma8452_interrupt,
829 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
830 client->name, indio_dev);
835 ret = iio_device_register(indio_dev);
842 iio_triggered_buffer_cleanup(indio_dev);
846 static int mma8452_remove(struct i2c_client *client)
848 struct iio_dev *indio_dev = i2c_get_clientdata(client);
850 iio_device_unregister(indio_dev);
851 iio_triggered_buffer_cleanup(indio_dev);
852 mma8452_standby(iio_priv(indio_dev));
857 #ifdef CONFIG_PM_SLEEP
858 static int mma8452_suspend(struct device *dev)
860 return mma8452_standby(iio_priv(i2c_get_clientdata(
861 to_i2c_client(dev))));
864 static int mma8452_resume(struct device *dev)
866 return mma8452_active(iio_priv(i2c_get_clientdata(
867 to_i2c_client(dev))));
870 static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
871 #define MMA8452_PM_OPS (&mma8452_pm_ops)
873 #define MMA8452_PM_OPS NULL
876 static const struct i2c_device_id mma8452_id[] = {
880 MODULE_DEVICE_TABLE(i2c, mma8452_id);
882 static const struct of_device_id mma8452_dt_ids[] = {
883 { .compatible = "fsl,mma8452" },
887 static struct i2c_driver mma8452_driver = {
890 .of_match_table = of_match_ptr(mma8452_dt_ids),
891 .pm = MMA8452_PM_OPS,
893 .probe = mma8452_probe,
894 .remove = mma8452_remove,
895 .id_table = mma8452_id,
897 module_i2c_driver(mma8452_driver);
899 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
900 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
901 MODULE_LICENSE("GPL");