2 * mma8452.c - Support for Freescale MMA8452Q 3-axis 12-bit accelerometer
4 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
6 * This file is subject to the terms and conditions of version 2 of
7 * the GNU General Public License. See the file COPYING in the main
8 * directory of this archive for more details.
10 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
12 * TODO: orientation / freefall events, autosleep
15 #include <linux/module.h>
16 #include <linux/i2c.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/sysfs.h>
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/trigger.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/triggered_buffer.h>
23 #include <linux/iio/events.h>
24 #include <linux/delay.h>
26 #define MMA8452_STATUS 0x00
27 #define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */
28 #define MMA8452_OUT_Y 0x03
29 #define MMA8452_OUT_Z 0x05
30 #define MMA8452_INT_SRC 0x0c
31 #define MMA8452_WHO_AM_I 0x0d
32 #define MMA8452_DATA_CFG 0x0e
33 #define MMA8452_HP_FILTER_CUTOFF 0x0f
34 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK (BIT(0) | BIT(1))
35 #define MMA8452_TRANSIENT_CFG 0x1d
36 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
37 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
38 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
39 #define MMA8452_TRANSIENT_SRC 0x1e
40 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
41 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
42 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
43 #define MMA8452_TRANSIENT_THS 0x1f
44 #define MMA8452_TRANSIENT_THS_MASK 0x7f
45 #define MMA8452_TRANSIENT_COUNT 0x20
46 #define MMA8452_OFF_X 0x2f
47 #define MMA8452_OFF_Y 0x30
48 #define MMA8452_OFF_Z 0x31
49 #define MMA8452_CTRL_REG1 0x2a
50 #define MMA8452_CTRL_REG2 0x2b
51 #define MMA8452_CTRL_REG2_RST BIT(6)
52 #define MMA8452_CTRL_REG4 0x2d
53 #define MMA8452_CTRL_REG5 0x2e
55 #define MMA8452_MAX_REG 0x31
57 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
59 #define MMA8452_CTRL_DR_MASK (BIT(5) | BIT(4) | BIT(3))
60 #define MMA8452_CTRL_DR_SHIFT 3
61 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
62 #define MMA8452_CTRL_ACTIVE BIT(0)
64 #define MMA8452_DATA_CFG_FS_MASK (BIT(1) | BIT(0))
65 #define MMA8452_DATA_CFG_FS_2G 0
66 #define MMA8452_DATA_CFG_FS_4G 1
67 #define MMA8452_DATA_CFG_FS_8G 2
68 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
70 #define MMA8452_INT_DRDY BIT(0)
71 #define MMA8452_INT_TRANS BIT(5)
73 #define MMA8452_DEVICE_ID 0x2a
76 struct i2c_client *client;
82 static int mma8452_drdy(struct mma8452_data *data)
87 int ret = i2c_smbus_read_byte_data(data->client,
91 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
96 dev_err(&data->client->dev, "data not ready\n");
100 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
102 int ret = mma8452_drdy(data);
105 return i2c_smbus_read_i2c_block_data(data->client,
106 MMA8452_OUT_X, 3 * sizeof(__be16), (u8 *) buf);
109 static ssize_t mma8452_show_int_plus_micros(char *buf,
110 const int (*vals)[2], int n)
115 len += scnprintf(buf + len, PAGE_SIZE - len,
116 "%d.%06d ", vals[n][0], vals[n][1]);
118 /* replace trailing space by newline */
124 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
128 if (val == vals[n][0] && val2 == vals[n][1])
134 static int mma8452_get_odr_index(struct mma8452_data *data)
136 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
137 MMA8452_CTRL_DR_SHIFT;
140 static const int mma8452_samp_freq[8][2] = {
141 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
142 {6, 250000}, {1, 560000}
146 * Hardware has fullscale of -2G, -4G, -8G corresponding to raw value -2048
147 * The userspace interface uses m/s^2 and we declare micro units
148 * So scale factor is given by:
149 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
151 static const int mma8452_scales[3][2] = {
152 {0, 9577}, {0, 19154}, {0, 38307}
155 /* Datasheet table 35 (step time vs sample frequency) */
156 static const int mma8452_transient_time_step_us[8] = {
167 /* Datasheet table 18 (normal mode) */
168 static const int mma8452_hp_filter_cutoff[8][4][2] = {
169 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
170 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
171 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
172 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
173 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
174 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
175 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
176 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
179 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
180 struct device_attribute *attr, char *buf)
182 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
183 ARRAY_SIZE(mma8452_samp_freq));
186 static ssize_t mma8452_show_scale_avail(struct device *dev,
187 struct device_attribute *attr, char *buf)
189 return mma8452_show_int_plus_micros(buf, mma8452_scales,
190 ARRAY_SIZE(mma8452_scales));
193 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
194 struct device_attribute *attr,
197 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
198 struct mma8452_data *data = iio_priv(indio_dev);
199 int i = mma8452_get_odr_index(data);
201 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
202 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
205 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
206 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
207 mma8452_show_scale_avail, NULL, 0);
208 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
209 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
211 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
214 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
215 ARRAY_SIZE(mma8452_samp_freq), val, val2);
218 static int mma8452_get_scale_index(struct mma8452_data *data,
221 return mma8452_get_int_plus_micros_index(mma8452_scales,
222 ARRAY_SIZE(mma8452_scales), val, val2);
225 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
228 int i = mma8452_get_odr_index(data);
230 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
231 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
234 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
238 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
242 i = mma8452_get_odr_index(data);
243 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
244 *hz = mma8452_hp_filter_cutoff[i][ret][0];
245 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
250 static int mma8452_read_raw(struct iio_dev *indio_dev,
251 struct iio_chan_spec const *chan,
252 int *val, int *val2, long mask)
254 struct mma8452_data *data = iio_priv(indio_dev);
259 case IIO_CHAN_INFO_RAW:
260 if (iio_buffer_enabled(indio_dev))
263 mutex_lock(&data->lock);
264 ret = mma8452_read(data, buffer);
265 mutex_unlock(&data->lock);
268 *val = sign_extend32(
269 be16_to_cpu(buffer[chan->scan_index]) >> 4, 11);
271 case IIO_CHAN_INFO_SCALE:
272 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
273 *val = mma8452_scales[i][0];
274 *val2 = mma8452_scales[i][1];
275 return IIO_VAL_INT_PLUS_MICRO;
276 case IIO_CHAN_INFO_SAMP_FREQ:
277 i = mma8452_get_odr_index(data);
278 *val = mma8452_samp_freq[i][0];
279 *val2 = mma8452_samp_freq[i][1];
280 return IIO_VAL_INT_PLUS_MICRO;
281 case IIO_CHAN_INFO_CALIBBIAS:
282 ret = i2c_smbus_read_byte_data(data->client, MMA8452_OFF_X +
286 *val = sign_extend32(ret, 7);
288 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
289 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
290 ret = mma8452_read_hp_filter(data, val, val2);
297 return IIO_VAL_INT_PLUS_MICRO;
302 static int mma8452_standby(struct mma8452_data *data)
304 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
305 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
308 static int mma8452_active(struct mma8452_data *data)
310 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
314 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
318 mutex_lock(&data->lock);
320 /* config can only be changed when in standby */
321 ret = mma8452_standby(data);
325 ret = i2c_smbus_write_byte_data(data->client, reg, val);
329 ret = mma8452_active(data);
335 mutex_unlock(&data->lock);
339 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
344 i = mma8452_get_hp_filter_index(data, val, val2);
348 reg = i2c_smbus_read_byte_data(data->client,
349 MMA8452_HP_FILTER_CUTOFF);
352 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
355 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
358 static int mma8452_write_raw(struct iio_dev *indio_dev,
359 struct iio_chan_spec const *chan,
360 int val, int val2, long mask)
362 struct mma8452_data *data = iio_priv(indio_dev);
365 if (iio_buffer_enabled(indio_dev))
369 case IIO_CHAN_INFO_SAMP_FREQ:
370 i = mma8452_get_samp_freq_index(data, val, val2);
374 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
375 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
376 return mma8452_change_config(data, MMA8452_CTRL_REG1,
378 case IIO_CHAN_INFO_SCALE:
379 i = mma8452_get_scale_index(data, val, val2);
382 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
384 return mma8452_change_config(data, MMA8452_DATA_CFG,
386 case IIO_CHAN_INFO_CALIBBIAS:
387 if (val < -128 || val > 127)
389 return mma8452_change_config(data, MMA8452_OFF_X +
390 chan->scan_index, val);
392 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
393 if (val == 0 && val2 == 0) {
394 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
396 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
397 ret = mma8452_set_hp_filter_frequency(data, val, val2);
401 return mma8452_change_config(data, MMA8452_DATA_CFG,
409 static int mma8452_read_thresh(struct iio_dev *indio_dev,
410 const struct iio_chan_spec *chan,
411 enum iio_event_type type,
412 enum iio_event_direction dir,
413 enum iio_event_info info,
416 struct mma8452_data *data = iio_priv(indio_dev);
420 case IIO_EV_INFO_VALUE:
421 ret = i2c_smbus_read_byte_data(data->client,
422 MMA8452_TRANSIENT_THS);
426 *val = ret & MMA8452_TRANSIENT_THS_MASK;
429 case IIO_EV_INFO_PERIOD:
430 ret = i2c_smbus_read_byte_data(data->client,
431 MMA8452_TRANSIENT_COUNT);
435 us = ret * mma8452_transient_time_step_us[
436 mma8452_get_odr_index(data)];
437 *val = us / USEC_PER_SEC;
438 *val2 = us % USEC_PER_SEC;
439 return IIO_VAL_INT_PLUS_MICRO;
441 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
442 ret = i2c_smbus_read_byte_data(data->client,
443 MMA8452_TRANSIENT_CFG);
447 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
451 ret = mma8452_read_hp_filter(data, val, val2);
455 return IIO_VAL_INT_PLUS_MICRO;
462 static int mma8452_write_thresh(struct iio_dev *indio_dev,
463 const struct iio_chan_spec *chan,
464 enum iio_event_type type,
465 enum iio_event_direction dir,
466 enum iio_event_info info,
469 struct mma8452_data *data = iio_priv(indio_dev);
473 case IIO_EV_INFO_VALUE:
474 return mma8452_change_config(data, MMA8452_TRANSIENT_THS,
475 val & MMA8452_TRANSIENT_THS_MASK);
477 case IIO_EV_INFO_PERIOD:
478 steps = (val * USEC_PER_SEC + val2) /
479 mma8452_transient_time_step_us[
480 mma8452_get_odr_index(data)];
485 return mma8452_change_config(data, MMA8452_TRANSIENT_COUNT,
487 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
488 reg = i2c_smbus_read_byte_data(data->client,
489 MMA8452_TRANSIENT_CFG);
493 if (val == 0 && val2 == 0) {
494 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
496 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
497 ret = mma8452_set_hp_filter_frequency(data, val, val2);
501 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
508 static int mma8452_read_event_config(struct iio_dev *indio_dev,
509 const struct iio_chan_spec *chan,
510 enum iio_event_type type,
511 enum iio_event_direction dir)
513 struct mma8452_data *data = iio_priv(indio_dev);
516 ret = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
520 return ret & MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index) ? 1 : 0;
523 static int mma8452_write_event_config(struct iio_dev *indio_dev,
524 const struct iio_chan_spec *chan,
525 enum iio_event_type type,
526 enum iio_event_direction dir,
529 struct mma8452_data *data = iio_priv(indio_dev);
532 val = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
537 val |= MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
539 val &= ~MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
541 val |= MMA8452_TRANSIENT_CFG_ELE;
543 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, val);
546 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
548 struct mma8452_data *data = iio_priv(indio_dev);
549 s64 ts = iio_get_time_ns();
552 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
556 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
557 iio_push_event(indio_dev,
558 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
563 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
564 iio_push_event(indio_dev,
565 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
570 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
571 iio_push_event(indio_dev,
572 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
578 static irqreturn_t mma8452_interrupt(int irq, void *p)
580 struct iio_dev *indio_dev = p;
581 struct mma8452_data *data = iio_priv(indio_dev);
585 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
589 if (src & MMA8452_INT_DRDY) {
590 iio_trigger_poll_chained(indio_dev->trig);
594 if (src & MMA8452_INT_TRANS) {
595 mma8452_transient_interrupt(indio_dev);
602 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
604 struct iio_poll_func *pf = p;
605 struct iio_dev *indio_dev = pf->indio_dev;
606 struct mma8452_data *data = iio_priv(indio_dev);
607 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
610 ret = mma8452_read(data, (__be16 *) buffer);
614 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
618 iio_trigger_notify_done(indio_dev->trig);
622 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
623 unsigned reg, unsigned writeval,
627 struct mma8452_data *data = iio_priv(indio_dev);
629 if (reg > MMA8452_MAX_REG)
633 return mma8452_change_config(data, reg, writeval);
635 ret = i2c_smbus_read_byte_data(data->client, reg);
644 static const struct iio_event_spec mma8452_transient_event[] = {
646 .type = IIO_EV_TYPE_THRESH,
647 .dir = IIO_EV_DIR_RISING,
648 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
649 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
650 BIT(IIO_EV_INFO_PERIOD) |
651 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
656 * Threshold is configured in fixed 8G/127 steps regardless of
657 * currently selected scale for measurement.
659 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
661 static struct attribute *mma8452_event_attributes[] = {
662 &iio_const_attr_accel_transient_scale.dev_attr.attr,
666 static struct attribute_group mma8452_event_attribute_group = {
667 .attrs = mma8452_event_attributes,
671 #define MMA8452_CHANNEL(axis, idx) { \
674 .channel2 = IIO_MOD_##axis, \
675 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
676 BIT(IIO_CHAN_INFO_CALIBBIAS), \
677 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
678 BIT(IIO_CHAN_INFO_SCALE) | \
679 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
686 .endianness = IIO_BE, \
688 .event_spec = mma8452_transient_event, \
689 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
692 static const struct iio_chan_spec mma8452_channels[] = {
693 MMA8452_CHANNEL(X, 0),
694 MMA8452_CHANNEL(Y, 1),
695 MMA8452_CHANNEL(Z, 2),
696 IIO_CHAN_SOFT_TIMESTAMP(3),
699 static struct attribute *mma8452_attributes[] = {
700 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
701 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
702 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
706 static const struct attribute_group mma8452_group = {
707 .attrs = mma8452_attributes,
710 static const struct iio_info mma8452_info = {
711 .attrs = &mma8452_group,
712 .read_raw = &mma8452_read_raw,
713 .write_raw = &mma8452_write_raw,
714 .event_attrs = &mma8452_event_attribute_group,
715 .read_event_value = &mma8452_read_thresh,
716 .write_event_value = &mma8452_write_thresh,
717 .read_event_config = &mma8452_read_event_config,
718 .write_event_config = &mma8452_write_event_config,
719 .debugfs_reg_access = &mma8452_reg_access_dbg,
720 .driver_module = THIS_MODULE,
723 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
725 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
728 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
729 struct mma8452_data *data = iio_priv(indio_dev);
732 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
737 reg |= MMA8452_INT_DRDY;
739 reg &= ~MMA8452_INT_DRDY;
741 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
744 static int mma8452_validate_device(struct iio_trigger *trig,
745 struct iio_dev *indio_dev)
747 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
749 if (indio != indio_dev)
755 static const struct iio_trigger_ops mma8452_trigger_ops = {
756 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
757 .validate_device = mma8452_validate_device,
758 .owner = THIS_MODULE,
761 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
763 struct mma8452_data *data = iio_priv(indio_dev);
764 struct iio_trigger *trig;
767 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
773 trig->dev.parent = &data->client->dev;
774 trig->ops = &mma8452_trigger_ops;
775 iio_trigger_set_drvdata(trig, indio_dev);
777 ret = iio_trigger_register(trig);
781 indio_dev->trig = trig;
785 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
788 iio_trigger_unregister(indio_dev->trig);
791 static int mma8452_reset(struct i2c_client *client)
796 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
797 MMA8452_CTRL_REG2_RST);
801 for (i = 0; i < 10; i++) {
802 usleep_range(100, 200);
803 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
805 continue; /* I2C comm reset */
808 if (!(ret & MMA8452_CTRL_REG2_RST))
815 static int mma8452_probe(struct i2c_client *client,
816 const struct i2c_device_id *id)
818 struct mma8452_data *data;
819 struct iio_dev *indio_dev;
822 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
825 if (ret != MMA8452_DEVICE_ID)
828 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
832 data = iio_priv(indio_dev);
833 data->client = client;
834 mutex_init(&data->lock);
836 i2c_set_clientdata(client, indio_dev);
837 indio_dev->info = &mma8452_info;
838 indio_dev->name = id->name;
839 indio_dev->dev.parent = &client->dev;
840 indio_dev->modes = INDIO_DIRECT_MODE;
841 indio_dev->channels = mma8452_channels;
842 indio_dev->num_channels = ARRAY_SIZE(mma8452_channels);
843 indio_dev->available_scan_masks = mma8452_scan_masks;
845 ret = mma8452_reset(client);
849 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
850 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
856 * By default set transient threshold to max to avoid events if
857 * enabling without configuring threshold.
859 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
860 MMA8452_TRANSIENT_THS_MASK);
866 * Although we enable the transient interrupt source once and
867 * for all here the transient event detection itself is not
868 * enabled until userspace asks for it by
869 * mma8452_write_event_config()
871 int supported_interrupts = MMA8452_INT_DRDY | MMA8452_INT_TRANS;
872 int enabled_interrupts = MMA8452_INT_TRANS;
874 /* Assume wired to INT1 pin */
875 ret = i2c_smbus_write_byte_data(client,
877 supported_interrupts);
881 ret = i2c_smbus_write_byte_data(client,
887 ret = mma8452_trigger_setup(indio_dev);
892 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
893 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
894 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
897 goto trigger_cleanup;
899 ret = iio_triggered_buffer_setup(indio_dev, NULL,
900 mma8452_trigger_handler, NULL);
902 goto trigger_cleanup;
905 ret = devm_request_threaded_irq(&client->dev,
907 NULL, mma8452_interrupt,
908 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
909 client->name, indio_dev);
914 ret = iio_device_register(indio_dev);
921 iio_triggered_buffer_cleanup(indio_dev);
924 mma8452_trigger_cleanup(indio_dev);
929 static int mma8452_remove(struct i2c_client *client)
931 struct iio_dev *indio_dev = i2c_get_clientdata(client);
933 iio_device_unregister(indio_dev);
934 iio_triggered_buffer_cleanup(indio_dev);
935 mma8452_trigger_cleanup(indio_dev);
936 mma8452_standby(iio_priv(indio_dev));
941 #ifdef CONFIG_PM_SLEEP
942 static int mma8452_suspend(struct device *dev)
944 return mma8452_standby(iio_priv(i2c_get_clientdata(
945 to_i2c_client(dev))));
948 static int mma8452_resume(struct device *dev)
950 return mma8452_active(iio_priv(i2c_get_clientdata(
951 to_i2c_client(dev))));
954 static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
955 #define MMA8452_PM_OPS (&mma8452_pm_ops)
957 #define MMA8452_PM_OPS NULL
960 static const struct i2c_device_id mma8452_id[] = {
964 MODULE_DEVICE_TABLE(i2c, mma8452_id);
966 static const struct of_device_id mma8452_dt_ids[] = {
967 { .compatible = "fsl,mma8452" },
970 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
972 static struct i2c_driver mma8452_driver = {
975 .of_match_table = of_match_ptr(mma8452_dt_ids),
976 .pm = MMA8452_PM_OPS,
978 .probe = mma8452_probe,
979 .remove = mma8452_remove,
980 .id_table = mma8452_id,
982 module_i2c_driver(mma8452_driver);
984 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
985 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
986 MODULE_LICENSE("GPL");