1 // SPDX-License-Identifier: GPL-2.0
3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
5 * device name digital output 7-bit I2C slave address (pin selectable)
6 * ---------------------------------------------------------------------
7 * MMA8451Q 14 bit 0x1c / 0x1d
8 * MMA8452Q 12 bit 0x1c / 0x1d
9 * MMA8453Q 10 bit 0x1c / 0x1d
10 * MMA8652FC 12 bit 0x1d
11 * MMA8653FC 10 bit 0x1d
12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
14 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
18 * TODO: orientation events
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/delay.h>
31 #include <linux/of_device.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
36 #define MMA8452_STATUS 0x00
37 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
38 #define MMA8452_OUT_X 0x01 /* MSB first */
39 #define MMA8452_OUT_Y 0x03
40 #define MMA8452_OUT_Z 0x05
41 #define MMA8452_INT_SRC 0x0c
42 #define MMA8452_WHO_AM_I 0x0d
43 #define MMA8452_DATA_CFG 0x0e
44 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
45 #define MMA8452_DATA_CFG_FS_2G 0
46 #define MMA8452_DATA_CFG_FS_4G 1
47 #define MMA8452_DATA_CFG_FS_8G 2
48 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
49 #define MMA8452_HP_FILTER_CUTOFF 0x0f
50 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
51 #define MMA8452_FF_MT_CFG 0x15
52 #define MMA8452_FF_MT_CFG_OAE BIT(6)
53 #define MMA8452_FF_MT_CFG_ELE BIT(7)
54 #define MMA8452_FF_MT_SRC 0x16
55 #define MMA8452_FF_MT_SRC_XHE BIT(1)
56 #define MMA8452_FF_MT_SRC_YHE BIT(3)
57 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
58 #define MMA8452_FF_MT_THS 0x17
59 #define MMA8452_FF_MT_THS_MASK 0x7f
60 #define MMA8452_FF_MT_COUNT 0x18
61 #define MMA8452_FF_MT_CHAN_SHIFT 3
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
64 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
65 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
66 #define MMA8452_TRANSIENT_SRC 0x1e
67 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
68 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
69 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
70 #define MMA8452_TRANSIENT_THS 0x1f
71 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
72 #define MMA8452_TRANSIENT_COUNT 0x20
73 #define MMA8452_TRANSIENT_CHAN_SHIFT 1
74 #define MMA8452_CTRL_REG1 0x2a
75 #define MMA8452_CTRL_ACTIVE BIT(0)
76 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
77 #define MMA8452_CTRL_DR_SHIFT 3
78 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
79 #define MMA8452_CTRL_REG2 0x2b
80 #define MMA8452_CTRL_REG2_RST BIT(6)
81 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
82 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
83 #define MMA8452_CTRL_REG4 0x2d
84 #define MMA8452_CTRL_REG5 0x2e
85 #define MMA8452_OFF_X 0x2f
86 #define MMA8452_OFF_Y 0x30
87 #define MMA8452_OFF_Z 0x31
89 #define MMA8452_MAX_REG 0x31
91 #define MMA8452_INT_DRDY BIT(0)
92 #define MMA8452_INT_FF_MT BIT(2)
93 #define MMA8452_INT_TRANS BIT(5)
95 #define MMA8451_DEVICE_ID 0x1a
96 #define MMA8452_DEVICE_ID 0x2a
97 #define MMA8453_DEVICE_ID 0x3a
98 #define MMA8652_DEVICE_ID 0x4a
99 #define MMA8653_DEVICE_ID 0x5a
100 #define FXLS8471_DEVICE_ID 0x6a
102 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
104 struct mma8452_data {
105 struct i2c_client *client;
109 const struct mma_chip_info *chip_info;
111 struct regulator *vdd_reg;
112 struct regulator *vddio_reg;
114 /* Ensure correct alignment of time stamp when present */
122 * struct mma8452_event_regs - chip specific data related to events
123 * @ev_cfg: event config register address
124 * @ev_cfg_ele: latch bit in event config register
125 * @ev_cfg_chan_shift: number of the bit to enable events in X
126 * direction; in event config register
127 * @ev_src: event source register address
128 * @ev_ths: event threshold register address
129 * @ev_ths_mask: mask for the threshold value
130 * @ev_count: event count (period) register address
132 * Since not all chips supported by the driver support comparing high pass
133 * filtered data for events (interrupts), different interrupt sources are
134 * used for different chips and the relevant registers are included here.
136 struct mma8452_event_regs {
139 u8 ev_cfg_chan_shift;
146 static const struct mma8452_event_regs ff_mt_ev_regs = {
147 .ev_cfg = MMA8452_FF_MT_CFG,
148 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
149 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
150 .ev_src = MMA8452_FF_MT_SRC,
151 .ev_ths = MMA8452_FF_MT_THS,
152 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
153 .ev_count = MMA8452_FF_MT_COUNT
156 static const struct mma8452_event_regs trans_ev_regs = {
157 .ev_cfg = MMA8452_TRANSIENT_CFG,
158 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
159 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
160 .ev_src = MMA8452_TRANSIENT_SRC,
161 .ev_ths = MMA8452_TRANSIENT_THS,
162 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
163 .ev_count = MMA8452_TRANSIENT_COUNT,
167 * struct mma_chip_info - chip specific data
168 * @chip_id: WHO_AM_I register's value
169 * @channels: struct iio_chan_spec matching the device's
171 * @num_channels: number of channels
172 * @mma_scales: scale factors for converting register values
173 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
174 * per mode: m/s^2 and micro m/s^2
175 * @all_events: all events supported by this chip
176 * @enabled_events: event flags enabled and handled by this driver
178 struct mma_chip_info {
180 const struct iio_chan_spec *channels;
182 const int mma_scales[3][2];
194 static int mma8452_drdy(struct mma8452_data *data)
198 while (tries-- > 0) {
199 int ret = i2c_smbus_read_byte_data(data->client,
203 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
206 if (data->sleep_val <= 20)
207 usleep_range(data->sleep_val * 250,
208 data->sleep_val * 500);
213 dev_err(&data->client->dev, "data not ready\n");
218 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
224 ret = pm_runtime_resume_and_get(&client->dev);
226 pm_runtime_mark_last_busy(&client->dev);
227 ret = pm_runtime_put_autosuspend(&client->dev);
231 dev_err(&client->dev,
232 "failed to change power state to %d\n", on);
241 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
243 int ret = mma8452_drdy(data);
248 ret = mma8452_set_runtime_pm_state(data->client, true);
252 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
253 3 * sizeof(__be16), (u8 *)buf);
255 ret = mma8452_set_runtime_pm_state(data->client, false);
260 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
266 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
267 vals[n][0], vals[n][1]);
269 /* replace trailing space by newline */
275 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
279 if (val == vals[n][0] && val2 == vals[n][1])
285 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
287 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
288 MMA8452_CTRL_DR_SHIFT;
291 static const int mma8452_samp_freq[8][2] = {
292 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
293 {6, 250000}, {1, 560000}
296 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
297 static const unsigned int mma8452_time_step_us[4][8] = {
298 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
299 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
300 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
301 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
304 /* Datasheet table "High-Pass Filter Cutoff Options" */
305 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
307 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
308 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
309 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
310 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
311 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
312 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
313 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
316 { /* low noise low power */
317 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
318 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
319 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
320 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
321 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
322 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
323 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
324 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
326 { /* high resolution */
327 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
328 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
329 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
337 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
338 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
339 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
340 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
341 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
342 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
343 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
344 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
348 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
349 static const u16 mma8452_os_ratio[4][8] = {
350 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
351 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
352 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
353 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
354 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
357 static int mma8452_get_power_mode(struct mma8452_data *data)
361 reg = i2c_smbus_read_byte_data(data->client,
366 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
367 MMA8452_CTRL_REG2_MODS_SHIFT);
370 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
371 struct device_attribute *attr,
374 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
375 ARRAY_SIZE(mma8452_samp_freq));
378 static ssize_t mma8452_show_scale_avail(struct device *dev,
379 struct device_attribute *attr,
382 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
383 to_i2c_client(dev)));
385 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
386 ARRAY_SIZE(data->chip_info->mma_scales));
389 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
390 struct device_attribute *attr,
393 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
394 struct mma8452_data *data = iio_priv(indio_dev);
397 i = mma8452_get_odr_index(data);
398 j = mma8452_get_power_mode(data);
402 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
403 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
406 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
407 struct device_attribute *attr,
410 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
411 struct mma8452_data *data = iio_priv(indio_dev);
412 int i = mma8452_get_odr_index(data);
417 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
418 if (val == mma8452_os_ratio[j][i])
421 val = mma8452_os_ratio[j][i];
423 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
430 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
431 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
432 mma8452_show_scale_avail, NULL, 0);
433 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
434 0444, mma8452_show_hp_cutoff_avail, NULL, 0);
435 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
436 mma8452_show_os_ratio_avail, NULL, 0);
438 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
441 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
442 ARRAY_SIZE(mma8452_samp_freq),
446 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
448 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
449 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
452 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
457 i = mma8452_get_odr_index(data);
458 j = mma8452_get_power_mode(data);
462 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
463 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
466 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
470 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
474 i = mma8452_get_odr_index(data);
475 j = mma8452_get_power_mode(data);
479 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
480 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
481 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
486 static int mma8452_read_raw(struct iio_dev *indio_dev,
487 struct iio_chan_spec const *chan,
488 int *val, int *val2, long mask)
490 struct mma8452_data *data = iio_priv(indio_dev);
495 case IIO_CHAN_INFO_RAW:
496 ret = iio_device_claim_direct_mode(indio_dev);
500 mutex_lock(&data->lock);
501 ret = mma8452_read(data, buffer);
502 mutex_unlock(&data->lock);
503 iio_device_release_direct_mode(indio_dev);
507 *val = sign_extend32(be16_to_cpu(
508 buffer[chan->scan_index]) >> chan->scan_type.shift,
509 chan->scan_type.realbits - 1);
512 case IIO_CHAN_INFO_SCALE:
513 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
514 *val = data->chip_info->mma_scales[i][0];
515 *val2 = data->chip_info->mma_scales[i][1];
517 return IIO_VAL_INT_PLUS_MICRO;
518 case IIO_CHAN_INFO_SAMP_FREQ:
519 i = mma8452_get_odr_index(data);
520 *val = mma8452_samp_freq[i][0];
521 *val2 = mma8452_samp_freq[i][1];
523 return IIO_VAL_INT_PLUS_MICRO;
524 case IIO_CHAN_INFO_CALIBBIAS:
525 ret = i2c_smbus_read_byte_data(data->client,
531 *val = sign_extend32(ret, 7);
534 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
535 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
536 ret = mma8452_read_hp_filter(data, val, val2);
544 return IIO_VAL_INT_PLUS_MICRO;
545 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
546 ret = mma8452_get_power_mode(data);
550 i = mma8452_get_odr_index(data);
552 *val = mma8452_os_ratio[ret][i];
559 static int mma8452_calculate_sleep(struct mma8452_data *data)
561 int ret, i = mma8452_get_odr_index(data);
563 if (mma8452_samp_freq[i][0] > 0)
564 ret = 1000 / mma8452_samp_freq[i][0];
568 return ret == 0 ? 1 : ret;
571 static int mma8452_standby(struct mma8452_data *data)
573 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
574 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
577 static int mma8452_active(struct mma8452_data *data)
579 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
583 /* returns >0 if active, 0 if in standby and <0 on error */
584 static int mma8452_is_active(struct mma8452_data *data)
588 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
592 return reg & MMA8452_CTRL_ACTIVE;
595 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
600 mutex_lock(&data->lock);
602 is_active = mma8452_is_active(data);
608 /* config can only be changed when in standby */
610 ret = mma8452_standby(data);
615 ret = i2c_smbus_write_byte_data(data->client, reg, val);
620 ret = mma8452_active(data);
627 mutex_unlock(&data->lock);
632 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
636 reg = i2c_smbus_read_byte_data(data->client,
641 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
642 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
644 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
647 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
648 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
652 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
656 return !(val & MMA8452_FF_MT_CFG_OAE);
659 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
663 if ((state && mma8452_freefall_mode_enabled(data)) ||
664 (!state && !(mma8452_freefall_mode_enabled(data))))
667 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
672 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
673 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
674 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
675 val &= ~MMA8452_FF_MT_CFG_OAE;
677 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
678 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
679 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
680 val |= MMA8452_FF_MT_CFG_OAE;
683 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
686 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
691 i = mma8452_get_hp_filter_index(data, val, val2);
695 reg = i2c_smbus_read_byte_data(data->client,
696 MMA8452_HP_FILTER_CUTOFF);
700 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
703 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
706 static int mma8452_write_raw(struct iio_dev *indio_dev,
707 struct iio_chan_spec const *chan,
708 int val, int val2, long mask)
710 struct mma8452_data *data = iio_priv(indio_dev);
713 ret = iio_device_claim_direct_mode(indio_dev);
718 case IIO_CHAN_INFO_SAMP_FREQ:
719 i = mma8452_get_samp_freq_index(data, val, val2);
724 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
725 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
727 data->sleep_val = mma8452_calculate_sleep(data);
729 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
732 case IIO_CHAN_INFO_SCALE:
733 i = mma8452_get_scale_index(data, val, val2);
739 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
742 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
745 case IIO_CHAN_INFO_CALIBBIAS:
746 if (val < -128 || val > 127) {
751 ret = mma8452_change_config(data,
752 MMA8452_OFF_X + chan->scan_index,
756 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
757 if (val == 0 && val2 == 0) {
758 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
760 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
761 ret = mma8452_set_hp_filter_frequency(data, val, val2);
766 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
770 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
771 ret = mma8452_get_odr_index(data);
773 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
774 if (mma8452_os_ratio[i][ret] == val) {
775 ret = mma8452_set_power_mode(data, i);
785 iio_device_release_direct_mode(indio_dev);
789 static int mma8452_get_event_regs(struct mma8452_data *data,
790 const struct iio_chan_spec *chan, enum iio_event_direction dir,
791 const struct mma8452_event_regs **ev_reg)
796 switch (chan->type) {
799 case IIO_EV_DIR_RISING:
800 if ((data->chip_info->all_events
801 & MMA8452_INT_TRANS) &&
802 (data->chip_info->enabled_events
803 & MMA8452_INT_TRANS))
804 *ev_reg = &trans_ev_regs;
806 *ev_reg = &ff_mt_ev_regs;
808 case IIO_EV_DIR_FALLING:
809 *ev_reg = &ff_mt_ev_regs;
819 static int mma8452_read_event_value(struct iio_dev *indio_dev,
820 const struct iio_chan_spec *chan,
821 enum iio_event_type type,
822 enum iio_event_direction dir,
823 enum iio_event_info info,
826 struct mma8452_data *data = iio_priv(indio_dev);
827 int ret, us, power_mode;
828 const struct mma8452_event_regs *ev_regs;
830 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
835 case IIO_EV_INFO_VALUE:
836 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
840 *val = ret & ev_regs->ev_ths_mask;
844 case IIO_EV_INFO_PERIOD:
845 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
849 power_mode = mma8452_get_power_mode(data);
853 us = ret * mma8452_time_step_us[power_mode][
854 mma8452_get_odr_index(data)];
855 *val = us / USEC_PER_SEC;
856 *val2 = us % USEC_PER_SEC;
858 return IIO_VAL_INT_PLUS_MICRO;
860 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
861 ret = i2c_smbus_read_byte_data(data->client,
862 MMA8452_TRANSIENT_CFG);
866 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
870 ret = mma8452_read_hp_filter(data, val, val2);
875 return IIO_VAL_INT_PLUS_MICRO;
882 static int mma8452_write_event_value(struct iio_dev *indio_dev,
883 const struct iio_chan_spec *chan,
884 enum iio_event_type type,
885 enum iio_event_direction dir,
886 enum iio_event_info info,
889 struct mma8452_data *data = iio_priv(indio_dev);
891 const struct mma8452_event_regs *ev_regs;
893 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
898 case IIO_EV_INFO_VALUE:
899 if (val < 0 || val > ev_regs->ev_ths_mask)
902 return mma8452_change_config(data, ev_regs->ev_ths, val);
904 case IIO_EV_INFO_PERIOD:
905 ret = mma8452_get_power_mode(data);
909 steps = (val * USEC_PER_SEC + val2) /
910 mma8452_time_step_us[ret][
911 mma8452_get_odr_index(data)];
913 if (steps < 0 || steps > 0xff)
916 return mma8452_change_config(data, ev_regs->ev_count, steps);
918 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
919 reg = i2c_smbus_read_byte_data(data->client,
920 MMA8452_TRANSIENT_CFG);
924 if (val == 0 && val2 == 0) {
925 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
927 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
928 ret = mma8452_set_hp_filter_frequency(data, val, val2);
933 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
940 static int mma8452_read_event_config(struct iio_dev *indio_dev,
941 const struct iio_chan_spec *chan,
942 enum iio_event_type type,
943 enum iio_event_direction dir)
945 struct mma8452_data *data = iio_priv(indio_dev);
947 const struct mma8452_event_regs *ev_regs;
949 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
954 case IIO_EV_DIR_FALLING:
955 return mma8452_freefall_mode_enabled(data);
956 case IIO_EV_DIR_RISING:
957 ret = i2c_smbus_read_byte_data(data->client,
962 return !!(ret & BIT(chan->scan_index +
963 ev_regs->ev_cfg_chan_shift));
969 static int mma8452_write_event_config(struct iio_dev *indio_dev,
970 const struct iio_chan_spec *chan,
971 enum iio_event_type type,
972 enum iio_event_direction dir,
975 struct mma8452_data *data = iio_priv(indio_dev);
977 const struct mma8452_event_regs *ev_regs;
979 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
983 ret = mma8452_set_runtime_pm_state(data->client, state);
988 case IIO_EV_DIR_FALLING:
989 return mma8452_set_freefall_mode(data, state);
990 case IIO_EV_DIR_RISING:
991 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
996 if (mma8452_freefall_mode_enabled(data)) {
997 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
998 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
999 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
1000 val |= MMA8452_FF_MT_CFG_OAE;
1002 val |= BIT(chan->scan_index +
1003 ev_regs->ev_cfg_chan_shift);
1005 if (mma8452_freefall_mode_enabled(data))
1008 val &= ~BIT(chan->scan_index +
1009 ev_regs->ev_cfg_chan_shift);
1012 val |= ev_regs->ev_cfg_ele;
1014 return mma8452_change_config(data, ev_regs->ev_cfg, val);
1020 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1022 struct mma8452_data *data = iio_priv(indio_dev);
1023 s64 ts = iio_get_time_ns(indio_dev);
1026 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1030 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1031 iio_push_event(indio_dev,
1032 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1037 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1038 iio_push_event(indio_dev,
1039 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1044 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1045 iio_push_event(indio_dev,
1046 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1052 static irqreturn_t mma8452_interrupt(int irq, void *p)
1054 struct iio_dev *indio_dev = p;
1055 struct mma8452_data *data = iio_priv(indio_dev);
1059 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1063 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1066 if (src & MMA8452_INT_DRDY) {
1067 iio_trigger_poll_chained(indio_dev->trig);
1071 if (src & MMA8452_INT_FF_MT) {
1072 if (mma8452_freefall_mode_enabled(data)) {
1073 s64 ts = iio_get_time_ns(indio_dev);
1075 iio_push_event(indio_dev,
1076 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1077 IIO_MOD_X_AND_Y_AND_Z,
1079 IIO_EV_DIR_FALLING),
1085 if (src & MMA8452_INT_TRANS) {
1086 mma8452_transient_interrupt(indio_dev);
1093 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1095 struct iio_poll_func *pf = p;
1096 struct iio_dev *indio_dev = pf->indio_dev;
1097 struct mma8452_data *data = iio_priv(indio_dev);
1100 ret = mma8452_read(data, data->buffer.channels);
1104 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1105 iio_get_time_ns(indio_dev));
1108 iio_trigger_notify_done(indio_dev->trig);
1113 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1114 unsigned int reg, unsigned int writeval,
1115 unsigned int *readval)
1118 struct mma8452_data *data = iio_priv(indio_dev);
1120 if (reg > MMA8452_MAX_REG)
1124 return mma8452_change_config(data, reg, writeval);
1126 ret = i2c_smbus_read_byte_data(data->client, reg);
1135 static const struct iio_event_spec mma8452_freefall_event[] = {
1137 .type = IIO_EV_TYPE_MAG,
1138 .dir = IIO_EV_DIR_FALLING,
1139 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1140 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1141 BIT(IIO_EV_INFO_PERIOD) |
1142 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1146 static const struct iio_event_spec mma8652_freefall_event[] = {
1148 .type = IIO_EV_TYPE_MAG,
1149 .dir = IIO_EV_DIR_FALLING,
1150 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1151 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1152 BIT(IIO_EV_INFO_PERIOD)
1156 static const struct iio_event_spec mma8452_transient_event[] = {
1158 .type = IIO_EV_TYPE_MAG,
1159 .dir = IIO_EV_DIR_RISING,
1160 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1161 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1162 BIT(IIO_EV_INFO_PERIOD) |
1163 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1167 static const struct iio_event_spec mma8452_motion_event[] = {
1169 .type = IIO_EV_TYPE_MAG,
1170 .dir = IIO_EV_DIR_RISING,
1171 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1172 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1173 BIT(IIO_EV_INFO_PERIOD)
1178 * Threshold is configured in fixed 8G/127 steps regardless of
1179 * currently selected scale for measurement.
1181 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1183 static struct attribute *mma8452_event_attributes[] = {
1184 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1188 static const struct attribute_group mma8452_event_attribute_group = {
1189 .attrs = mma8452_event_attributes,
1192 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1193 .type = IIO_ACCEL, \
1195 .channel2 = modifier, \
1197 .event_spec = mma8452_freefall_event, \
1198 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1201 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1202 .type = IIO_ACCEL, \
1204 .channel2 = modifier, \
1206 .event_spec = mma8652_freefall_event, \
1207 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1210 #define MMA8452_CHANNEL(axis, idx, bits) { \
1211 .type = IIO_ACCEL, \
1213 .channel2 = IIO_MOD_##axis, \
1214 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1215 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1216 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1217 BIT(IIO_CHAN_INFO_SCALE) | \
1218 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1219 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1220 .scan_index = idx, \
1223 .realbits = (bits), \
1224 .storagebits = 16, \
1225 .shift = 16 - (bits), \
1226 .endianness = IIO_BE, \
1228 .event_spec = mma8452_transient_event, \
1229 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1232 #define MMA8652_CHANNEL(axis, idx, bits) { \
1233 .type = IIO_ACCEL, \
1235 .channel2 = IIO_MOD_##axis, \
1236 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1237 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1238 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1239 BIT(IIO_CHAN_INFO_SCALE) | \
1240 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1241 .scan_index = idx, \
1244 .realbits = (bits), \
1245 .storagebits = 16, \
1246 .shift = 16 - (bits), \
1247 .endianness = IIO_BE, \
1249 .event_spec = mma8452_motion_event, \
1250 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1253 static const struct iio_chan_spec mma8451_channels[] = {
1254 MMA8452_CHANNEL(X, idx_x, 14),
1255 MMA8452_CHANNEL(Y, idx_y, 14),
1256 MMA8452_CHANNEL(Z, idx_z, 14),
1257 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1258 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1261 static const struct iio_chan_spec mma8452_channels[] = {
1262 MMA8452_CHANNEL(X, idx_x, 12),
1263 MMA8452_CHANNEL(Y, idx_y, 12),
1264 MMA8452_CHANNEL(Z, idx_z, 12),
1265 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1266 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1269 static const struct iio_chan_spec mma8453_channels[] = {
1270 MMA8452_CHANNEL(X, idx_x, 10),
1271 MMA8452_CHANNEL(Y, idx_y, 10),
1272 MMA8452_CHANNEL(Z, idx_z, 10),
1273 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1274 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1277 static const struct iio_chan_spec mma8652_channels[] = {
1278 MMA8652_CHANNEL(X, idx_x, 12),
1279 MMA8652_CHANNEL(Y, idx_y, 12),
1280 MMA8652_CHANNEL(Z, idx_z, 12),
1281 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1282 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1285 static const struct iio_chan_spec mma8653_channels[] = {
1286 MMA8652_CHANNEL(X, idx_x, 10),
1287 MMA8652_CHANNEL(Y, idx_y, 10),
1288 MMA8652_CHANNEL(Z, idx_z, 10),
1289 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1290 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1302 static const struct mma_chip_info mma_chip_info_table[] = {
1304 .chip_id = MMA8451_DEVICE_ID,
1305 .channels = mma8451_channels,
1306 .num_channels = ARRAY_SIZE(mma8451_channels),
1308 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1309 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1311 * The userspace interface uses m/s^2 and we declare micro units
1312 * So scale factor for 12 bit here is given by:
1313 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1315 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1317 * Although we enable the interrupt sources once and for
1318 * all here the event detection itself is not enabled until
1319 * userspace asks for it by mma8452_write_event_config()
1321 .all_events = MMA8452_INT_DRDY |
1324 .enabled_events = MMA8452_INT_TRANS |
1328 .chip_id = MMA8452_DEVICE_ID,
1329 .channels = mma8452_channels,
1330 .num_channels = ARRAY_SIZE(mma8452_channels),
1331 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1333 * Although we enable the interrupt sources once and for
1334 * all here the event detection itself is not enabled until
1335 * userspace asks for it by mma8452_write_event_config()
1337 .all_events = MMA8452_INT_DRDY |
1340 .enabled_events = MMA8452_INT_TRANS |
1344 .chip_id = MMA8453_DEVICE_ID,
1345 .channels = mma8453_channels,
1346 .num_channels = ARRAY_SIZE(mma8453_channels),
1347 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1349 * Although we enable the interrupt sources once and for
1350 * all here the event detection itself is not enabled until
1351 * userspace asks for it by mma8452_write_event_config()
1353 .all_events = MMA8452_INT_DRDY |
1356 .enabled_events = MMA8452_INT_TRANS |
1360 .chip_id = MMA8652_DEVICE_ID,
1361 .channels = mma8652_channels,
1362 .num_channels = ARRAY_SIZE(mma8652_channels),
1363 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1364 .all_events = MMA8452_INT_DRDY |
1366 .enabled_events = MMA8452_INT_FF_MT,
1369 .chip_id = MMA8653_DEVICE_ID,
1370 .channels = mma8653_channels,
1371 .num_channels = ARRAY_SIZE(mma8653_channels),
1372 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1374 * Although we enable the interrupt sources once and for
1375 * all here the event detection itself is not enabled until
1376 * userspace asks for it by mma8452_write_event_config()
1378 .all_events = MMA8452_INT_DRDY |
1380 .enabled_events = MMA8452_INT_FF_MT,
1383 .chip_id = FXLS8471_DEVICE_ID,
1384 .channels = mma8451_channels,
1385 .num_channels = ARRAY_SIZE(mma8451_channels),
1386 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1388 * Although we enable the interrupt sources once and for
1389 * all here the event detection itself is not enabled until
1390 * userspace asks for it by mma8452_write_event_config()
1392 .all_events = MMA8452_INT_DRDY |
1395 .enabled_events = MMA8452_INT_TRANS |
1400 static struct attribute *mma8452_attributes[] = {
1401 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1402 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1403 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1404 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1408 static const struct attribute_group mma8452_group = {
1409 .attrs = mma8452_attributes,
1412 static const struct iio_info mma8452_info = {
1413 .attrs = &mma8452_group,
1414 .read_raw = &mma8452_read_raw,
1415 .write_raw = &mma8452_write_raw,
1416 .event_attrs = &mma8452_event_attribute_group,
1417 .read_event_value = &mma8452_read_event_value,
1418 .write_event_value = &mma8452_write_event_value,
1419 .read_event_config = &mma8452_read_event_config,
1420 .write_event_config = &mma8452_write_event_config,
1421 .debugfs_reg_access = &mma8452_reg_access_dbg,
1424 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1426 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1429 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1430 struct mma8452_data *data = iio_priv(indio_dev);
1433 ret = mma8452_set_runtime_pm_state(data->client, state);
1437 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1442 reg |= MMA8452_INT_DRDY;
1444 reg &= ~MMA8452_INT_DRDY;
1446 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1449 static const struct iio_trigger_ops mma8452_trigger_ops = {
1450 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1451 .validate_device = iio_trigger_validate_own_device,
1454 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1456 struct mma8452_data *data = iio_priv(indio_dev);
1457 struct iio_trigger *trig;
1460 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1462 iio_device_id(indio_dev));
1466 trig->ops = &mma8452_trigger_ops;
1467 iio_trigger_set_drvdata(trig, indio_dev);
1469 ret = iio_trigger_register(trig);
1473 indio_dev->trig = trig;
1478 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1480 if (indio_dev->trig)
1481 iio_trigger_unregister(indio_dev->trig);
1484 static int mma8452_reset(struct i2c_client *client)
1489 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1490 MMA8452_CTRL_REG2_RST);
1494 for (i = 0; i < 10; i++) {
1495 usleep_range(100, 200);
1496 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1498 continue; /* I2C comm reset */
1501 if (!(ret & MMA8452_CTRL_REG2_RST))
1508 static const struct of_device_id mma8452_dt_ids[] = {
1509 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1510 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1511 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1512 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1513 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1514 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1517 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1519 static int mma8452_probe(struct i2c_client *client,
1520 const struct i2c_device_id *id)
1522 struct mma8452_data *data;
1523 struct iio_dev *indio_dev;
1525 const struct of_device_id *match;
1527 match = of_match_device(mma8452_dt_ids, &client->dev);
1529 dev_err(&client->dev, "unknown device model\n");
1533 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1537 data = iio_priv(indio_dev);
1538 data->client = client;
1539 mutex_init(&data->lock);
1540 data->chip_info = match->data;
1542 data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
1543 if (IS_ERR(data->vdd_reg))
1544 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg),
1545 "failed to get VDD regulator!\n");
1547 data->vddio_reg = devm_regulator_get(&client->dev, "vddio");
1548 if (IS_ERR(data->vddio_reg))
1549 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg),
1550 "failed to get VDDIO regulator!\n");
1552 ret = regulator_enable(data->vdd_reg);
1554 dev_err(&client->dev, "failed to enable VDD regulator!\n");
1558 ret = regulator_enable(data->vddio_reg);
1560 dev_err(&client->dev, "failed to enable VDDIO regulator!\n");
1561 goto disable_regulator_vdd;
1564 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1566 goto disable_regulators;
1569 case MMA8451_DEVICE_ID:
1570 case MMA8452_DEVICE_ID:
1571 case MMA8453_DEVICE_ID:
1572 case MMA8652_DEVICE_ID:
1573 case MMA8653_DEVICE_ID:
1574 case FXLS8471_DEVICE_ID:
1575 if (ret == data->chip_info->chip_id)
1580 goto disable_regulators;
1583 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1584 match->compatible, data->chip_info->chip_id);
1586 i2c_set_clientdata(client, indio_dev);
1587 indio_dev->info = &mma8452_info;
1588 indio_dev->name = id->name;
1589 indio_dev->modes = INDIO_DIRECT_MODE;
1590 indio_dev->channels = data->chip_info->channels;
1591 indio_dev->num_channels = data->chip_info->num_channels;
1592 indio_dev->available_scan_masks = mma8452_scan_masks;
1594 ret = mma8452_reset(client);
1596 goto disable_regulators;
1598 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1599 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1602 goto disable_regulators;
1605 * By default set transient threshold to max to avoid events if
1606 * enabling without configuring threshold.
1608 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1609 MMA8452_TRANSIENT_THS_MASK);
1611 goto disable_regulators;
1616 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1618 if (irq2 == client->irq) {
1619 dev_dbg(&client->dev, "using interrupt line INT2\n");
1621 ret = i2c_smbus_write_byte_data(client,
1623 data->chip_info->all_events);
1625 goto disable_regulators;
1627 dev_dbg(&client->dev, "using interrupt line INT1\n");
1630 ret = i2c_smbus_write_byte_data(client,
1632 data->chip_info->enabled_events);
1634 goto disable_regulators;
1636 ret = mma8452_trigger_setup(indio_dev);
1638 goto disable_regulators;
1641 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1642 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1644 data->sleep_val = mma8452_calculate_sleep(data);
1646 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1649 goto trigger_cleanup;
1651 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1652 mma8452_trigger_handler, NULL);
1654 goto trigger_cleanup;
1657 ret = devm_request_threaded_irq(&client->dev,
1659 NULL, mma8452_interrupt,
1660 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1661 client->name, indio_dev);
1663 goto buffer_cleanup;
1666 ret = pm_runtime_set_active(&client->dev);
1668 goto buffer_cleanup;
1670 pm_runtime_enable(&client->dev);
1671 pm_runtime_set_autosuspend_delay(&client->dev,
1672 MMA8452_AUTO_SUSPEND_DELAY_MS);
1673 pm_runtime_use_autosuspend(&client->dev);
1675 ret = iio_device_register(indio_dev);
1677 goto buffer_cleanup;
1679 ret = mma8452_set_freefall_mode(data, false);
1681 goto unregister_device;
1686 iio_device_unregister(indio_dev);
1689 iio_triggered_buffer_cleanup(indio_dev);
1692 mma8452_trigger_cleanup(indio_dev);
1695 regulator_disable(data->vddio_reg);
1697 disable_regulator_vdd:
1698 regulator_disable(data->vdd_reg);
1703 static int mma8452_remove(struct i2c_client *client)
1705 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1706 struct mma8452_data *data = iio_priv(indio_dev);
1708 iio_device_unregister(indio_dev);
1710 pm_runtime_disable(&client->dev);
1711 pm_runtime_set_suspended(&client->dev);
1713 iio_triggered_buffer_cleanup(indio_dev);
1714 mma8452_trigger_cleanup(indio_dev);
1715 mma8452_standby(iio_priv(indio_dev));
1717 regulator_disable(data->vddio_reg);
1718 regulator_disable(data->vdd_reg);
1724 static int mma8452_runtime_suspend(struct device *dev)
1726 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1727 struct mma8452_data *data = iio_priv(indio_dev);
1730 mutex_lock(&data->lock);
1731 ret = mma8452_standby(data);
1732 mutex_unlock(&data->lock);
1734 dev_err(&data->client->dev, "powering off device failed\n");
1738 ret = regulator_disable(data->vddio_reg);
1740 dev_err(dev, "failed to disable VDDIO regulator\n");
1744 ret = regulator_disable(data->vdd_reg);
1746 dev_err(dev, "failed to disable VDD regulator\n");
1753 static int mma8452_runtime_resume(struct device *dev)
1755 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1756 struct mma8452_data *data = iio_priv(indio_dev);
1759 ret = regulator_enable(data->vdd_reg);
1761 dev_err(dev, "failed to enable VDD regulator\n");
1765 ret = regulator_enable(data->vddio_reg);
1767 dev_err(dev, "failed to enable VDDIO regulator\n");
1768 regulator_disable(data->vdd_reg);
1772 ret = mma8452_active(data);
1774 goto runtime_resume_failed;
1776 ret = mma8452_get_odr_index(data);
1777 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1779 usleep_range(sleep_val * 1000, 20000);
1781 msleep_interruptible(sleep_val);
1785 runtime_resume_failed:
1786 regulator_disable(data->vddio_reg);
1787 regulator_disable(data->vdd_reg);
1793 static const struct dev_pm_ops mma8452_pm_ops = {
1794 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1795 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1796 mma8452_runtime_resume, NULL)
1799 static const struct i2c_device_id mma8452_id[] = {
1800 { "mma8451", mma8451 },
1801 { "mma8452", mma8452 },
1802 { "mma8453", mma8453 },
1803 { "mma8652", mma8652 },
1804 { "mma8653", mma8653 },
1805 { "fxls8471", fxls8471 },
1808 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1810 static struct i2c_driver mma8452_driver = {
1813 .of_match_table = of_match_ptr(mma8452_dt_ids),
1814 .pm = &mma8452_pm_ops,
1816 .probe = mma8452_probe,
1817 .remove = mma8452_remove,
1818 .id_table = mma8452_id,
1820 module_i2c_driver(mma8452_driver);
1822 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1823 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1824 MODULE_LICENSE("GPL");