2 * mma8452.c - Support for Freescale MMA8452Q 3-axis 12-bit accelerometer
4 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
6 * This file is subject to the terms and conditions of version 2 of
7 * the GNU General Public License. See the file COPYING in the main
8 * directory of this archive for more details.
10 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
12 * TODO: orientation / freefall events, autosleep
15 #include <linux/module.h>
16 #include <linux/i2c.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/sysfs.h>
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/trigger.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/triggered_buffer.h>
23 #include <linux/iio/events.h>
24 #include <linux/delay.h>
26 #define MMA8452_STATUS 0x00
27 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
28 #define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */
29 #define MMA8452_OUT_Y 0x03
30 #define MMA8452_OUT_Z 0x05
31 #define MMA8452_INT_SRC 0x0c
32 #define MMA8452_WHO_AM_I 0x0d
33 #define MMA8452_DATA_CFG 0x0e
34 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
35 #define MMA8452_DATA_CFG_FS_2G 0
36 #define MMA8452_DATA_CFG_FS_4G 1
37 #define MMA8452_DATA_CFG_FS_8G 2
38 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
39 #define MMA8452_HP_FILTER_CUTOFF 0x0f
40 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
41 #define MMA8452_TRANSIENT_CFG 0x1d
42 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
43 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
44 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
45 #define MMA8452_TRANSIENT_SRC 0x1e
46 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
47 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
48 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
49 #define MMA8452_TRANSIENT_THS 0x1f
50 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
51 #define MMA8452_TRANSIENT_COUNT 0x20
52 #define MMA8452_CTRL_REG1 0x2a
53 #define MMA8452_CTRL_ACTIVE BIT(0)
54 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
55 #define MMA8452_CTRL_DR_SHIFT 3
56 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
57 #define MMA8452_CTRL_REG2 0x2b
58 #define MMA8452_CTRL_REG2_RST BIT(6)
59 #define MMA8452_CTRL_REG4 0x2d
60 #define MMA8452_CTRL_REG5 0x2e
61 #define MMA8452_OFF_X 0x2f
62 #define MMA8452_OFF_Y 0x30
63 #define MMA8452_OFF_Z 0x31
65 #define MMA8452_MAX_REG 0x31
67 #define MMA8452_INT_DRDY BIT(0)
68 #define MMA8452_INT_TRANS BIT(5)
70 #define MMA8452_DEVICE_ID 0x2a
73 struct i2c_client *client;
79 static int mma8452_drdy(struct mma8452_data *data)
84 int ret = i2c_smbus_read_byte_data(data->client,
88 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
93 dev_err(&data->client->dev, "data not ready\n");
97 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
99 int ret = mma8452_drdy(data);
102 return i2c_smbus_read_i2c_block_data(data->client,
103 MMA8452_OUT_X, 3 * sizeof(__be16), (u8 *) buf);
106 static ssize_t mma8452_show_int_plus_micros(char *buf,
107 const int (*vals)[2], int n)
112 len += scnprintf(buf + len, PAGE_SIZE - len,
113 "%d.%06d ", vals[n][0], vals[n][1]);
115 /* replace trailing space by newline */
121 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
125 if (val == vals[n][0] && val2 == vals[n][1])
131 static int mma8452_get_odr_index(struct mma8452_data *data)
133 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
134 MMA8452_CTRL_DR_SHIFT;
137 static const int mma8452_samp_freq[8][2] = {
138 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
139 {6, 250000}, {1, 560000}
143 * Hardware has fullscale of -2G, -4G, -8G corresponding to raw value -2048
144 * The userspace interface uses m/s^2 and we declare micro units
145 * So scale factor is given by:
146 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
148 static const int mma8452_scales[3][2] = {
149 {0, 9577}, {0, 19154}, {0, 38307}
152 /* Datasheet table 35 (step time vs sample frequency) */
153 static const int mma8452_transient_time_step_us[8] = {
164 /* Datasheet table 18 (normal mode) */
165 static const int mma8452_hp_filter_cutoff[8][4][2] = {
166 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
167 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
168 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
169 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
170 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
171 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
172 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
173 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
176 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
177 struct device_attribute *attr, char *buf)
179 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
180 ARRAY_SIZE(mma8452_samp_freq));
183 static ssize_t mma8452_show_scale_avail(struct device *dev,
184 struct device_attribute *attr, char *buf)
186 return mma8452_show_int_plus_micros(buf, mma8452_scales,
187 ARRAY_SIZE(mma8452_scales));
190 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
191 struct device_attribute *attr,
194 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
195 struct mma8452_data *data = iio_priv(indio_dev);
196 int i = mma8452_get_odr_index(data);
198 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
199 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
202 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
203 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
204 mma8452_show_scale_avail, NULL, 0);
205 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
206 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
208 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
211 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
212 ARRAY_SIZE(mma8452_samp_freq), val, val2);
215 static int mma8452_get_scale_index(struct mma8452_data *data,
218 return mma8452_get_int_plus_micros_index(mma8452_scales,
219 ARRAY_SIZE(mma8452_scales), val, val2);
222 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
225 int i = mma8452_get_odr_index(data);
227 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
228 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
231 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
235 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
239 i = mma8452_get_odr_index(data);
240 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
241 *hz = mma8452_hp_filter_cutoff[i][ret][0];
242 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
247 static int mma8452_read_raw(struct iio_dev *indio_dev,
248 struct iio_chan_spec const *chan,
249 int *val, int *val2, long mask)
251 struct mma8452_data *data = iio_priv(indio_dev);
256 case IIO_CHAN_INFO_RAW:
257 if (iio_buffer_enabled(indio_dev))
260 mutex_lock(&data->lock);
261 ret = mma8452_read(data, buffer);
262 mutex_unlock(&data->lock);
265 *val = sign_extend32(
266 be16_to_cpu(buffer[chan->scan_index]) >> 4, 11);
268 case IIO_CHAN_INFO_SCALE:
269 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
270 *val = mma8452_scales[i][0];
271 *val2 = mma8452_scales[i][1];
272 return IIO_VAL_INT_PLUS_MICRO;
273 case IIO_CHAN_INFO_SAMP_FREQ:
274 i = mma8452_get_odr_index(data);
275 *val = mma8452_samp_freq[i][0];
276 *val2 = mma8452_samp_freq[i][1];
277 return IIO_VAL_INT_PLUS_MICRO;
278 case IIO_CHAN_INFO_CALIBBIAS:
279 ret = i2c_smbus_read_byte_data(data->client, MMA8452_OFF_X +
283 *val = sign_extend32(ret, 7);
285 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
286 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
287 ret = mma8452_read_hp_filter(data, val, val2);
294 return IIO_VAL_INT_PLUS_MICRO;
299 static int mma8452_standby(struct mma8452_data *data)
301 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
302 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
305 static int mma8452_active(struct mma8452_data *data)
307 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
311 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
315 mutex_lock(&data->lock);
317 /* config can only be changed when in standby */
318 ret = mma8452_standby(data);
322 ret = i2c_smbus_write_byte_data(data->client, reg, val);
326 ret = mma8452_active(data);
332 mutex_unlock(&data->lock);
336 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
341 i = mma8452_get_hp_filter_index(data, val, val2);
345 reg = i2c_smbus_read_byte_data(data->client,
346 MMA8452_HP_FILTER_CUTOFF);
349 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
352 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
355 static int mma8452_write_raw(struct iio_dev *indio_dev,
356 struct iio_chan_spec const *chan,
357 int val, int val2, long mask)
359 struct mma8452_data *data = iio_priv(indio_dev);
362 if (iio_buffer_enabled(indio_dev))
366 case IIO_CHAN_INFO_SAMP_FREQ:
367 i = mma8452_get_samp_freq_index(data, val, val2);
371 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
372 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
373 return mma8452_change_config(data, MMA8452_CTRL_REG1,
375 case IIO_CHAN_INFO_SCALE:
376 i = mma8452_get_scale_index(data, val, val2);
379 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
381 return mma8452_change_config(data, MMA8452_DATA_CFG,
383 case IIO_CHAN_INFO_CALIBBIAS:
384 if (val < -128 || val > 127)
386 return mma8452_change_config(data, MMA8452_OFF_X +
387 chan->scan_index, val);
389 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
390 if (val == 0 && val2 == 0) {
391 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
393 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
394 ret = mma8452_set_hp_filter_frequency(data, val, val2);
398 return mma8452_change_config(data, MMA8452_DATA_CFG,
406 static int mma8452_read_thresh(struct iio_dev *indio_dev,
407 const struct iio_chan_spec *chan,
408 enum iio_event_type type,
409 enum iio_event_direction dir,
410 enum iio_event_info info,
413 struct mma8452_data *data = iio_priv(indio_dev);
417 case IIO_EV_INFO_VALUE:
418 ret = i2c_smbus_read_byte_data(data->client,
419 MMA8452_TRANSIENT_THS);
423 *val = ret & MMA8452_TRANSIENT_THS_MASK;
426 case IIO_EV_INFO_PERIOD:
427 ret = i2c_smbus_read_byte_data(data->client,
428 MMA8452_TRANSIENT_COUNT);
432 us = ret * mma8452_transient_time_step_us[
433 mma8452_get_odr_index(data)];
434 *val = us / USEC_PER_SEC;
435 *val2 = us % USEC_PER_SEC;
436 return IIO_VAL_INT_PLUS_MICRO;
438 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
439 ret = i2c_smbus_read_byte_data(data->client,
440 MMA8452_TRANSIENT_CFG);
444 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
448 ret = mma8452_read_hp_filter(data, val, val2);
452 return IIO_VAL_INT_PLUS_MICRO;
459 static int mma8452_write_thresh(struct iio_dev *indio_dev,
460 const struct iio_chan_spec *chan,
461 enum iio_event_type type,
462 enum iio_event_direction dir,
463 enum iio_event_info info,
466 struct mma8452_data *data = iio_priv(indio_dev);
470 case IIO_EV_INFO_VALUE:
471 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
474 return mma8452_change_config(data, MMA8452_TRANSIENT_THS, val);
476 case IIO_EV_INFO_PERIOD:
477 steps = (val * USEC_PER_SEC + val2) /
478 mma8452_transient_time_step_us[
479 mma8452_get_odr_index(data)];
481 if (steps < 0 || steps > 0xff)
484 return mma8452_change_config(data, MMA8452_TRANSIENT_COUNT,
486 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
487 reg = i2c_smbus_read_byte_data(data->client,
488 MMA8452_TRANSIENT_CFG);
492 if (val == 0 && val2 == 0) {
493 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
495 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
496 ret = mma8452_set_hp_filter_frequency(data, val, val2);
500 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
507 static int mma8452_read_event_config(struct iio_dev *indio_dev,
508 const struct iio_chan_spec *chan,
509 enum iio_event_type type,
510 enum iio_event_direction dir)
512 struct mma8452_data *data = iio_priv(indio_dev);
515 ret = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
519 return ret & MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index) ? 1 : 0;
522 static int mma8452_write_event_config(struct iio_dev *indio_dev,
523 const struct iio_chan_spec *chan,
524 enum iio_event_type type,
525 enum iio_event_direction dir,
528 struct mma8452_data *data = iio_priv(indio_dev);
531 val = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
536 val |= MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
538 val &= ~MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
540 val |= MMA8452_TRANSIENT_CFG_ELE;
542 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, val);
545 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
547 struct mma8452_data *data = iio_priv(indio_dev);
548 s64 ts = iio_get_time_ns();
551 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
555 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
556 iio_push_event(indio_dev,
557 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
562 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
563 iio_push_event(indio_dev,
564 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
569 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
570 iio_push_event(indio_dev,
571 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
577 static irqreturn_t mma8452_interrupt(int irq, void *p)
579 struct iio_dev *indio_dev = p;
580 struct mma8452_data *data = iio_priv(indio_dev);
584 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
588 if (src & MMA8452_INT_DRDY) {
589 iio_trigger_poll_chained(indio_dev->trig);
593 if (src & MMA8452_INT_TRANS) {
594 mma8452_transient_interrupt(indio_dev);
601 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
603 struct iio_poll_func *pf = p;
604 struct iio_dev *indio_dev = pf->indio_dev;
605 struct mma8452_data *data = iio_priv(indio_dev);
606 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
609 ret = mma8452_read(data, (__be16 *) buffer);
613 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
617 iio_trigger_notify_done(indio_dev->trig);
621 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
622 unsigned reg, unsigned writeval,
626 struct mma8452_data *data = iio_priv(indio_dev);
628 if (reg > MMA8452_MAX_REG)
632 return mma8452_change_config(data, reg, writeval);
634 ret = i2c_smbus_read_byte_data(data->client, reg);
643 static const struct iio_event_spec mma8452_transient_event[] = {
645 .type = IIO_EV_TYPE_THRESH,
646 .dir = IIO_EV_DIR_RISING,
647 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
648 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
649 BIT(IIO_EV_INFO_PERIOD) |
650 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
655 * Threshold is configured in fixed 8G/127 steps regardless of
656 * currently selected scale for measurement.
658 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
660 static struct attribute *mma8452_event_attributes[] = {
661 &iio_const_attr_accel_transient_scale.dev_attr.attr,
665 static struct attribute_group mma8452_event_attribute_group = {
666 .attrs = mma8452_event_attributes,
670 #define MMA8452_CHANNEL(axis, idx) { \
673 .channel2 = IIO_MOD_##axis, \
674 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
675 BIT(IIO_CHAN_INFO_CALIBBIAS), \
676 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
677 BIT(IIO_CHAN_INFO_SCALE) | \
678 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
685 .endianness = IIO_BE, \
687 .event_spec = mma8452_transient_event, \
688 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
691 static const struct iio_chan_spec mma8452_channels[] = {
692 MMA8452_CHANNEL(X, 0),
693 MMA8452_CHANNEL(Y, 1),
694 MMA8452_CHANNEL(Z, 2),
695 IIO_CHAN_SOFT_TIMESTAMP(3),
698 static struct attribute *mma8452_attributes[] = {
699 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
700 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
701 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
705 static const struct attribute_group mma8452_group = {
706 .attrs = mma8452_attributes,
709 static const struct iio_info mma8452_info = {
710 .attrs = &mma8452_group,
711 .read_raw = &mma8452_read_raw,
712 .write_raw = &mma8452_write_raw,
713 .event_attrs = &mma8452_event_attribute_group,
714 .read_event_value = &mma8452_read_thresh,
715 .write_event_value = &mma8452_write_thresh,
716 .read_event_config = &mma8452_read_event_config,
717 .write_event_config = &mma8452_write_event_config,
718 .debugfs_reg_access = &mma8452_reg_access_dbg,
719 .driver_module = THIS_MODULE,
722 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
724 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
727 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
728 struct mma8452_data *data = iio_priv(indio_dev);
731 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
736 reg |= MMA8452_INT_DRDY;
738 reg &= ~MMA8452_INT_DRDY;
740 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
743 static int mma8452_validate_device(struct iio_trigger *trig,
744 struct iio_dev *indio_dev)
746 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
748 if (indio != indio_dev)
754 static const struct iio_trigger_ops mma8452_trigger_ops = {
755 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
756 .validate_device = mma8452_validate_device,
757 .owner = THIS_MODULE,
760 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
762 struct mma8452_data *data = iio_priv(indio_dev);
763 struct iio_trigger *trig;
766 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
772 trig->dev.parent = &data->client->dev;
773 trig->ops = &mma8452_trigger_ops;
774 iio_trigger_set_drvdata(trig, indio_dev);
776 ret = iio_trigger_register(trig);
780 indio_dev->trig = trig;
784 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
787 iio_trigger_unregister(indio_dev->trig);
790 static int mma8452_reset(struct i2c_client *client)
795 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
796 MMA8452_CTRL_REG2_RST);
800 for (i = 0; i < 10; i++) {
801 usleep_range(100, 200);
802 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
804 continue; /* I2C comm reset */
807 if (!(ret & MMA8452_CTRL_REG2_RST))
814 static int mma8452_probe(struct i2c_client *client,
815 const struct i2c_device_id *id)
817 struct mma8452_data *data;
818 struct iio_dev *indio_dev;
821 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
824 if (ret != MMA8452_DEVICE_ID)
827 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
831 data = iio_priv(indio_dev);
832 data->client = client;
833 mutex_init(&data->lock);
835 i2c_set_clientdata(client, indio_dev);
836 indio_dev->info = &mma8452_info;
837 indio_dev->name = id->name;
838 indio_dev->dev.parent = &client->dev;
839 indio_dev->modes = INDIO_DIRECT_MODE;
840 indio_dev->channels = mma8452_channels;
841 indio_dev->num_channels = ARRAY_SIZE(mma8452_channels);
842 indio_dev->available_scan_masks = mma8452_scan_masks;
844 ret = mma8452_reset(client);
848 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
849 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
855 * By default set transient threshold to max to avoid events if
856 * enabling without configuring threshold.
858 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
859 MMA8452_TRANSIENT_THS_MASK);
865 * Although we enable the transient interrupt source once and
866 * for all here the transient event detection itself is not
867 * enabled until userspace asks for it by
868 * mma8452_write_event_config()
870 int supported_interrupts = MMA8452_INT_DRDY | MMA8452_INT_TRANS;
871 int enabled_interrupts = MMA8452_INT_TRANS;
873 /* Assume wired to INT1 pin */
874 ret = i2c_smbus_write_byte_data(client,
876 supported_interrupts);
880 ret = i2c_smbus_write_byte_data(client,
886 ret = mma8452_trigger_setup(indio_dev);
891 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
892 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
893 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
896 goto trigger_cleanup;
898 ret = iio_triggered_buffer_setup(indio_dev, NULL,
899 mma8452_trigger_handler, NULL);
901 goto trigger_cleanup;
904 ret = devm_request_threaded_irq(&client->dev,
906 NULL, mma8452_interrupt,
907 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
908 client->name, indio_dev);
913 ret = iio_device_register(indio_dev);
920 iio_triggered_buffer_cleanup(indio_dev);
923 mma8452_trigger_cleanup(indio_dev);
928 static int mma8452_remove(struct i2c_client *client)
930 struct iio_dev *indio_dev = i2c_get_clientdata(client);
932 iio_device_unregister(indio_dev);
933 iio_triggered_buffer_cleanup(indio_dev);
934 mma8452_trigger_cleanup(indio_dev);
935 mma8452_standby(iio_priv(indio_dev));
940 #ifdef CONFIG_PM_SLEEP
941 static int mma8452_suspend(struct device *dev)
943 return mma8452_standby(iio_priv(i2c_get_clientdata(
944 to_i2c_client(dev))));
947 static int mma8452_resume(struct device *dev)
949 return mma8452_active(iio_priv(i2c_get_clientdata(
950 to_i2c_client(dev))));
953 static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
954 #define MMA8452_PM_OPS (&mma8452_pm_ops)
956 #define MMA8452_PM_OPS NULL
959 static const struct i2c_device_id mma8452_id[] = {
963 MODULE_DEVICE_TABLE(i2c, mma8452_id);
965 static const struct of_device_id mma8452_dt_ids[] = {
966 { .compatible = "fsl,mma8452" },
969 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
971 static struct i2c_driver mma8452_driver = {
974 .of_match_table = of_match_ptr(mma8452_dt_ids),
975 .pm = MMA8452_PM_OPS,
977 .probe = mma8452_probe,
978 .remove = mma8452_remove,
979 .id_table = mma8452_id,
981 module_i2c_driver(mma8452_driver);
983 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
984 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
985 MODULE_LICENSE("GPL");