1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2021 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/iio/buffer.h>
10 #include <linux/iio/events.h>
11 #include <linux/iio/iio.h>
12 #include <linux/iio/kfifo_buf.h>
13 #include <linux/iio/sysfs.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <asm/unaligned.h>
23 #define ADXL367_REG_DEVID 0x00
24 #define ADXL367_DEVID_AD 0xAD
26 #define ADXL367_REG_STATUS 0x0B
27 #define ADXL367_STATUS_INACT_MASK BIT(5)
28 #define ADXL367_STATUS_ACT_MASK BIT(4)
29 #define ADXL367_STATUS_FIFO_FULL_MASK BIT(2)
31 #define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0)
33 #define ADXL367_REG_X_DATA_H 0x0E
34 #define ADXL367_REG_Y_DATA_H 0x10
35 #define ADXL367_REG_Z_DATA_H 0x12
36 #define ADXL367_REG_TEMP_DATA_H 0x14
37 #define ADXL367_REG_EX_ADC_DATA_H 0x16
38 #define ADXL367_DATA_MASK GENMASK(15, 2)
40 #define ADXL367_TEMP_25C 165
41 #define ADXL367_TEMP_PER_C 54
43 #define ADXL367_VOLTAGE_OFFSET 8192
44 #define ADXL367_VOLTAGE_MAX_MV 1000
45 #define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0)
47 #define ADXL367_REG_RESET 0x1F
48 #define ADXL367_RESET_CODE 0x52
50 #define ADXL367_REG_THRESH_ACT_H 0x20
51 #define ADXL367_REG_THRESH_INACT_H 0x23
52 #define ADXL367_THRESH_MAX GENMASK(12, 0)
53 #define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6)
54 #define ADXL367_THRESH_H_MASK GENMASK(6, 0)
55 #define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0)
56 #define ADXL367_THRESH_L_MASK GENMASK(7, 2)
58 #define ADXL367_REG_TIME_ACT 0x22
59 #define ADXL367_REG_TIME_INACT_H 0x25
60 #define ADXL367_TIME_ACT_MAX GENMASK(7, 0)
61 #define ADXL367_TIME_INACT_MAX GENMASK(15, 0)
62 #define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8)
63 #define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0)
64 #define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0)
65 #define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0)
67 #define ADXL367_REG_ACT_INACT_CTL 0x27
68 #define ADXL367_ACT_EN_MASK GENMASK(1, 0)
69 #define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4)
71 #define ADXL367_REG_FIFO_CTL 0x28
72 #define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3)
73 #define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0)
75 #define ADXL367_REG_FIFO_SAMPLES 0x29
76 #define ADXL367_FIFO_SIZE 512
77 #define ADXL367_FIFO_MAX_WATERMARK 511
79 #define ADXL367_SAMPLES_VAL_H_MASK BIT(8)
80 #define ADXL367_SAMPLES_H_MASK BIT(2)
81 #define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0)
82 #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0)
84 #define ADXL367_REG_INT1_MAP 0x2A
85 #define ADXL367_INT_INACT_MASK BIT(5)
86 #define ADXL367_INT_ACT_MASK BIT(4)
87 #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2)
89 #define ADXL367_REG_FILTER_CTL 0x2C
90 #define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6)
91 #define ADXL367_2G_RANGE_1G 4095
92 #define ADXL367_2G_RANGE_100MG 409
93 #define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0)
95 #define ADXL367_REG_POWER_CTL 0x2D
96 #define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0)
98 #define ADXL367_REG_ADC_CTL 0x3C
99 #define ADXL367_REG_TEMP_CTL 0x3D
100 #define ADXL367_ADC_EN_MASK BIT(0)
108 enum adxl367_fifo_mode {
109 ADXL367_FIFO_MODE_DISABLED = 0b00,
110 ADXL367_FIFO_MODE_STREAM = 0b10,
113 enum adxl367_fifo_format {
114 ADXL367_FIFO_FORMAT_XYZ,
115 ADXL367_FIFO_FORMAT_X,
116 ADXL367_FIFO_FORMAT_Y,
117 ADXL367_FIFO_FORMAT_Z,
118 ADXL367_FIFO_FORMAT_XYZT,
119 ADXL367_FIFO_FORMAT_XT,
120 ADXL367_FIFO_FORMAT_YT,
121 ADXL367_FIFO_FORMAT_ZT,
122 ADXL367_FIFO_FORMAT_XYZA,
123 ADXL367_FIFO_FORMAT_XA,
124 ADXL367_FIFO_FORMAT_YA,
125 ADXL367_FIFO_FORMAT_ZA,
128 enum adxl367_op_mode {
129 ADXL367_OP_STANDBY = 0b00,
130 ADXL367_OP_MEASURE = 0b10,
133 enum adxl367_act_proc_mode {
134 ADXL367_LOOPED = 0b11,
137 enum adxl367_act_en_mode {
138 ADXL367_ACT_DISABLED = 0b00,
139 ADCL367_ACT_REF_ENABLED = 0b11,
142 enum adxl367_activity_type {
156 struct adxl367_state {
157 const struct adxl367_ops *ops;
161 struct regmap *regmap;
164 * Synchronize access to members of driver state, and ensure atomicity
165 * of consecutive regmap operations.
169 enum adxl367_odr odr;
170 enum adxl367_range range;
172 unsigned int act_threshold;
173 unsigned int act_time_ms;
174 unsigned int inact_threshold;
175 unsigned int inact_time_ms;
177 unsigned int fifo_set_size;
178 unsigned int fifo_watermark;
180 __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
182 u8 act_threshold_buf[2];
183 u8 inact_time_buf[2];
187 static const unsigned int adxl367_threshold_h_reg_tbl[] = {
188 [ADXL367_ACTIVITY] = ADXL367_REG_THRESH_ACT_H,
189 [ADXL367_INACTIVITY] = ADXL367_REG_THRESH_INACT_H,
192 static const unsigned int adxl367_act_en_shift_tbl[] = {
193 [ADXL367_ACTIVITY] = 0,
194 [ADXL367_INACTIVITY] = 2,
197 static const unsigned int adxl367_act_int_mask_tbl[] = {
198 [ADXL367_ACTIVITY] = ADXL367_INT_ACT_MASK,
199 [ADXL367_INACTIVITY] = ADXL367_INT_INACT_MASK,
202 static const int adxl367_samp_freq_tbl[][2] = {
203 [ADXL367_ODR_12P5HZ] = {12, 500000},
204 [ADXL367_ODR_25HZ] = {25, 0},
205 [ADXL367_ODR_50HZ] = {50, 0},
206 [ADXL367_ODR_100HZ] = {100, 0},
207 [ADXL367_ODR_200HZ] = {200, 0},
208 [ADXL367_ODR_400HZ] = {400, 0},
211 /* (g * 2) * 9.80665 * 1000000 / (2^14 - 1) */
212 static const int adxl367_range_scale_tbl[][2] = {
213 [ADXL367_2G_RANGE] = {0, 2394347},
214 [ADXL367_4G_RANGE] = {0, 4788695},
215 [ADXL367_8G_RANGE] = {0, 9577391},
218 static const int adxl367_range_scale_factor_tbl[] = {
219 [ADXL367_2G_RANGE] = 1,
220 [ADXL367_4G_RANGE] = 2,
221 [ADXL367_8G_RANGE] = 4,
225 ADXL367_X_CHANNEL_INDEX,
226 ADXL367_Y_CHANNEL_INDEX,
227 ADXL367_Z_CHANNEL_INDEX,
228 ADXL367_TEMP_CHANNEL_INDEX,
229 ADXL367_EX_ADC_CHANNEL_INDEX
232 #define ADXL367_X_CHANNEL_MASK BIT(ADXL367_X_CHANNEL_INDEX)
233 #define ADXL367_Y_CHANNEL_MASK BIT(ADXL367_Y_CHANNEL_INDEX)
234 #define ADXL367_Z_CHANNEL_MASK BIT(ADXL367_Z_CHANNEL_INDEX)
235 #define ADXL367_TEMP_CHANNEL_MASK BIT(ADXL367_TEMP_CHANNEL_INDEX)
236 #define ADXL367_EX_ADC_CHANNEL_MASK BIT(ADXL367_EX_ADC_CHANNEL_INDEX)
238 static const enum adxl367_fifo_format adxl367_fifo_formats[] = {
239 ADXL367_FIFO_FORMAT_X,
240 ADXL367_FIFO_FORMAT_Y,
241 ADXL367_FIFO_FORMAT_Z,
242 ADXL367_FIFO_FORMAT_XT,
243 ADXL367_FIFO_FORMAT_YT,
244 ADXL367_FIFO_FORMAT_ZT,
245 ADXL367_FIFO_FORMAT_XA,
246 ADXL367_FIFO_FORMAT_YA,
247 ADXL367_FIFO_FORMAT_ZA,
248 ADXL367_FIFO_FORMAT_XYZ,
249 ADXL367_FIFO_FORMAT_XYZT,
250 ADXL367_FIFO_FORMAT_XYZA,
253 static const unsigned long adxl367_channel_masks[] = {
254 ADXL367_X_CHANNEL_MASK,
255 ADXL367_Y_CHANNEL_MASK,
256 ADXL367_Z_CHANNEL_MASK,
257 ADXL367_X_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
258 ADXL367_Y_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
259 ADXL367_Z_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
260 ADXL367_X_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
261 ADXL367_Y_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
262 ADXL367_Z_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
263 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK,
264 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
265 ADXL367_TEMP_CHANNEL_MASK,
266 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
267 ADXL367_EX_ADC_CHANNEL_MASK,
271 static int adxl367_set_measure_en(struct adxl367_state *st, bool en)
273 enum adxl367_op_mode op_mode = en ? ADXL367_OP_MEASURE
274 : ADXL367_OP_STANDBY;
277 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL,
278 ADXL367_POWER_CTL_MODE_MASK,
279 FIELD_PREP(ADXL367_POWER_CTL_MODE_MASK,
285 * Wait for acceleration output to settle after entering
294 static void adxl367_scale_act_thresholds(struct adxl367_state *st,
295 enum adxl367_range old_range,
296 enum adxl367_range new_range)
298 st->act_threshold = st->act_threshold
299 * adxl367_range_scale_factor_tbl[old_range]
300 / adxl367_range_scale_factor_tbl[new_range];
301 st->inact_threshold = st->inact_threshold
302 * adxl367_range_scale_factor_tbl[old_range]
303 / adxl367_range_scale_factor_tbl[new_range];
306 static int _adxl367_set_act_threshold(struct adxl367_state *st,
307 enum adxl367_activity_type act,
308 unsigned int threshold)
310 u8 reg = adxl367_threshold_h_reg_tbl[act];
313 if (threshold > ADXL367_THRESH_MAX)
316 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK,
317 FIELD_GET(ADXL367_THRESH_VAL_H_MASK,
319 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK,
320 FIELD_GET(ADXL367_THRESH_VAL_L_MASK,
323 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf,
324 sizeof(st->act_threshold_buf));
328 if (act == ADXL367_ACTIVITY)
329 st->act_threshold = threshold;
331 st->inact_threshold = threshold;
336 static int adxl367_set_act_threshold(struct adxl367_state *st,
337 enum adxl367_activity_type act,
338 unsigned int threshold)
342 mutex_lock(&st->lock);
344 ret = adxl367_set_measure_en(st, false);
348 ret = _adxl367_set_act_threshold(st, act, threshold);
352 ret = adxl367_set_measure_en(st, true);
355 mutex_unlock(&st->lock);
360 static int adxl367_set_act_proc_mode(struct adxl367_state *st,
361 enum adxl367_act_proc_mode mode)
363 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
364 ADXL367_ACT_LINKLOOP_MASK,
365 FIELD_PREP(ADXL367_ACT_LINKLOOP_MASK,
369 static int adxl367_set_act_interrupt_en(struct adxl367_state *st,
370 enum adxl367_activity_type act,
373 unsigned int mask = adxl367_act_int_mask_tbl[act];
375 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
376 mask, en ? mask : 0);
379 static int adxl367_get_act_interrupt_en(struct adxl367_state *st,
380 enum adxl367_activity_type act,
383 unsigned int mask = adxl367_act_int_mask_tbl[act];
387 ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);
391 *en = !!(val & mask);
396 static int adxl367_set_act_en(struct adxl367_state *st,
397 enum adxl367_activity_type act,
398 enum adxl367_act_en_mode en)
400 unsigned int ctl_shift = adxl367_act_en_shift_tbl[act];
402 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
403 ADXL367_ACT_EN_MASK << ctl_shift,
407 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,
410 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
411 ADXL367_INT_FIFO_WATERMARK_MASK,
412 en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0);
415 static int adxl367_get_fifo_mode(struct adxl367_state *st,
416 enum adxl367_fifo_mode *fifo_mode)
421 ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val);
425 *fifo_mode = FIELD_GET(ADXL367_FIFO_CTL_MODE_MASK, val);
430 static int adxl367_set_fifo_mode(struct adxl367_state *st,
431 enum adxl367_fifo_mode fifo_mode)
433 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
434 ADXL367_FIFO_CTL_MODE_MASK,
435 FIELD_PREP(ADXL367_FIFO_CTL_MODE_MASK,
439 static int adxl367_set_fifo_format(struct adxl367_state *st,
440 enum adxl367_fifo_format fifo_format)
442 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
443 ADXL367_FIFO_CTL_FORMAT_MASK,
444 FIELD_PREP(ADXL367_FIFO_CTL_FORMAT_MASK,
448 static int adxl367_set_fifo_watermark(struct adxl367_state *st,
449 unsigned int fifo_watermark)
451 unsigned int fifo_samples = fifo_watermark * st->fifo_set_size;
452 unsigned int fifo_samples_h, fifo_samples_l;
455 if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK)
456 fifo_samples = ADXL367_FIFO_MAX_WATERMARK;
458 fifo_samples /= st->fifo_set_size;
460 fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK,
461 FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK,
463 fifo_samples_l = FIELD_PREP(ADXL367_SAMPLES_L_MASK,
464 FIELD_GET(ADXL367_SAMPLES_VAL_L_MASK,
467 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
468 ADXL367_SAMPLES_H_MASK, fifo_samples_h);
472 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES,
473 ADXL367_SAMPLES_L_MASK, fifo_samples_l);
477 st->fifo_watermark = fifo_watermark;
482 static int adxl367_set_range(struct iio_dev *indio_dev,
483 enum adxl367_range range)
485 struct adxl367_state *st = iio_priv(indio_dev);
488 ret = iio_device_claim_direct_mode(indio_dev);
492 mutex_lock(&st->lock);
494 ret = adxl367_set_measure_en(st, false);
498 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
499 ADXL367_FILTER_CTL_RANGE_MASK,
500 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MASK,
505 adxl367_scale_act_thresholds(st, st->range, range);
507 /* Activity thresholds depend on range */
508 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
513 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
514 st->inact_threshold);
518 ret = adxl367_set_measure_en(st, true);
525 mutex_unlock(&st->lock);
527 iio_device_release_direct_mode(indio_dev);
532 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms)
534 int freq_hz = adxl367_samp_freq_tbl[st->odr][0];
535 int freq_microhz = adxl367_samp_freq_tbl[st->odr][1];
536 /* Scale to decihertz to prevent precision loss in 12.5Hz case. */
537 int freq_dhz = freq_hz * 10 + freq_microhz / 100000;
539 return DIV_ROUND_CLOSEST(ms * freq_dhz, 10000);
542 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms)
544 unsigned int val = adxl367_time_ms_to_samples(st, ms);
547 if (val > ADXL367_TIME_ACT_MAX)
548 val = ADXL367_TIME_ACT_MAX;
550 ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val);
554 st->act_time_ms = ms;
559 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms)
561 unsigned int val = adxl367_time_ms_to_samples(st, ms);
564 if (val > ADXL367_TIME_INACT_MAX)
565 val = ADXL367_TIME_INACT_MAX;
567 st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK,
568 FIELD_GET(ADXL367_TIME_INACT_VAL_H_MASK,
570 st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK,
571 FIELD_GET(ADXL367_TIME_INACT_VAL_L_MASK,
574 ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H,
575 st->inact_time_buf, sizeof(st->inact_time_buf));
579 st->inact_time_ms = ms;
584 static int adxl367_set_act_time_ms(struct adxl367_state *st,
585 enum adxl367_activity_type act,
590 mutex_lock(&st->lock);
592 ret = adxl367_set_measure_en(st, false);
596 if (act == ADXL367_ACTIVITY)
597 ret = _adxl367_set_act_time_ms(st, ms);
599 ret = _adxl367_set_inact_time_ms(st, ms);
604 ret = adxl367_set_measure_en(st, true);
607 mutex_unlock(&st->lock);
612 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr)
616 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
617 ADXL367_FILTER_CTL_ODR_MASK,
618 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MASK,
623 /* Activity timers depend on ODR */
624 ret = _adxl367_set_act_time_ms(st, st->act_time_ms);
628 ret = _adxl367_set_inact_time_ms(st, st->inact_time_ms);
637 static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr)
639 struct adxl367_state *st = iio_priv(indio_dev);
642 ret = iio_device_claim_direct_mode(indio_dev);
646 mutex_lock(&st->lock);
648 ret = adxl367_set_measure_en(st, false);
652 ret = _adxl367_set_odr(st, odr);
656 ret = adxl367_set_measure_en(st, true);
659 mutex_unlock(&st->lock);
661 iio_device_release_direct_mode(indio_dev);
666 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg,
669 return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK,
670 en ? ADXL367_ADC_EN_MASK : 0);
673 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st,
674 unsigned int reg, bool en)
679 case ADXL367_REG_TEMP_DATA_H:
680 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
682 case ADXL367_REG_EX_ADC_DATA_H:
683 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
698 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st,
699 const unsigned long *active_scan_mask,
702 if (*active_scan_mask & ADXL367_TEMP_CHANNEL_MASK)
703 return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
704 else if (*active_scan_mask & ADXL367_EX_ADC_CHANNEL_MASK)
705 return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
710 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2,
711 enum adxl367_odr *odr)
713 size_t size = ARRAY_SIZE(adxl367_samp_freq_tbl);
716 for (i = 0; i < size; i++)
717 if (val == adxl367_samp_freq_tbl[i][0] &&
718 val2 == adxl367_samp_freq_tbl[i][1])
729 static int adxl367_find_range(struct adxl367_state *st, int val, int val2,
730 enum adxl367_range *range)
732 size_t size = ARRAY_SIZE(adxl367_range_scale_tbl);
735 for (i = 0; i < size; i++)
736 if (val == adxl367_range_scale_tbl[i][0] &&
737 val2 == adxl367_range_scale_tbl[i][1])
748 static int adxl367_read_sample(struct iio_dev *indio_dev,
749 struct iio_chan_spec const *chan,
752 struct adxl367_state *st = iio_priv(indio_dev);
756 ret = iio_device_claim_direct_mode(indio_dev);
760 mutex_lock(&st->lock);
762 ret = adxl367_set_temp_adc_reg_en(st, chan->address, true);
766 ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf,
767 sizeof(st->sample_buf));
771 sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf));
772 *val = sign_extend32(sample, chan->scan_type.realbits - 1);
774 ret = adxl367_set_temp_adc_reg_en(st, chan->address, false);
777 mutex_unlock(&st->lock);
779 iio_device_release_direct_mode(indio_dev);
781 return ret ?: IIO_VAL_INT;
784 static int adxl367_get_status(struct adxl367_state *st, u8 *status,
789 /* Read STATUS, FIFO_ENT_L and FIFO_ENT_H */
790 ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS,
791 st->status_buf, sizeof(st->status_buf));
795 st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK;
797 *status = st->status_buf[0];
798 *fifo_entries = get_unaligned_le16(&st->status_buf[1]);
803 static bool adxl367_push_event(struct iio_dev *indio_dev, u8 status)
807 if (FIELD_GET(ADXL367_STATUS_ACT_MASK, status))
808 ev_dir = IIO_EV_DIR_RISING;
809 else if (FIELD_GET(ADXL367_STATUS_INACT_MASK, status))
810 ev_dir = IIO_EV_DIR_FALLING;
814 iio_push_event(indio_dev,
815 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
816 IIO_EV_TYPE_THRESH, ev_dir),
817 iio_get_time_ns(indio_dev));
822 static bool adxl367_push_fifo_data(struct iio_dev *indio_dev, u8 status,
825 struct adxl367_state *st = iio_priv(indio_dev);
829 if (!FIELD_GET(ADXL367_STATUS_FIFO_FULL_MASK, status))
832 fifo_entries -= fifo_entries % st->fifo_set_size;
834 ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries);
836 dev_err(st->dev, "Failed to read FIFO: %d\n", ret);
840 for (i = 0; i < fifo_entries; i += st->fifo_set_size)
841 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
846 static irqreturn_t adxl367_irq_handler(int irq, void *private)
848 struct iio_dev *indio_dev = private;
849 struct adxl367_state *st = iio_priv(indio_dev);
855 ret = adxl367_get_status(st, &status, &fifo_entries);
859 handled = adxl367_push_event(indio_dev, status);
860 handled |= adxl367_push_fifo_data(indio_dev, status, fifo_entries);
862 return handled ? IRQ_HANDLED : IRQ_NONE;
865 static int adxl367_reg_access(struct iio_dev *indio_dev,
867 unsigned int writeval,
868 unsigned int *readval)
870 struct adxl367_state *st = iio_priv(indio_dev);
873 return regmap_read(st->regmap, reg, readval);
875 return regmap_write(st->regmap, reg, writeval);
878 static int adxl367_read_raw(struct iio_dev *indio_dev,
879 struct iio_chan_spec const *chan,
880 int *val, int *val2, long info)
882 struct adxl367_state *st = iio_priv(indio_dev);
885 case IIO_CHAN_INFO_RAW:
886 return adxl367_read_sample(indio_dev, chan, val);
887 case IIO_CHAN_INFO_SCALE:
888 switch (chan->type) {
890 mutex_lock(&st->lock);
891 *val = adxl367_range_scale_tbl[st->range][0];
892 *val2 = adxl367_range_scale_tbl[st->range][1];
893 mutex_unlock(&st->lock);
894 return IIO_VAL_INT_PLUS_NANO;
897 *val2 = ADXL367_TEMP_PER_C;
898 return IIO_VAL_FRACTIONAL;
900 *val = ADXL367_VOLTAGE_MAX_MV;
901 *val2 = ADXL367_VOLTAGE_MAX_RAW;
902 return IIO_VAL_FRACTIONAL;
906 case IIO_CHAN_INFO_OFFSET:
907 switch (chan->type) {
909 *val = 25 * ADXL367_TEMP_PER_C - ADXL367_TEMP_25C;
912 *val = ADXL367_VOLTAGE_OFFSET;
917 case IIO_CHAN_INFO_SAMP_FREQ:
918 mutex_lock(&st->lock);
919 *val = adxl367_samp_freq_tbl[st->odr][0];
920 *val2 = adxl367_samp_freq_tbl[st->odr][1];
921 mutex_unlock(&st->lock);
922 return IIO_VAL_INT_PLUS_MICRO;
928 static int adxl367_write_raw(struct iio_dev *indio_dev,
929 struct iio_chan_spec const *chan,
930 int val, int val2, long info)
932 struct adxl367_state *st = iio_priv(indio_dev);
936 case IIO_CHAN_INFO_SAMP_FREQ: {
937 enum adxl367_odr odr;
939 ret = adxl367_find_odr(st, val, val2, &odr);
943 return adxl367_set_odr(indio_dev, odr);
945 case IIO_CHAN_INFO_SCALE: {
946 enum adxl367_range range;
948 ret = adxl367_find_range(st, val, val2, &range);
952 return adxl367_set_range(indio_dev, range);
959 static int adxl367_write_raw_get_fmt(struct iio_dev *indio_dev,
960 struct iio_chan_spec const *chan,
964 case IIO_CHAN_INFO_SCALE:
965 if (chan->type != IIO_ACCEL)
968 return IIO_VAL_INT_PLUS_NANO;
970 return IIO_VAL_INT_PLUS_MICRO;
974 static int adxl367_read_avail(struct iio_dev *indio_dev,
975 struct iio_chan_spec const *chan,
976 const int **vals, int *type, int *length,
980 case IIO_CHAN_INFO_SCALE:
981 if (chan->type != IIO_ACCEL)
984 *vals = (int *)adxl367_range_scale_tbl;
985 *type = IIO_VAL_INT_PLUS_NANO;
986 *length = ARRAY_SIZE(adxl367_range_scale_tbl) * 2;
987 return IIO_AVAIL_LIST;
988 case IIO_CHAN_INFO_SAMP_FREQ:
989 *vals = (int *)adxl367_samp_freq_tbl;
990 *type = IIO_VAL_INT_PLUS_MICRO;
991 *length = ARRAY_SIZE(adxl367_samp_freq_tbl) * 2;
992 return IIO_AVAIL_LIST;
998 static int adxl367_read_event_value(struct iio_dev *indio_dev,
999 const struct iio_chan_spec *chan,
1000 enum iio_event_type type,
1001 enum iio_event_direction dir,
1002 enum iio_event_info info,
1003 int *val, int *val2)
1005 struct adxl367_state *st = iio_priv(indio_dev);
1008 case IIO_EV_INFO_VALUE: {
1010 case IIO_EV_DIR_RISING:
1011 mutex_lock(&st->lock);
1012 *val = st->act_threshold;
1013 mutex_unlock(&st->lock);
1015 case IIO_EV_DIR_FALLING:
1016 mutex_lock(&st->lock);
1017 *val = st->inact_threshold;
1018 mutex_unlock(&st->lock);
1024 case IIO_EV_INFO_PERIOD:
1026 case IIO_EV_DIR_RISING:
1027 mutex_lock(&st->lock);
1028 *val = st->act_time_ms;
1029 mutex_unlock(&st->lock);
1031 return IIO_VAL_FRACTIONAL;
1032 case IIO_EV_DIR_FALLING:
1033 mutex_lock(&st->lock);
1034 *val = st->inact_time_ms;
1035 mutex_unlock(&st->lock);
1037 return IIO_VAL_FRACTIONAL;
1046 static int adxl367_write_event_value(struct iio_dev *indio_dev,
1047 const struct iio_chan_spec *chan,
1048 enum iio_event_type type,
1049 enum iio_event_direction dir,
1050 enum iio_event_info info,
1053 struct adxl367_state *st = iio_priv(indio_dev);
1056 case IIO_EV_INFO_VALUE:
1061 case IIO_EV_DIR_RISING:
1062 return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val);
1063 case IIO_EV_DIR_FALLING:
1064 return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val);
1068 case IIO_EV_INFO_PERIOD:
1072 val = val * 1000 + DIV_ROUND_UP(val2, 1000);
1074 case IIO_EV_DIR_RISING:
1075 return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val);
1076 case IIO_EV_DIR_FALLING:
1077 return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val);
1086 static int adxl367_read_event_config(struct iio_dev *indio_dev,
1087 const struct iio_chan_spec *chan,
1088 enum iio_event_type type,
1089 enum iio_event_direction dir)
1091 struct adxl367_state *st = iio_priv(indio_dev);
1096 case IIO_EV_DIR_RISING:
1097 ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en);
1099 case IIO_EV_DIR_FALLING:
1100 ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en);
1107 static int adxl367_write_event_config(struct iio_dev *indio_dev,
1108 const struct iio_chan_spec *chan,
1109 enum iio_event_type type,
1110 enum iio_event_direction dir,
1113 struct adxl367_state *st = iio_priv(indio_dev);
1114 enum adxl367_activity_type act;
1118 case IIO_EV_DIR_RISING:
1119 act = ADXL367_ACTIVITY;
1121 case IIO_EV_DIR_FALLING:
1122 act = ADXL367_INACTIVITY;
1128 ret = iio_device_claim_direct_mode(indio_dev);
1132 mutex_lock(&st->lock);
1134 ret = adxl367_set_measure_en(st, false);
1138 ret = adxl367_set_act_interrupt_en(st, act, state);
1142 ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED
1143 : ADXL367_ACT_DISABLED);
1147 ret = adxl367_set_measure_en(st, true);
1150 mutex_unlock(&st->lock);
1152 iio_device_release_direct_mode(indio_dev);
1157 static ssize_t adxl367_get_fifo_enabled(struct device *dev,
1158 struct device_attribute *attr,
1161 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1162 enum adxl367_fifo_mode fifo_mode;
1165 ret = adxl367_get_fifo_mode(st, &fifo_mode);
1169 return sysfs_emit(buf, "%d\n", fifo_mode != ADXL367_FIFO_MODE_DISABLED);
1172 static ssize_t adxl367_get_fifo_watermark(struct device *dev,
1173 struct device_attribute *attr,
1176 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1177 unsigned int fifo_watermark;
1179 mutex_lock(&st->lock);
1180 fifo_watermark = st->fifo_watermark;
1181 mutex_unlock(&st->lock);
1183 return sysfs_emit(buf, "%d\n", fifo_watermark);
1186 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1");
1187 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max,
1188 __stringify(ADXL367_FIFO_MAX_WATERMARK));
1189 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1190 adxl367_get_fifo_watermark, NULL, 0);
1191 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1192 adxl367_get_fifo_enabled, NULL, 0);
1194 static const struct iio_dev_attr *adxl367_fifo_attributes[] = {
1195 &iio_dev_attr_hwfifo_watermark_min,
1196 &iio_dev_attr_hwfifo_watermark_max,
1197 &iio_dev_attr_hwfifo_watermark,
1198 &iio_dev_attr_hwfifo_enabled,
1202 static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1204 struct adxl367_state *st = iio_priv(indio_dev);
1207 if (val > ADXL367_FIFO_MAX_WATERMARK)
1210 mutex_lock(&st->lock);
1212 ret = adxl367_set_measure_en(st, false);
1216 ret = adxl367_set_fifo_watermark(st, val);
1220 ret = adxl367_set_measure_en(st, true);
1223 mutex_unlock(&st->lock);
1228 static bool adxl367_find_mask_fifo_format(const unsigned long *scan_mask,
1229 enum adxl367_fifo_format *fifo_format)
1231 size_t size = ARRAY_SIZE(adxl367_fifo_formats);
1234 for (i = 0; i < size; i++)
1235 if (*scan_mask == adxl367_channel_masks[i])
1241 *fifo_format = adxl367_fifo_formats[i];
1246 static int adxl367_update_scan_mode(struct iio_dev *indio_dev,
1247 const unsigned long *active_scan_mask)
1249 struct adxl367_state *st = iio_priv(indio_dev);
1250 enum adxl367_fifo_format fifo_format;
1253 if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format))
1256 mutex_lock(&st->lock);
1258 ret = adxl367_set_measure_en(st, false);
1262 ret = adxl367_set_fifo_format(st, fifo_format);
1266 ret = adxl367_set_measure_en(st, true);
1270 st->fifo_set_size = bitmap_weight(active_scan_mask,
1271 indio_dev->masklength);
1274 mutex_unlock(&st->lock);
1279 static int adxl367_buffer_postenable(struct iio_dev *indio_dev)
1281 struct adxl367_state *st = iio_priv(indio_dev);
1284 mutex_lock(&st->lock);
1286 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1291 ret = adxl367_set_measure_en(st, false);
1295 ret = adxl367_set_fifo_watermark_interrupt_en(st, true);
1299 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM);
1303 ret = adxl367_set_measure_en(st, true);
1306 mutex_unlock(&st->lock);
1311 static int adxl367_buffer_predisable(struct iio_dev *indio_dev)
1313 struct adxl367_state *st = iio_priv(indio_dev);
1316 mutex_lock(&st->lock);
1318 ret = adxl367_set_measure_en(st, false);
1322 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED);
1326 ret = adxl367_set_fifo_watermark_interrupt_en(st, false);
1330 ret = adxl367_set_measure_en(st, true);
1334 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1338 mutex_unlock(&st->lock);
1343 static const struct iio_buffer_setup_ops adxl367_buffer_ops = {
1344 .postenable = adxl367_buffer_postenable,
1345 .predisable = adxl367_buffer_predisable,
1348 static const struct iio_info adxl367_info = {
1349 .read_raw = adxl367_read_raw,
1350 .write_raw = adxl367_write_raw,
1351 .write_raw_get_fmt = adxl367_write_raw_get_fmt,
1352 .read_avail = adxl367_read_avail,
1353 .read_event_config = adxl367_read_event_config,
1354 .write_event_config = adxl367_write_event_config,
1355 .read_event_value = adxl367_read_event_value,
1356 .write_event_value = adxl367_write_event_value,
1357 .debugfs_reg_access = adxl367_reg_access,
1358 .hwfifo_set_watermark = adxl367_set_watermark,
1359 .update_scan_mode = adxl367_update_scan_mode,
1362 static const struct iio_event_spec adxl367_events[] = {
1364 .type = IIO_EV_TYPE_MAG_REFERENCED,
1365 .dir = IIO_EV_DIR_RISING,
1366 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1367 BIT(IIO_EV_INFO_PERIOD) |
1368 BIT(IIO_EV_INFO_VALUE),
1371 .type = IIO_EV_TYPE_MAG_REFERENCED,
1372 .dir = IIO_EV_DIR_FALLING,
1373 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1374 BIT(IIO_EV_INFO_PERIOD) |
1375 BIT(IIO_EV_INFO_VALUE),
1379 #define ADXL367_ACCEL_CHANNEL(index, reg, axis) { \
1380 .type = IIO_ACCEL, \
1383 .channel2 = IIO_MOD_##axis, \
1384 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1385 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1386 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
1387 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1388 .info_mask_shared_by_all_available = \
1389 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1390 .event_spec = adxl367_events, \
1391 .num_event_specs = ARRAY_SIZE(adxl367_events), \
1392 .scan_index = (index), \
1396 .storagebits = 16, \
1397 .endianness = IIO_BE, \
1401 #define ADXL367_CHANNEL(index, reg, _type) { \
1404 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1405 BIT(IIO_CHAN_INFO_OFFSET) | \
1406 BIT(IIO_CHAN_INFO_SCALE), \
1407 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1408 .scan_index = (index), \
1412 .storagebits = 16, \
1413 .endianness = IIO_BE, \
1417 static const struct iio_chan_spec adxl367_channels[] = {
1418 ADXL367_ACCEL_CHANNEL(ADXL367_X_CHANNEL_INDEX, ADXL367_REG_X_DATA_H, X),
1419 ADXL367_ACCEL_CHANNEL(ADXL367_Y_CHANNEL_INDEX, ADXL367_REG_Y_DATA_H, Y),
1420 ADXL367_ACCEL_CHANNEL(ADXL367_Z_CHANNEL_INDEX, ADXL367_REG_Z_DATA_H, Z),
1421 ADXL367_CHANNEL(ADXL367_TEMP_CHANNEL_INDEX, ADXL367_REG_TEMP_DATA_H,
1423 ADXL367_CHANNEL(ADXL367_EX_ADC_CHANNEL_INDEX, ADXL367_REG_EX_ADC_DATA_H,
1427 static int adxl367_verify_devid(struct adxl367_state *st)
1432 ret = regmap_read_poll_timeout(st->regmap, ADXL367_REG_DEVID, val,
1433 val == ADXL367_DEVID_AD, 1000, 10000);
1435 return dev_err_probe(st->dev, -ENODEV,
1436 "Invalid dev id 0x%02X, expected 0x%02X\n",
1437 val, ADXL367_DEVID_AD);
1442 static int adxl367_setup(struct adxl367_state *st)
1446 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
1447 ADXL367_2G_RANGE_1G);
1451 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
1452 ADXL367_2G_RANGE_100MG);
1456 ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED);
1460 ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ);
1464 ret = _adxl367_set_act_time_ms(st, 10);
1468 ret = _adxl367_set_inact_time_ms(st, 10000);
1472 return adxl367_set_measure_en(st, true);
1475 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
1476 void *context, struct regmap *regmap, int irq)
1478 static const char * const regulator_names[] = { "vdd", "vddio" };
1479 struct iio_dev *indio_dev;
1480 struct adxl367_state *st;
1483 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1487 st = iio_priv(indio_dev);
1489 st->regmap = regmap;
1490 st->context = context;
1493 mutex_init(&st->lock);
1495 indio_dev->channels = adxl367_channels;
1496 indio_dev->num_channels = ARRAY_SIZE(adxl367_channels);
1497 indio_dev->available_scan_masks = adxl367_channel_masks;
1498 indio_dev->name = "adxl367";
1499 indio_dev->info = &adxl367_info;
1500 indio_dev->modes = INDIO_DIRECT_MODE;
1502 ret = devm_regulator_bulk_get_enable(st->dev,
1503 ARRAY_SIZE(regulator_names),
1506 return dev_err_probe(st->dev, ret,
1507 "Failed to get regulators\n");
1509 ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE);
1513 ret = adxl367_verify_devid(st);
1517 ret = adxl367_setup(st);
1521 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,
1522 &adxl367_buffer_ops,
1523 adxl367_fifo_attributes);
1527 ret = devm_request_threaded_irq(st->dev, irq, NULL,
1528 adxl367_irq_handler, IRQF_ONESHOT,
1529 indio_dev->name, indio_dev);
1531 return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1533 return devm_iio_device_register(dev, indio_dev);
1535 EXPORT_SYMBOL_NS_GPL(adxl367_probe, IIO_ADXL367);
1537 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1538 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer driver");
1539 MODULE_LICENSE("GPL");