1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2021 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/iio/buffer.h>
10 #include <linux/iio/events.h>
11 #include <linux/iio/iio.h>
12 #include <linux/iio/kfifo_buf.h>
13 #include <linux/iio/sysfs.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <asm/unaligned.h>
23 #define ADXL367_REG_DEVID 0x00
24 #define ADXL367_DEVID_AD 0xAD
26 #define ADXL367_REG_STATUS 0x0B
27 #define ADXL367_STATUS_INACT_MASK BIT(5)
28 #define ADXL367_STATUS_ACT_MASK BIT(4)
29 #define ADXL367_STATUS_FIFO_FULL_MASK BIT(2)
31 #define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0)
33 #define ADXL367_REG_X_DATA_H 0x0E
34 #define ADXL367_REG_Y_DATA_H 0x10
35 #define ADXL367_REG_Z_DATA_H 0x12
36 #define ADXL367_REG_TEMP_DATA_H 0x14
37 #define ADXL367_REG_EX_ADC_DATA_H 0x16
38 #define ADXL367_DATA_MASK GENMASK(15, 2)
40 #define ADXL367_TEMP_25C 165
41 #define ADXL367_TEMP_PER_C 54
43 #define ADXL367_VOLTAGE_OFFSET 8192
44 #define ADXL367_VOLTAGE_MAX_MV 1000
45 #define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0)
47 #define ADXL367_REG_RESET 0x1F
48 #define ADXL367_RESET_CODE 0x52
50 #define ADXL367_REG_THRESH_ACT_H 0x20
51 #define ADXL367_REG_THRESH_INACT_H 0x23
52 #define ADXL367_THRESH_MAX GENMASK(12, 0)
53 #define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6)
54 #define ADXL367_THRESH_H_MASK GENMASK(6, 0)
55 #define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0)
56 #define ADXL367_THRESH_L_MASK GENMASK(7, 2)
58 #define ADXL367_REG_TIME_ACT 0x22
59 #define ADXL367_REG_TIME_INACT_H 0x25
60 #define ADXL367_TIME_ACT_MAX GENMASK(7, 0)
61 #define ADXL367_TIME_INACT_MAX GENMASK(15, 0)
62 #define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8)
63 #define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0)
64 #define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0)
65 #define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0)
67 #define ADXL367_REG_ACT_INACT_CTL 0x27
68 #define ADXL367_ACT_EN_MASK GENMASK(1, 0)
69 #define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4)
71 #define ADXL367_REG_FIFO_CTL 0x28
72 #define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3)
73 #define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0)
75 #define ADXL367_REG_FIFO_SAMPLES 0x29
76 #define ADXL367_FIFO_SIZE 512
77 #define ADXL367_FIFO_MAX_WATERMARK 511
79 #define ADXL367_SAMPLES_VAL_H_MASK BIT(8)
80 #define ADXL367_SAMPLES_H_MASK BIT(2)
81 #define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0)
82 #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0)
84 #define ADXL367_REG_INT1_MAP 0x2A
85 #define ADXL367_INT_INACT_MASK BIT(5)
86 #define ADXL367_INT_ACT_MASK BIT(4)
87 #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2)
89 #define ADXL367_REG_FILTER_CTL 0x2C
90 #define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6)
91 #define ADXL367_2G_RANGE_1G 4095
92 #define ADXL367_2G_RANGE_100MG 409
93 #define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0)
95 #define ADXL367_REG_POWER_CTL 0x2D
96 #define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0)
98 #define ADXL367_REG_ADC_CTL 0x3C
99 #define ADXL367_REG_TEMP_CTL 0x3D
100 #define ADXL367_ADC_EN_MASK BIT(0)
108 enum adxl367_fifo_mode {
109 ADXL367_FIFO_MODE_DISABLED = 0b00,
110 ADXL367_FIFO_MODE_STREAM = 0b10,
113 enum adxl367_fifo_format {
114 ADXL367_FIFO_FORMAT_XYZ,
115 ADXL367_FIFO_FORMAT_X,
116 ADXL367_FIFO_FORMAT_Y,
117 ADXL367_FIFO_FORMAT_Z,
118 ADXL367_FIFO_FORMAT_XYZT,
119 ADXL367_FIFO_FORMAT_XT,
120 ADXL367_FIFO_FORMAT_YT,
121 ADXL367_FIFO_FORMAT_ZT,
122 ADXL367_FIFO_FORMAT_XYZA,
123 ADXL367_FIFO_FORMAT_XA,
124 ADXL367_FIFO_FORMAT_YA,
125 ADXL367_FIFO_FORMAT_ZA,
128 enum adxl367_op_mode {
129 ADXL367_OP_STANDBY = 0b00,
130 ADXL367_OP_MEASURE = 0b10,
133 enum adxl367_act_proc_mode {
134 ADXL367_LOOPED = 0b11,
137 enum adxl367_act_en_mode {
138 ADXL367_ACT_DISABLED = 0b00,
139 ADCL367_ACT_REF_ENABLED = 0b11,
142 enum adxl367_activity_type {
156 struct adxl367_state {
157 const struct adxl367_ops *ops;
161 struct regmap *regmap;
163 struct regulator_bulk_data regulators[2];
166 * Synchronize access to members of driver state, and ensure atomicity
167 * of consecutive regmap operations.
171 enum adxl367_odr odr;
172 enum adxl367_range range;
174 unsigned int act_threshold;
175 unsigned int act_time_ms;
176 unsigned int inact_threshold;
177 unsigned int inact_time_ms;
179 unsigned int fifo_set_size;
180 unsigned int fifo_watermark;
182 __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
184 u8 act_threshold_buf[2];
185 u8 inact_time_buf[2];
189 static const unsigned int adxl367_threshold_h_reg_tbl[] = {
190 [ADXL367_ACTIVITY] = ADXL367_REG_THRESH_ACT_H,
191 [ADXL367_INACTIVITY] = ADXL367_REG_THRESH_INACT_H,
194 static const unsigned int adxl367_act_en_shift_tbl[] = {
195 [ADXL367_ACTIVITY] = 0,
196 [ADXL367_INACTIVITY] = 2,
199 static const unsigned int adxl367_act_int_mask_tbl[] = {
200 [ADXL367_ACTIVITY] = ADXL367_INT_ACT_MASK,
201 [ADXL367_INACTIVITY] = ADXL367_INT_INACT_MASK,
204 static const int adxl367_samp_freq_tbl[][2] = {
205 [ADXL367_ODR_12P5HZ] = {12, 500000},
206 [ADXL367_ODR_25HZ] = {25, 0},
207 [ADXL367_ODR_50HZ] = {50, 0},
208 [ADXL367_ODR_100HZ] = {100, 0},
209 [ADXL367_ODR_200HZ] = {200, 0},
210 [ADXL367_ODR_400HZ] = {400, 0},
213 /* (g * 2) * 9.80665 * 1000000 / (2^14 - 1) */
214 static const int adxl367_range_scale_tbl[][2] = {
215 [ADXL367_2G_RANGE] = {0, 2394347},
216 [ADXL367_4G_RANGE] = {0, 4788695},
217 [ADXL367_8G_RANGE] = {0, 9577391},
220 static const int adxl367_range_scale_factor_tbl[] = {
221 [ADXL367_2G_RANGE] = 1,
222 [ADXL367_4G_RANGE] = 2,
223 [ADXL367_8G_RANGE] = 4,
227 ADXL367_X_CHANNEL_INDEX,
228 ADXL367_Y_CHANNEL_INDEX,
229 ADXL367_Z_CHANNEL_INDEX,
230 ADXL367_TEMP_CHANNEL_INDEX,
231 ADXL367_EX_ADC_CHANNEL_INDEX
234 #define ADXL367_X_CHANNEL_MASK BIT(ADXL367_X_CHANNEL_INDEX)
235 #define ADXL367_Y_CHANNEL_MASK BIT(ADXL367_Y_CHANNEL_INDEX)
236 #define ADXL367_Z_CHANNEL_MASK BIT(ADXL367_Z_CHANNEL_INDEX)
237 #define ADXL367_TEMP_CHANNEL_MASK BIT(ADXL367_TEMP_CHANNEL_INDEX)
238 #define ADXL367_EX_ADC_CHANNEL_MASK BIT(ADXL367_EX_ADC_CHANNEL_INDEX)
240 static const enum adxl367_fifo_format adxl367_fifo_formats[] = {
241 ADXL367_FIFO_FORMAT_X,
242 ADXL367_FIFO_FORMAT_Y,
243 ADXL367_FIFO_FORMAT_Z,
244 ADXL367_FIFO_FORMAT_XT,
245 ADXL367_FIFO_FORMAT_YT,
246 ADXL367_FIFO_FORMAT_ZT,
247 ADXL367_FIFO_FORMAT_XA,
248 ADXL367_FIFO_FORMAT_YA,
249 ADXL367_FIFO_FORMAT_ZA,
250 ADXL367_FIFO_FORMAT_XYZ,
251 ADXL367_FIFO_FORMAT_XYZT,
252 ADXL367_FIFO_FORMAT_XYZA,
255 static const unsigned long adxl367_channel_masks[] = {
256 ADXL367_X_CHANNEL_MASK,
257 ADXL367_Y_CHANNEL_MASK,
258 ADXL367_Z_CHANNEL_MASK,
259 ADXL367_X_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
260 ADXL367_Y_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
261 ADXL367_Z_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
262 ADXL367_X_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
263 ADXL367_Y_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
264 ADXL367_Z_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
265 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK,
266 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
267 ADXL367_TEMP_CHANNEL_MASK,
268 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
269 ADXL367_EX_ADC_CHANNEL_MASK,
273 static int adxl367_set_measure_en(struct adxl367_state *st, bool en)
275 enum adxl367_op_mode op_mode = en ? ADXL367_OP_MEASURE
276 : ADXL367_OP_STANDBY;
279 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL,
280 ADXL367_POWER_CTL_MODE_MASK,
281 FIELD_PREP(ADXL367_POWER_CTL_MODE_MASK,
287 * Wait for acceleration output to settle after entering
296 static void adxl367_scale_act_thresholds(struct adxl367_state *st,
297 enum adxl367_range old_range,
298 enum adxl367_range new_range)
300 st->act_threshold = st->act_threshold
301 * adxl367_range_scale_factor_tbl[old_range]
302 / adxl367_range_scale_factor_tbl[new_range];
303 st->inact_threshold = st->inact_threshold
304 * adxl367_range_scale_factor_tbl[old_range]
305 / adxl367_range_scale_factor_tbl[new_range];
308 static int _adxl367_set_act_threshold(struct adxl367_state *st,
309 enum adxl367_activity_type act,
310 unsigned int threshold)
312 u8 reg = adxl367_threshold_h_reg_tbl[act];
315 if (threshold > ADXL367_THRESH_MAX)
318 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK,
319 FIELD_GET(ADXL367_THRESH_VAL_H_MASK,
321 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK,
322 FIELD_GET(ADXL367_THRESH_VAL_L_MASK,
325 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf,
326 sizeof(st->act_threshold_buf));
330 if (act == ADXL367_ACTIVITY)
331 st->act_threshold = threshold;
333 st->inact_threshold = threshold;
338 static int adxl367_set_act_threshold(struct adxl367_state *st,
339 enum adxl367_activity_type act,
340 unsigned int threshold)
344 mutex_lock(&st->lock);
346 ret = adxl367_set_measure_en(st, false);
350 ret = _adxl367_set_act_threshold(st, act, threshold);
354 ret = adxl367_set_measure_en(st, true);
357 mutex_unlock(&st->lock);
362 static int adxl367_set_act_proc_mode(struct adxl367_state *st,
363 enum adxl367_act_proc_mode mode)
365 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
366 ADXL367_ACT_LINKLOOP_MASK,
367 FIELD_PREP(ADXL367_ACT_LINKLOOP_MASK,
371 static int adxl367_set_act_interrupt_en(struct adxl367_state *st,
372 enum adxl367_activity_type act,
375 unsigned int mask = adxl367_act_int_mask_tbl[act];
377 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
378 mask, en ? mask : 0);
381 static int adxl367_get_act_interrupt_en(struct adxl367_state *st,
382 enum adxl367_activity_type act,
385 unsigned int mask = adxl367_act_int_mask_tbl[act];
389 ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);
393 *en = !!(val & mask);
398 static int adxl367_set_act_en(struct adxl367_state *st,
399 enum adxl367_activity_type act,
400 enum adxl367_act_en_mode en)
402 unsigned int ctl_shift = adxl367_act_en_shift_tbl[act];
404 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
405 ADXL367_ACT_EN_MASK << ctl_shift,
409 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,
412 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
413 ADXL367_INT_FIFO_WATERMARK_MASK,
414 en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0);
417 static int adxl367_get_fifo_mode(struct adxl367_state *st,
418 enum adxl367_fifo_mode *fifo_mode)
423 ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val);
427 *fifo_mode = FIELD_GET(ADXL367_FIFO_CTL_MODE_MASK, val);
432 static int adxl367_set_fifo_mode(struct adxl367_state *st,
433 enum adxl367_fifo_mode fifo_mode)
435 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
436 ADXL367_FIFO_CTL_MODE_MASK,
437 FIELD_PREP(ADXL367_FIFO_CTL_MODE_MASK,
441 static int adxl367_set_fifo_format(struct adxl367_state *st,
442 enum adxl367_fifo_format fifo_format)
444 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
445 ADXL367_FIFO_CTL_FORMAT_MASK,
446 FIELD_PREP(ADXL367_FIFO_CTL_FORMAT_MASK,
450 static int adxl367_set_fifo_watermark(struct adxl367_state *st,
451 unsigned int fifo_watermark)
453 unsigned int fifo_samples = fifo_watermark * st->fifo_set_size;
454 unsigned int fifo_samples_h, fifo_samples_l;
457 if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK)
458 fifo_samples = ADXL367_FIFO_MAX_WATERMARK;
460 fifo_samples /= st->fifo_set_size;
462 fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK,
463 FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK,
465 fifo_samples_l = FIELD_PREP(ADXL367_SAMPLES_L_MASK,
466 FIELD_GET(ADXL367_SAMPLES_VAL_L_MASK,
469 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
470 ADXL367_SAMPLES_H_MASK, fifo_samples_h);
474 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES,
475 ADXL367_SAMPLES_L_MASK, fifo_samples_l);
479 st->fifo_watermark = fifo_watermark;
484 static int adxl367_set_range(struct iio_dev *indio_dev,
485 enum adxl367_range range)
487 struct adxl367_state *st = iio_priv(indio_dev);
490 ret = iio_device_claim_direct_mode(indio_dev);
494 mutex_lock(&st->lock);
496 ret = adxl367_set_measure_en(st, false);
500 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
501 ADXL367_FILTER_CTL_RANGE_MASK,
502 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MASK,
507 adxl367_scale_act_thresholds(st, st->range, range);
509 /* Activity thresholds depend on range */
510 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
515 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
516 st->inact_threshold);
520 ret = adxl367_set_measure_en(st, true);
527 mutex_unlock(&st->lock);
529 iio_device_release_direct_mode(indio_dev);
534 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms)
536 int freq_hz = adxl367_samp_freq_tbl[st->odr][0];
537 int freq_microhz = adxl367_samp_freq_tbl[st->odr][1];
538 /* Scale to decihertz to prevent precision loss in 12.5Hz case. */
539 int freq_dhz = freq_hz * 10 + freq_microhz / 100000;
541 return DIV_ROUND_CLOSEST(ms * freq_dhz, 10000);
544 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms)
546 unsigned int val = adxl367_time_ms_to_samples(st, ms);
549 if (val > ADXL367_TIME_ACT_MAX)
550 val = ADXL367_TIME_ACT_MAX;
552 ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val);
556 st->act_time_ms = ms;
561 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms)
563 unsigned int val = adxl367_time_ms_to_samples(st, ms);
566 if (val > ADXL367_TIME_INACT_MAX)
567 val = ADXL367_TIME_INACT_MAX;
569 st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK,
570 FIELD_GET(ADXL367_TIME_INACT_VAL_H_MASK,
572 st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK,
573 FIELD_GET(ADXL367_TIME_INACT_VAL_L_MASK,
576 ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H,
577 st->inact_time_buf, sizeof(st->inact_time_buf));
581 st->inact_time_ms = ms;
586 static int adxl367_set_act_time_ms(struct adxl367_state *st,
587 enum adxl367_activity_type act,
592 mutex_lock(&st->lock);
594 ret = adxl367_set_measure_en(st, false);
598 if (act == ADXL367_ACTIVITY)
599 ret = _adxl367_set_act_time_ms(st, ms);
601 ret = _adxl367_set_inact_time_ms(st, ms);
606 ret = adxl367_set_measure_en(st, true);
609 mutex_unlock(&st->lock);
614 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr)
618 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
619 ADXL367_FILTER_CTL_ODR_MASK,
620 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MASK,
625 /* Activity timers depend on ODR */
626 ret = _adxl367_set_act_time_ms(st, st->act_time_ms);
630 ret = _adxl367_set_inact_time_ms(st, st->inact_time_ms);
639 static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr)
641 struct adxl367_state *st = iio_priv(indio_dev);
644 ret = iio_device_claim_direct_mode(indio_dev);
648 mutex_lock(&st->lock);
650 ret = adxl367_set_measure_en(st, false);
654 ret = _adxl367_set_odr(st, odr);
658 ret = adxl367_set_measure_en(st, true);
661 mutex_unlock(&st->lock);
663 iio_device_release_direct_mode(indio_dev);
668 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg,
671 return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK,
672 en ? ADXL367_ADC_EN_MASK : 0);
675 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st,
676 unsigned int reg, bool en)
681 case ADXL367_REG_TEMP_DATA_H:
682 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
684 case ADXL367_REG_EX_ADC_DATA_H:
685 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
700 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st,
701 const unsigned long *active_scan_mask,
704 if (*active_scan_mask & ADXL367_TEMP_CHANNEL_MASK)
705 return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
706 else if (*active_scan_mask & ADXL367_EX_ADC_CHANNEL_MASK)
707 return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
712 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2,
713 enum adxl367_odr *odr)
715 size_t size = ARRAY_SIZE(adxl367_samp_freq_tbl);
718 for (i = 0; i < size; i++)
719 if (val == adxl367_samp_freq_tbl[i][0] &&
720 val2 == adxl367_samp_freq_tbl[i][1])
731 static int adxl367_find_range(struct adxl367_state *st, int val, int val2,
732 enum adxl367_range *range)
734 size_t size = ARRAY_SIZE(adxl367_range_scale_tbl);
737 for (i = 0; i < size; i++)
738 if (val == adxl367_range_scale_tbl[i][0] &&
739 val2 == adxl367_range_scale_tbl[i][1])
750 static int adxl367_read_sample(struct iio_dev *indio_dev,
751 struct iio_chan_spec const *chan,
754 struct adxl367_state *st = iio_priv(indio_dev);
758 ret = iio_device_claim_direct_mode(indio_dev);
762 mutex_lock(&st->lock);
764 ret = adxl367_set_temp_adc_reg_en(st, chan->address, true);
768 ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf,
769 sizeof(st->sample_buf));
773 sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf));
774 *val = sign_extend32(sample, chan->scan_type.realbits - 1);
776 ret = adxl367_set_temp_adc_reg_en(st, chan->address, false);
779 mutex_unlock(&st->lock);
781 iio_device_release_direct_mode(indio_dev);
783 return ret ?: IIO_VAL_INT;
786 static int adxl367_get_status(struct adxl367_state *st, u8 *status,
791 /* Read STATUS, FIFO_ENT_L and FIFO_ENT_H */
792 ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS,
793 st->status_buf, sizeof(st->status_buf));
797 st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK;
799 *status = st->status_buf[0];
800 *fifo_entries = get_unaligned_le16(&st->status_buf[1]);
805 static bool adxl367_push_event(struct iio_dev *indio_dev, u8 status)
809 if (FIELD_GET(ADXL367_STATUS_ACT_MASK, status))
810 ev_dir = IIO_EV_DIR_RISING;
811 else if (FIELD_GET(ADXL367_STATUS_INACT_MASK, status))
812 ev_dir = IIO_EV_DIR_FALLING;
816 iio_push_event(indio_dev,
817 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
818 IIO_EV_TYPE_THRESH, ev_dir),
819 iio_get_time_ns(indio_dev));
824 static bool adxl367_push_fifo_data(struct iio_dev *indio_dev, u8 status,
827 struct adxl367_state *st = iio_priv(indio_dev);
831 if (!FIELD_GET(ADXL367_STATUS_FIFO_FULL_MASK, status))
834 fifo_entries -= fifo_entries % st->fifo_set_size;
836 ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries);
838 dev_err(st->dev, "Failed to read FIFO: %d\n", ret);
842 for (i = 0; i < fifo_entries; i += st->fifo_set_size)
843 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
848 static irqreturn_t adxl367_irq_handler(int irq, void *private)
850 struct iio_dev *indio_dev = private;
851 struct adxl367_state *st = iio_priv(indio_dev);
857 ret = adxl367_get_status(st, &status, &fifo_entries);
861 handled = adxl367_push_event(indio_dev, status);
862 handled |= adxl367_push_fifo_data(indio_dev, status, fifo_entries);
864 return handled ? IRQ_HANDLED : IRQ_NONE;
867 static int adxl367_reg_access(struct iio_dev *indio_dev,
869 unsigned int writeval,
870 unsigned int *readval)
872 struct adxl367_state *st = iio_priv(indio_dev);
875 return regmap_read(st->regmap, reg, readval);
877 return regmap_write(st->regmap, reg, writeval);
880 static int adxl367_read_raw(struct iio_dev *indio_dev,
881 struct iio_chan_spec const *chan,
882 int *val, int *val2, long info)
884 struct adxl367_state *st = iio_priv(indio_dev);
887 case IIO_CHAN_INFO_RAW:
888 return adxl367_read_sample(indio_dev, chan, val);
889 case IIO_CHAN_INFO_SCALE:
890 switch (chan->type) {
892 mutex_lock(&st->lock);
893 *val = adxl367_range_scale_tbl[st->range][0];
894 *val2 = adxl367_range_scale_tbl[st->range][1];
895 mutex_unlock(&st->lock);
896 return IIO_VAL_INT_PLUS_NANO;
899 *val2 = ADXL367_TEMP_PER_C;
900 return IIO_VAL_FRACTIONAL;
902 *val = ADXL367_VOLTAGE_MAX_MV;
903 *val2 = ADXL367_VOLTAGE_MAX_RAW;
904 return IIO_VAL_FRACTIONAL;
908 case IIO_CHAN_INFO_OFFSET:
909 switch (chan->type) {
911 *val = 25 * ADXL367_TEMP_PER_C - ADXL367_TEMP_25C;
914 *val = ADXL367_VOLTAGE_OFFSET;
919 case IIO_CHAN_INFO_SAMP_FREQ:
920 mutex_lock(&st->lock);
921 *val = adxl367_samp_freq_tbl[st->odr][0];
922 *val2 = adxl367_samp_freq_tbl[st->odr][1];
923 mutex_unlock(&st->lock);
924 return IIO_VAL_INT_PLUS_MICRO;
930 static int adxl367_write_raw(struct iio_dev *indio_dev,
931 struct iio_chan_spec const *chan,
932 int val, int val2, long info)
934 struct adxl367_state *st = iio_priv(indio_dev);
938 case IIO_CHAN_INFO_SAMP_FREQ: {
939 enum adxl367_odr odr;
941 ret = adxl367_find_odr(st, val, val2, &odr);
945 return adxl367_set_odr(indio_dev, odr);
947 case IIO_CHAN_INFO_SCALE: {
948 enum adxl367_range range;
950 ret = adxl367_find_range(st, val, val2, &range);
954 return adxl367_set_range(indio_dev, range);
961 static int adxl367_write_raw_get_fmt(struct iio_dev *indio_dev,
962 struct iio_chan_spec const *chan,
966 case IIO_CHAN_INFO_SCALE:
967 if (chan->type != IIO_ACCEL)
970 return IIO_VAL_INT_PLUS_NANO;
972 return IIO_VAL_INT_PLUS_MICRO;
976 static int adxl367_read_avail(struct iio_dev *indio_dev,
977 struct iio_chan_spec const *chan,
978 const int **vals, int *type, int *length,
982 case IIO_CHAN_INFO_SCALE:
983 if (chan->type != IIO_ACCEL)
986 *vals = (int *)adxl367_range_scale_tbl;
987 *type = IIO_VAL_INT_PLUS_NANO;
988 *length = ARRAY_SIZE(adxl367_range_scale_tbl) * 2;
989 return IIO_AVAIL_LIST;
990 case IIO_CHAN_INFO_SAMP_FREQ:
991 *vals = (int *)adxl367_samp_freq_tbl;
992 *type = IIO_VAL_INT_PLUS_MICRO;
993 *length = ARRAY_SIZE(adxl367_samp_freq_tbl) * 2;
994 return IIO_AVAIL_LIST;
1000 static int adxl367_read_event_value(struct iio_dev *indio_dev,
1001 const struct iio_chan_spec *chan,
1002 enum iio_event_type type,
1003 enum iio_event_direction dir,
1004 enum iio_event_info info,
1005 int *val, int *val2)
1007 struct adxl367_state *st = iio_priv(indio_dev);
1010 case IIO_EV_INFO_VALUE: {
1012 case IIO_EV_DIR_RISING:
1013 mutex_lock(&st->lock);
1014 *val = st->act_threshold;
1015 mutex_unlock(&st->lock);
1017 case IIO_EV_DIR_FALLING:
1018 mutex_lock(&st->lock);
1019 *val = st->inact_threshold;
1020 mutex_unlock(&st->lock);
1026 case IIO_EV_INFO_PERIOD:
1028 case IIO_EV_DIR_RISING:
1029 mutex_lock(&st->lock);
1030 *val = st->act_time_ms;
1031 mutex_unlock(&st->lock);
1033 return IIO_VAL_FRACTIONAL;
1034 case IIO_EV_DIR_FALLING:
1035 mutex_lock(&st->lock);
1036 *val = st->inact_time_ms;
1037 mutex_unlock(&st->lock);
1039 return IIO_VAL_FRACTIONAL;
1048 static int adxl367_write_event_value(struct iio_dev *indio_dev,
1049 const struct iio_chan_spec *chan,
1050 enum iio_event_type type,
1051 enum iio_event_direction dir,
1052 enum iio_event_info info,
1055 struct adxl367_state *st = iio_priv(indio_dev);
1058 case IIO_EV_INFO_VALUE:
1063 case IIO_EV_DIR_RISING:
1064 return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val);
1065 case IIO_EV_DIR_FALLING:
1066 return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val);
1070 case IIO_EV_INFO_PERIOD:
1074 val = val * 1000 + DIV_ROUND_UP(val2, 1000);
1076 case IIO_EV_DIR_RISING:
1077 return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val);
1078 case IIO_EV_DIR_FALLING:
1079 return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val);
1088 static int adxl367_read_event_config(struct iio_dev *indio_dev,
1089 const struct iio_chan_spec *chan,
1090 enum iio_event_type type,
1091 enum iio_event_direction dir)
1093 struct adxl367_state *st = iio_priv(indio_dev);
1098 case IIO_EV_DIR_RISING:
1099 ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en);
1101 case IIO_EV_DIR_FALLING:
1102 ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en);
1109 static int adxl367_write_event_config(struct iio_dev *indio_dev,
1110 const struct iio_chan_spec *chan,
1111 enum iio_event_type type,
1112 enum iio_event_direction dir,
1115 struct adxl367_state *st = iio_priv(indio_dev);
1116 enum adxl367_activity_type act;
1120 case IIO_EV_DIR_RISING:
1121 act = ADXL367_ACTIVITY;
1123 case IIO_EV_DIR_FALLING:
1124 act = ADXL367_INACTIVITY;
1130 ret = iio_device_claim_direct_mode(indio_dev);
1134 mutex_lock(&st->lock);
1136 ret = adxl367_set_measure_en(st, false);
1140 ret = adxl367_set_act_interrupt_en(st, act, state);
1144 ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED
1145 : ADXL367_ACT_DISABLED);
1149 ret = adxl367_set_measure_en(st, true);
1152 mutex_unlock(&st->lock);
1154 iio_device_release_direct_mode(indio_dev);
1159 static ssize_t adxl367_get_fifo_enabled(struct device *dev,
1160 struct device_attribute *attr,
1163 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1164 enum adxl367_fifo_mode fifo_mode;
1167 ret = adxl367_get_fifo_mode(st, &fifo_mode);
1171 return sysfs_emit(buf, "%d\n", fifo_mode != ADXL367_FIFO_MODE_DISABLED);
1174 static ssize_t adxl367_get_fifo_watermark(struct device *dev,
1175 struct device_attribute *attr,
1178 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1179 unsigned int fifo_watermark;
1181 mutex_lock(&st->lock);
1182 fifo_watermark = st->fifo_watermark;
1183 mutex_unlock(&st->lock);
1185 return sysfs_emit(buf, "%d\n", fifo_watermark);
1188 static ssize_t hwfifo_watermark_min_show(struct device *dev,
1189 struct device_attribute *attr,
1192 return sysfs_emit(buf, "%s\n", "1");
1195 static ssize_t hwfifo_watermark_max_show(struct device *dev,
1196 struct device_attribute *attr,
1199 return sysfs_emit(buf, "%s\n", __stringify(ADXL367_FIFO_MAX_WATERMARK));
1202 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
1203 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
1204 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1205 adxl367_get_fifo_watermark, NULL, 0);
1206 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1207 adxl367_get_fifo_enabled, NULL, 0);
1209 static const struct attribute *adxl367_fifo_attributes[] = {
1210 &iio_dev_attr_hwfifo_watermark_min.dev_attr.attr,
1211 &iio_dev_attr_hwfifo_watermark_max.dev_attr.attr,
1212 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
1213 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
1217 static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1219 struct adxl367_state *st = iio_priv(indio_dev);
1222 if (val > ADXL367_FIFO_MAX_WATERMARK)
1225 mutex_lock(&st->lock);
1227 ret = adxl367_set_measure_en(st, false);
1231 ret = adxl367_set_fifo_watermark(st, val);
1235 ret = adxl367_set_measure_en(st, true);
1238 mutex_unlock(&st->lock);
1243 static bool adxl367_find_mask_fifo_format(const unsigned long *scan_mask,
1244 enum adxl367_fifo_format *fifo_format)
1246 size_t size = ARRAY_SIZE(adxl367_fifo_formats);
1249 for (i = 0; i < size; i++)
1250 if (*scan_mask == adxl367_channel_masks[i])
1256 *fifo_format = adxl367_fifo_formats[i];
1261 static int adxl367_update_scan_mode(struct iio_dev *indio_dev,
1262 const unsigned long *active_scan_mask)
1264 struct adxl367_state *st = iio_priv(indio_dev);
1265 enum adxl367_fifo_format fifo_format;
1268 if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format))
1271 mutex_lock(&st->lock);
1273 ret = adxl367_set_measure_en(st, false);
1277 ret = adxl367_set_fifo_format(st, fifo_format);
1281 ret = adxl367_set_measure_en(st, true);
1285 st->fifo_set_size = bitmap_weight(active_scan_mask,
1286 indio_dev->masklength);
1289 mutex_unlock(&st->lock);
1294 static int adxl367_buffer_postenable(struct iio_dev *indio_dev)
1296 struct adxl367_state *st = iio_priv(indio_dev);
1299 mutex_lock(&st->lock);
1301 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1306 ret = adxl367_set_measure_en(st, false);
1310 ret = adxl367_set_fifo_watermark_interrupt_en(st, true);
1314 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM);
1318 ret = adxl367_set_measure_en(st, true);
1321 mutex_unlock(&st->lock);
1326 static int adxl367_buffer_predisable(struct iio_dev *indio_dev)
1328 struct adxl367_state *st = iio_priv(indio_dev);
1331 mutex_lock(&st->lock);
1333 ret = adxl367_set_measure_en(st, false);
1337 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED);
1341 ret = adxl367_set_fifo_watermark_interrupt_en(st, false);
1345 ret = adxl367_set_measure_en(st, true);
1349 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1353 mutex_unlock(&st->lock);
1358 static const struct iio_buffer_setup_ops adxl367_buffer_ops = {
1359 .postenable = adxl367_buffer_postenable,
1360 .predisable = adxl367_buffer_predisable,
1363 static const struct iio_info adxl367_info = {
1364 .read_raw = adxl367_read_raw,
1365 .write_raw = adxl367_write_raw,
1366 .write_raw_get_fmt = adxl367_write_raw_get_fmt,
1367 .read_avail = adxl367_read_avail,
1368 .read_event_config = adxl367_read_event_config,
1369 .write_event_config = adxl367_write_event_config,
1370 .read_event_value = adxl367_read_event_value,
1371 .write_event_value = adxl367_write_event_value,
1372 .debugfs_reg_access = adxl367_reg_access,
1373 .hwfifo_set_watermark = adxl367_set_watermark,
1374 .update_scan_mode = adxl367_update_scan_mode,
1377 static const struct iio_event_spec adxl367_events[] = {
1379 .type = IIO_EV_TYPE_MAG_REFERENCED,
1380 .dir = IIO_EV_DIR_RISING,
1381 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1382 BIT(IIO_EV_INFO_PERIOD) |
1383 BIT(IIO_EV_INFO_VALUE),
1386 .type = IIO_EV_TYPE_MAG_REFERENCED,
1387 .dir = IIO_EV_DIR_FALLING,
1388 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1389 BIT(IIO_EV_INFO_PERIOD) |
1390 BIT(IIO_EV_INFO_VALUE),
1394 #define ADXL367_ACCEL_CHANNEL(index, reg, axis) { \
1395 .type = IIO_ACCEL, \
1398 .channel2 = IIO_MOD_##axis, \
1399 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1400 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1401 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
1402 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1403 .info_mask_shared_by_all_available = \
1404 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1405 .event_spec = adxl367_events, \
1406 .num_event_specs = ARRAY_SIZE(adxl367_events), \
1407 .scan_index = (index), \
1411 .storagebits = 16, \
1412 .endianness = IIO_BE, \
1416 #define ADXL367_CHANNEL(index, reg, _type) { \
1419 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1420 BIT(IIO_CHAN_INFO_OFFSET) | \
1421 BIT(IIO_CHAN_INFO_SCALE), \
1422 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1423 .scan_index = (index), \
1427 .storagebits = 16, \
1428 .endianness = IIO_BE, \
1432 static const struct iio_chan_spec adxl367_channels[] = {
1433 ADXL367_ACCEL_CHANNEL(ADXL367_X_CHANNEL_INDEX, ADXL367_REG_X_DATA_H, X),
1434 ADXL367_ACCEL_CHANNEL(ADXL367_Y_CHANNEL_INDEX, ADXL367_REG_Y_DATA_H, Y),
1435 ADXL367_ACCEL_CHANNEL(ADXL367_Z_CHANNEL_INDEX, ADXL367_REG_Z_DATA_H, Z),
1436 ADXL367_CHANNEL(ADXL367_TEMP_CHANNEL_INDEX, ADXL367_REG_TEMP_DATA_H,
1438 ADXL367_CHANNEL(ADXL367_EX_ADC_CHANNEL_INDEX, ADXL367_REG_EX_ADC_DATA_H,
1442 static int adxl367_verify_devid(struct adxl367_state *st)
1447 ret = regmap_read_poll_timeout(st->regmap, ADXL367_REG_DEVID, val,
1448 val == ADXL367_DEVID_AD, 1000, 10000);
1450 return dev_err_probe(st->dev, -ENODEV,
1451 "Invalid dev id 0x%02X, expected 0x%02X\n",
1452 val, ADXL367_DEVID_AD);
1457 static int adxl367_setup(struct adxl367_state *st)
1461 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
1462 ADXL367_2G_RANGE_1G);
1466 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
1467 ADXL367_2G_RANGE_100MG);
1471 ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED);
1475 ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ);
1479 ret = _adxl367_set_act_time_ms(st, 10);
1483 ret = _adxl367_set_inact_time_ms(st, 10000);
1487 return adxl367_set_measure_en(st, true);
1490 static void adxl367_disable_regulators(void *data)
1492 struct adxl367_state *st = data;
1494 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
1497 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
1498 void *context, struct regmap *regmap, int irq)
1500 struct iio_dev *indio_dev;
1501 struct adxl367_state *st;
1504 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1508 st = iio_priv(indio_dev);
1510 st->regmap = regmap;
1511 st->context = context;
1514 mutex_init(&st->lock);
1516 indio_dev->channels = adxl367_channels;
1517 indio_dev->num_channels = ARRAY_SIZE(adxl367_channels);
1518 indio_dev->available_scan_masks = adxl367_channel_masks;
1519 indio_dev->name = "adxl367";
1520 indio_dev->info = &adxl367_info;
1521 indio_dev->modes = INDIO_DIRECT_MODE;
1523 st->regulators[0].supply = "vdd";
1524 st->regulators[1].supply = "vddio";
1526 ret = devm_regulator_bulk_get(st->dev, ARRAY_SIZE(st->regulators),
1529 return dev_err_probe(st->dev, ret,
1530 "Failed to get regulators\n");
1532 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
1534 return dev_err_probe(st->dev, ret,
1535 "Failed to enable regulators\n");
1537 ret = devm_add_action_or_reset(st->dev, adxl367_disable_regulators, st);
1539 return dev_err_probe(st->dev, ret,
1540 "Failed to add regulators disable action\n");
1542 ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE);
1546 ret = adxl367_verify_devid(st);
1550 ret = adxl367_setup(st);
1554 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,
1555 &adxl367_buffer_ops,
1556 adxl367_fifo_attributes);
1560 ret = devm_request_threaded_irq(st->dev, irq, NULL,
1561 adxl367_irq_handler, IRQF_ONESHOT,
1562 indio_dev->name, indio_dev);
1564 return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1566 return devm_iio_device_register(dev, indio_dev);
1568 EXPORT_SYMBOL_NS_GPL(adxl367_probe, IIO_ADXL367);
1570 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1571 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer driver");
1572 MODULE_LICENSE("GPL");