drivers/idle/intel_idle.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * intel_idle.c - native hardware idle loop for modern Intel processors
   4  *
   5  * Copyright (c) 2013 - 2020, Intel Corporation.
   6  * Len Brown <len.brown@intel.com>
   7  * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   8  */
   9
  10 /*
  11  * intel_idle is a cpuidle driver that loads on all Intel CPUs with MWAIT
  12  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  13  * make Linux more efficient on these processors, as intel_idle knows
  14  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  15  */
  16
  17 /*
  18  * Design Assumptions
  19  *
  20  * All CPUs have same idle states as boot CPU
  21  *
  22  * Chipset BM_STS (bus master status) bit is a NOP
  23  *      for preventing entry into deep C-states
  24  *
  25  * CPU will flush caches as needed when entering a C-state via MWAIT
  26  *      (in contrast to entering ACPI C3, in which case the WBINVD
  27  *      instruction needs to be executed to flush the caches)
  28  */
  29
  30 /*
  31  * Known limitations
  32  *
  33  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  34  * to avoid complications with the lapic timer workaround.
  35  * Have not seen issues with suspend, but may need same workaround here.
  36  *
  37  */
  38
  39 /* un-comment DEBUG to enable pr_debug() statements */
  40 /* #define DEBUG */
  41
  42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  43
  44 #include <linux/acpi.h>
  45 #include <linux/kernel.h>
  46 #include <linux/cpuidle.h>
  47 #include <linux/tick.h>
  48 #include <trace/events/power.h>
  49 #include <linux/sched.h>
  50 #include <linux/sched/smt.h>
  51 #include <linux/notifier.h>
  52 #include <linux/cpu.h>
  53 #include <linux/moduleparam.h>
  54 #include <asm/cpu_device_id.h>
  55 #include <asm/intel-family.h>
  56 #include <asm/nospec-branch.h>
  57 #include <asm/mwait.h>
  58 #include <asm/msr.h>
  59
  60 #define INTEL_IDLE_VERSION "0.5.1"
  61
  62 static struct cpuidle_driver intel_idle_driver = {
  63         .name = "intel_idle",
  64         .owner = THIS_MODULE,
  65 };
  66 /* intel_idle.max_cstate=0 disables driver */
  67 static int max_cstate = CPUIDLE_STATE_MAX - 1;
  68 static unsigned int disabled_states_mask;
  69
  70 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  71
  72 static unsigned long auto_demotion_disable_flags;
  73 static bool disable_promotion_to_c1e;
  74
  75 struct idle_cpu {
  76         struct cpuidle_state *state_table;
  77
  78         /*
  79          * Hardware C-state auto-demotion may not always be optimal.
  80          * Indicate which enable bits to clear here.
  81          */
  82         unsigned long auto_demotion_disable_flags;
  83         bool byt_auto_demotion_disable_flag;
  84         bool disable_promotion_to_c1e;
  85         bool use_acpi;
  86 };
  87
  88 static const struct idle_cpu *icpu __initdata;
  89 static struct cpuidle_state *cpuidle_state_table __initdata;
  90
  91 static unsigned int mwait_substates __initdata;
  92
  93 /*
  94  * Enable this state by default even if the ACPI _CST does not list it.
  95  */
  96 #define CPUIDLE_FLAG_ALWAYS_ENABLE      BIT(15)
  97
  98 /*
  99  * Disable IBRS across idle (when KERNEL_IBRS), is exclusive vs IRQ_ENABLE
 100  * above.
 101  */
 102 #define CPUIDLE_FLAG_IBRS               BIT(16)
 103
 104 /*
 105  * MWAIT takes an 8-bit "hint" in EAX "suggesting"
 106  * the C-state (top nibble) and sub-state (bottom nibble)
 107  * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
 108  *
 109  * We store the hint at the top of our "flags" for each state.
 110  */
 111 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
 112 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
 113
 114 /**
 115  * intel_idle - Ask the processor to enter the given idle state.
 116  * @dev: cpuidle device of the target CPU.
 117  * @drv: cpuidle driver (assumed to point to intel_idle_driver).
 118  * @index: Target idle state index.
 119  *
 120  * Use the MWAIT instruction to notify the processor that the CPU represented by
 121  * @dev is idle and it can try to enter the idle state corresponding to @index.
 122  *
 123  * If the local APIC timer is not known to be reliable in the target idle state,
 124  * enable one-shot tick broadcasting for the target CPU before executing MWAIT.
 125  *
 126  * Optionally call leave_mm() for the target CPU upfront to avoid wakeups due to
 127  * flushing user TLBs.
 128  *
 129  * Must be called under local_irq_disable().
 130  */
 131 static __cpuidle int intel_idle(struct cpuidle_device *dev,
 132                                 struct cpuidle_driver *drv, int index)
 133 {
 134         struct cpuidle_state *state = &drv->states[index];
 135         unsigned long eax = flg2MWAIT(state->flags);
 136         unsigned long ecx = 1; /* break on interrupt flag */
 137
 138         mwait_idle_with_hints(eax, ecx);
 139
 140         return index;
 141 }
 142
 143 static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev,
 144                                      struct cpuidle_driver *drv, int index)
 145 {
 146         bool smt_active = sched_smt_active();
 147         u64 spec_ctrl = spec_ctrl_current();
 148         int ret;
 149
 150         if (smt_active)
 151                 wrmsrl(MSR_IA32_SPEC_CTRL, 0);
 152
 153         ret = intel_idle(dev, drv, index);
 154
 155         if (smt_active)
 156                 wrmsrl(MSR_IA32_SPEC_CTRL, spec_ctrl);
 157
 158         return ret;
 159 }
 160
 161 /**
 162  * intel_idle_s2idle - Ask the processor to enter the given idle state.
 163  * @dev: cpuidle device of the target CPU.
 164  * @drv: cpuidle driver (assumed to point to intel_idle_driver).
 165  * @index: Target idle state index.
 166  *
 167  * Use the MWAIT instruction to notify the processor that the CPU represented by
 168  * @dev is idle and it can try to enter the idle state corresponding to @index.
 169  *
 170  * Invoked as a suspend-to-idle callback routine with frozen user space, frozen
 171  * scheduler tick and suspended scheduler clock on the target CPU.
 172  */
 173 static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev,
 174                                        struct cpuidle_driver *drv, int index)
 175 {
 176         unsigned long eax = flg2MWAIT(drv->states[index].flags);
 177         unsigned long ecx = 1; /* break on interrupt flag */
 178
 179         mwait_idle_with_hints(eax, ecx);
 180
 181         return 0;
 182 }
 183
 184 /*
 185  * States are indexed by the cstate number,
 186  * which is also the index into the MWAIT hint array.
 187  * Thus C0 is a dummy.
 188  */
 189 static struct cpuidle_state nehalem_cstates[] __initdata = {
 190         {
 191                 .name = "C1",
 192                 .desc = "MWAIT 0x00",
 193                 .flags = MWAIT2flg(0x00),
 194                 .exit_latency = 3,
 195                 .target_residency = 6,
 196                 .enter = &intel_idle,
 197                 .enter_s2idle = intel_idle_s2idle, },
 198         {
 199                 .name = "C1E",
 200                 .desc = "MWAIT 0x01",
 201                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 202                 .exit_latency = 10,
 203                 .target_residency = 20,
 204                 .enter = &intel_idle,
 205                 .enter_s2idle = intel_idle_s2idle, },
 206         {
 207                 .name = "C3",
 208                 .desc = "MWAIT 0x10",
 209                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 210                 .exit_latency = 20,
 211                 .target_residency = 80,
 212                 .enter = &intel_idle,
 213                 .enter_s2idle = intel_idle_s2idle, },
 214         {
 215                 .name = "C6",
 216                 .desc = "MWAIT 0x20",
 217                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 218                 .exit_latency = 200,
 219                 .target_residency = 800,
 220                 .enter = &intel_idle,
 221                 .enter_s2idle = intel_idle_s2idle, },
 222         {
 223                 .enter = NULL }
 224 };
 225
 226 static struct cpuidle_state snb_cstates[] __initdata = {
 227         {
 228                 .name = "C1",
 229                 .desc = "MWAIT 0x00",
 230                 .flags = MWAIT2flg(0x00),
 231                 .exit_latency = 2,
 232                 .target_residency = 2,
 233                 .enter = &intel_idle,
 234                 .enter_s2idle = intel_idle_s2idle, },
 235         {
 236                 .name = "C1E",
 237                 .desc = "MWAIT 0x01",
 238                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 239                 .exit_latency = 10,
 240                 .target_residency = 20,
 241                 .enter = &intel_idle,
 242                 .enter_s2idle = intel_idle_s2idle, },
 243         {
 244                 .name = "C3",
 245                 .desc = "MWAIT 0x10",
 246                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 247                 .exit_latency = 80,
 248                 .target_residency = 211,
 249                 .enter = &intel_idle,
 250                 .enter_s2idle = intel_idle_s2idle, },
 251         {
 252                 .name = "C6",
 253                 .desc = "MWAIT 0x20",
 254                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 255                 .exit_latency = 104,
 256                 .target_residency = 345,
 257                 .enter = &intel_idle,
 258                 .enter_s2idle = intel_idle_s2idle, },
 259         {
 260                 .name = "C7",
 261                 .desc = "MWAIT 0x30",
 262                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 263                 .exit_latency = 109,
 264                 .target_residency = 345,
 265                 .enter = &intel_idle,
 266                 .enter_s2idle = intel_idle_s2idle, },
 267         {
 268                 .enter = NULL }
 269 };
 270
 271 static struct cpuidle_state byt_cstates[] __initdata = {
 272         {
 273                 .name = "C1",
 274                 .desc = "MWAIT 0x00",
 275                 .flags = MWAIT2flg(0x00),
 276                 .exit_latency = 1,
 277                 .target_residency = 1,
 278                 .enter = &intel_idle,
 279                 .enter_s2idle = intel_idle_s2idle, },
 280         {
 281                 .name = "C6N",
 282                 .desc = "MWAIT 0x58",
 283                 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
 284                 .exit_latency = 300,
 285                 .target_residency = 275,
 286                 .enter = &intel_idle,
 287                 .enter_s2idle = intel_idle_s2idle, },
 288         {
 289                 .name = "C6S",
 290                 .desc = "MWAIT 0x52",
 291                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 292                 .exit_latency = 500,
 293                 .target_residency = 560,
 294                 .enter = &intel_idle,
 295                 .enter_s2idle = intel_idle_s2idle, },
 296         {
 297                 .name = "C7",
 298                 .desc = "MWAIT 0x60",
 299                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 300                 .exit_latency = 1200,
 301                 .target_residency = 4000,
 302                 .enter = &intel_idle,
 303                 .enter_s2idle = intel_idle_s2idle, },
 304         {
 305                 .name = "C7S",
 306                 .desc = "MWAIT 0x64",
 307                 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
 308                 .exit_latency = 10000,
 309                 .target_residency = 20000,
 310                 .enter = &intel_idle,
 311                 .enter_s2idle = intel_idle_s2idle, },
 312         {
 313                 .enter = NULL }
 314 };
 315
 316 static struct cpuidle_state cht_cstates[] __initdata = {
 317         {
 318                 .name = "C1",
 319                 .desc = "MWAIT 0x00",
 320                 .flags = MWAIT2flg(0x00),
 321                 .exit_latency = 1,
 322                 .target_residency = 1,
 323                 .enter = &intel_idle,
 324                 .enter_s2idle = intel_idle_s2idle, },
 325         {
 326                 .name = "C6N",
 327                 .desc = "MWAIT 0x58",
 328                 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
 329                 .exit_latency = 80,
 330                 .target_residency = 275,
 331                 .enter = &intel_idle,
 332                 .enter_s2idle = intel_idle_s2idle, },
 333         {
 334                 .name = "C6S",
 335                 .desc = "MWAIT 0x52",
 336                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 337                 .exit_latency = 200,
 338                 .target_residency = 560,
 339                 .enter = &intel_idle,
 340                 .enter_s2idle = intel_idle_s2idle, },
 341         {
 342                 .name = "C7",
 343                 .desc = "MWAIT 0x60",
 344                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 345                 .exit_latency = 1200,
 346                 .target_residency = 4000,
 347                 .enter = &intel_idle,
 348                 .enter_s2idle = intel_idle_s2idle, },
 349         {
 350                 .name = "C7S",
 351                 .desc = "MWAIT 0x64",
 352                 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
 353                 .exit_latency = 10000,
 354                 .target_residency = 20000,
 355                 .enter = &intel_idle,
 356                 .enter_s2idle = intel_idle_s2idle, },
 357         {
 358                 .enter = NULL }
 359 };
 360
 361 static struct cpuidle_state ivb_cstates[] __initdata = {
 362         {
 363                 .name = "C1",
 364                 .desc = "MWAIT 0x00",
 365                 .flags = MWAIT2flg(0x00),
 366                 .exit_latency = 1,
 367                 .target_residency = 1,
 368                 .enter = &intel_idle,
 369                 .enter_s2idle = intel_idle_s2idle, },
 370         {
 371                 .name = "C1E",
 372                 .desc = "MWAIT 0x01",
 373                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 374                 .exit_latency = 10,
 375                 .target_residency = 20,
 376                 .enter = &intel_idle,
 377                 .enter_s2idle = intel_idle_s2idle, },
 378         {
 379                 .name = "C3",
 380                 .desc = "MWAIT 0x10",
 381                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 382                 .exit_latency = 59,
 383                 .target_residency = 156,
 384                 .enter = &intel_idle,
 385                 .enter_s2idle = intel_idle_s2idle, },
 386         {
 387                 .name = "C6",
 388                 .desc = "MWAIT 0x20",
 389                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 390                 .exit_latency = 80,
 391                 .target_residency = 300,
 392                 .enter = &intel_idle,
 393                 .enter_s2idle = intel_idle_s2idle, },
 394         {
 395                 .name = "C7",
 396                 .desc = "MWAIT 0x30",
 397                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 398                 .exit_latency = 87,
 399                 .target_residency = 300,
 400                 .enter = &intel_idle,
 401                 .enter_s2idle = intel_idle_s2idle, },
 402         {
 403                 .enter = NULL }
 404 };
 405
 406 static struct cpuidle_state ivt_cstates[] __initdata = {
 407         {
 408                 .name = "C1",
 409                 .desc = "MWAIT 0x00",
 410                 .flags = MWAIT2flg(0x00),
 411                 .exit_latency = 1,
 412                 .target_residency = 1,
 413                 .enter = &intel_idle,
 414                 .enter_s2idle = intel_idle_s2idle, },
 415         {
 416                 .name = "C1E",
 417                 .desc = "MWAIT 0x01",
 418                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 419                 .exit_latency = 10,
 420                 .target_residency = 80,
 421                 .enter = &intel_idle,
 422                 .enter_s2idle = intel_idle_s2idle, },
 423         {
 424                 .name = "C3",
 425                 .desc = "MWAIT 0x10",
 426                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 427                 .exit_latency = 59,
 428                 .target_residency = 156,
 429                 .enter = &intel_idle,
 430                 .enter_s2idle = intel_idle_s2idle, },
 431         {
 432                 .name = "C6",
 433                 .desc = "MWAIT 0x20",
 434                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 435                 .exit_latency = 82,
 436                 .target_residency = 300,
 437                 .enter = &intel_idle,
 438                 .enter_s2idle = intel_idle_s2idle, },
 439         {
 440                 .enter = NULL }
 441 };
 442
 443 static struct cpuidle_state ivt_cstates_4s[] __initdata = {
 444         {
 445                 .name = "C1",
 446                 .desc = "MWAIT 0x00",
 447                 .flags = MWAIT2flg(0x00),
 448                 .exit_latency = 1,
 449                 .target_residency = 1,
 450                 .enter = &intel_idle,
 451                 .enter_s2idle = intel_idle_s2idle, },
 452         {
 453                 .name = "C1E",
 454                 .desc = "MWAIT 0x01",
 455                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 456                 .exit_latency = 10,
 457                 .target_residency = 250,
 458                 .enter = &intel_idle,
 459                 .enter_s2idle = intel_idle_s2idle, },
 460         {
 461                 .name = "C3",
 462                 .desc = "MWAIT 0x10",
 463                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 464                 .exit_latency = 59,
 465                 .target_residency = 300,
 466                 .enter = &intel_idle,
 467                 .enter_s2idle = intel_idle_s2idle, },
 468         {
 469                 .name = "C6",
 470                 .desc = "MWAIT 0x20",
 471                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 472                 .exit_latency = 84,
 473                 .target_residency = 400,
 474                 .enter = &intel_idle,
 475                 .enter_s2idle = intel_idle_s2idle, },
 476         {
 477                 .enter = NULL }
 478 };
 479
 480 static struct cpuidle_state ivt_cstates_8s[] __initdata = {
 481         {
 482                 .name = "C1",
 483                 .desc = "MWAIT 0x00",
 484                 .flags = MWAIT2flg(0x00),
 485                 .exit_latency = 1,
 486                 .target_residency = 1,
 487                 .enter = &intel_idle,
 488                 .enter_s2idle = intel_idle_s2idle, },
 489         {
 490                 .name = "C1E",
 491                 .desc = "MWAIT 0x01",
 492                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 493                 .exit_latency = 10,
 494                 .target_residency = 500,
 495                 .enter = &intel_idle,
 496                 .enter_s2idle = intel_idle_s2idle, },
 497         {
 498                 .name = "C3",
 499                 .desc = "MWAIT 0x10",
 500                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 501                 .exit_latency = 59,
 502                 .target_residency = 600,
 503                 .enter = &intel_idle,
 504                 .enter_s2idle = intel_idle_s2idle, },
 505         {
 506                 .name = "C6",
 507                 .desc = "MWAIT 0x20",
 508                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 509                 .exit_latency = 88,
 510                 .target_residency = 700,
 511                 .enter = &intel_idle,
 512                 .enter_s2idle = intel_idle_s2idle, },
 513         {
 514                 .enter = NULL }
 515 };
 516
 517 static struct cpuidle_state hsw_cstates[] __initdata = {
 518         {
 519                 .name = "C1",
 520                 .desc = "MWAIT 0x00",
 521                 .flags = MWAIT2flg(0x00),
 522                 .exit_latency = 2,
 523                 .target_residency = 2,
 524                 .enter = &intel_idle,
 525                 .enter_s2idle = intel_idle_s2idle, },
 526         {
 527                 .name = "C1E",
 528                 .desc = "MWAIT 0x01",
 529                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 530                 .exit_latency = 10,
 531                 .target_residency = 20,
 532                 .enter = &intel_idle,
 533                 .enter_s2idle = intel_idle_s2idle, },
 534         {
 535                 .name = "C3",
 536                 .desc = "MWAIT 0x10",
 537                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 538                 .exit_latency = 33,
 539                 .target_residency = 100,
 540                 .enter = &intel_idle,
 541                 .enter_s2idle = intel_idle_s2idle, },
 542         {
 543                 .name = "C6",
 544                 .desc = "MWAIT 0x20",
 545                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 546                 .exit_latency = 133,
 547                 .target_residency = 400,
 548                 .enter = &intel_idle,
 549                 .enter_s2idle = intel_idle_s2idle, },
 550         {
 551                 .name = "C7s",
 552                 .desc = "MWAIT 0x32",
 553                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
 554                 .exit_latency = 166,
 555                 .target_residency = 500,
 556                 .enter = &intel_idle,
 557                 .enter_s2idle = intel_idle_s2idle, },
 558         {
 559                 .name = "C8",
 560                 .desc = "MWAIT 0x40",
 561                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 562                 .exit_latency = 300,
 563                 .target_residency = 900,
 564                 .enter = &intel_idle,
 565                 .enter_s2idle = intel_idle_s2idle, },
 566         {
 567                 .name = "C9",
 568                 .desc = "MWAIT 0x50",
 569                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 570                 .exit_latency = 600,
 571                 .target_residency = 1800,
 572                 .enter = &intel_idle,
 573                 .enter_s2idle = intel_idle_s2idle, },
 574         {
 575                 .name = "C10",
 576                 .desc = "MWAIT 0x60",
 577                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 578                 .exit_latency = 2600,
 579                 .target_residency = 7700,
 580                 .enter = &intel_idle,
 581                 .enter_s2idle = intel_idle_s2idle, },
 582         {
 583                 .enter = NULL }
 584 };
 585 static struct cpuidle_state bdw_cstates[] __initdata = {
 586         {
 587                 .name = "C1",
 588                 .desc = "MWAIT 0x00",
 589                 .flags = MWAIT2flg(0x00),
 590                 .exit_latency = 2,
 591                 .target_residency = 2,
 592                 .enter = &intel_idle,
 593                 .enter_s2idle = intel_idle_s2idle, },
 594         {
 595                 .name = "C1E",
 596                 .desc = "MWAIT 0x01",
 597                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 598                 .exit_latency = 10,
 599                 .target_residency = 20,
 600                 .enter = &intel_idle,
 601                 .enter_s2idle = intel_idle_s2idle, },
 602         {
 603                 .name = "C3",
 604                 .desc = "MWAIT 0x10",
 605                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 606                 .exit_latency = 40,
 607                 .target_residency = 100,
 608                 .enter = &intel_idle,
 609                 .enter_s2idle = intel_idle_s2idle, },
 610         {
 611                 .name = "C6",
 612                 .desc = "MWAIT 0x20",
 613                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 614                 .exit_latency = 133,
 615                 .target_residency = 400,
 616                 .enter = &intel_idle,
 617                 .enter_s2idle = intel_idle_s2idle, },
 618         {
 619                 .name = "C7s",
 620                 .desc = "MWAIT 0x32",
 621                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
 622                 .exit_latency = 166,
 623                 .target_residency = 500,
 624                 .enter = &intel_idle,
 625                 .enter_s2idle = intel_idle_s2idle, },
 626         {
 627                 .name = "C8",
 628                 .desc = "MWAIT 0x40",
 629                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 630                 .exit_latency = 300,
 631                 .target_residency = 900,
 632                 .enter = &intel_idle,
 633                 .enter_s2idle = intel_idle_s2idle, },
 634         {
 635                 .name = "C9",
 636                 .desc = "MWAIT 0x50",
 637                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 638                 .exit_latency = 600,
 639                 .target_residency = 1800,
 640                 .enter = &intel_idle,
 641                 .enter_s2idle = intel_idle_s2idle, },
 642         {
 643                 .name = "C10",
 644                 .desc = "MWAIT 0x60",
 645                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 646                 .exit_latency = 2600,
 647                 .target_residency = 7700,
 648                 .enter = &intel_idle,
 649                 .enter_s2idle = intel_idle_s2idle, },
 650         {
 651                 .enter = NULL }
 652 };
 653
 654 static struct cpuidle_state skl_cstates[] __initdata = {
 655         {
 656                 .name = "C1",
 657                 .desc = "MWAIT 0x00",
 658                 .flags = MWAIT2flg(0x00),
 659                 .exit_latency = 2,
 660                 .target_residency = 2,
 661                 .enter = &intel_idle,
 662                 .enter_s2idle = intel_idle_s2idle, },
 663         {
 664                 .name = "C1E",
 665                 .desc = "MWAIT 0x01",
 666                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 667                 .exit_latency = 10,
 668                 .target_residency = 20,
 669                 .enter = &intel_idle,
 670                 .enter_s2idle = intel_idle_s2idle, },
 671         {
 672                 .name = "C3",
 673                 .desc = "MWAIT 0x10",
 674                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 675                 .exit_latency = 70,
 676                 .target_residency = 100,
 677                 .enter = &intel_idle,
 678                 .enter_s2idle = intel_idle_s2idle, },
 679         {
 680                 .name = "C6",
 681                 .desc = "MWAIT 0x20",
 682                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
 683                 .exit_latency = 85,
 684                 .target_residency = 200,
 685                 .enter = &intel_idle,
 686                 .enter_s2idle = intel_idle_s2idle, },
 687         {
 688                 .name = "C7s",
 689                 .desc = "MWAIT 0x33",
 690                 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
 691                 .exit_latency = 124,
 692                 .target_residency = 800,
 693                 .enter = &intel_idle,
 694                 .enter_s2idle = intel_idle_s2idle, },
 695         {
 696                 .name = "C8",
 697                 .desc = "MWAIT 0x40",
 698                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
 699                 .exit_latency = 200,
 700                 .target_residency = 800,
 701                 .enter = &intel_idle,
 702                 .enter_s2idle = intel_idle_s2idle, },
 703         {
 704                 .name = "C9",
 705                 .desc = "MWAIT 0x50",
 706                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
 707                 .exit_latency = 480,
 708                 .target_residency = 5000,
 709                 .enter = &intel_idle,
 710                 .enter_s2idle = intel_idle_s2idle, },
 711         {
 712                 .name = "C10",
 713                 .desc = "MWAIT 0x60",
 714                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
 715                 .exit_latency = 890,
 716                 .target_residency = 5000,
 717                 .enter = &intel_idle,
 718                 .enter_s2idle = intel_idle_s2idle, },
 719         {
 720                 .enter = NULL }
 721 };
 722
 723 static struct cpuidle_state skx_cstates[] __initdata = {
 724         {
 725                 .name = "C1",
 726                 .desc = "MWAIT 0x00",
 727                 .flags = MWAIT2flg(0x00),
 728                 .exit_latency = 2,
 729                 .target_residency = 2,
 730                 .enter = &intel_idle,
 731                 .enter_s2idle = intel_idle_s2idle, },
 732         {
 733                 .name = "C1E",
 734                 .desc = "MWAIT 0x01",
 735                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 736                 .exit_latency = 10,
 737                 .target_residency = 20,
 738                 .enter = &intel_idle,
 739                 .enter_s2idle = intel_idle_s2idle, },
 740         {
 741                 .name = "C6",
 742                 .desc = "MWAIT 0x20",
 743                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
 744                 .exit_latency = 133,
 745                 .target_residency = 600,
 746                 .enter = &intel_idle,
 747                 .enter_s2idle = intel_idle_s2idle, },
 748         {
 749                 .enter = NULL }
 750 };
 751
 752 static struct cpuidle_state icx_cstates[] __initdata = {
 753         {
 754                 .name = "C1",
 755                 .desc = "MWAIT 0x00",
 756                 .flags = MWAIT2flg(0x00),
 757                 .exit_latency = 1,
 758                 .target_residency = 1,
 759                 .enter = &intel_idle,
 760                 .enter_s2idle = intel_idle_s2idle, },
 761         {
 762                 .name = "C1E",
 763                 .desc = "MWAIT 0x01",
 764                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 765                 .exit_latency = 4,
 766                 .target_residency = 4,
 767                 .enter = &intel_idle,
 768                 .enter_s2idle = intel_idle_s2idle, },
 769         {
 770                 .name = "C6",
 771                 .desc = "MWAIT 0x20",
 772                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 773                 .exit_latency = 170,
 774                 .target_residency = 600,
 775                 .enter = &intel_idle,
 776                 .enter_s2idle = intel_idle_s2idle, },
 777         {
 778                 .enter = NULL }
 779 };
 780
 781 static struct cpuidle_state atom_cstates[] __initdata = {
 782         {
 783                 .name = "C1E",
 784                 .desc = "MWAIT 0x00",
 785                 .flags = MWAIT2flg(0x00),
 786                 .exit_latency = 10,
 787                 .target_residency = 20,
 788                 .enter = &intel_idle,
 789                 .enter_s2idle = intel_idle_s2idle, },
 790         {
 791                 .name = "C2",
 792                 .desc = "MWAIT 0x10",
 793                 .flags = MWAIT2flg(0x10),
 794                 .exit_latency = 20,
 795                 .target_residency = 80,
 796                 .enter = &intel_idle,
 797                 .enter_s2idle = intel_idle_s2idle, },
 798         {
 799                 .name = "C4",
 800                 .desc = "MWAIT 0x30",
 801                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 802                 .exit_latency = 100,
 803                 .target_residency = 400,
 804                 .enter = &intel_idle,
 805                 .enter_s2idle = intel_idle_s2idle, },
 806         {
 807                 .name = "C6",
 808                 .desc = "MWAIT 0x52",
 809                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 810                 .exit_latency = 140,
 811                 .target_residency = 560,
 812                 .enter = &intel_idle,
 813                 .enter_s2idle = intel_idle_s2idle, },
 814         {
 815                 .enter = NULL }
 816 };
 817 static struct cpuidle_state tangier_cstates[] __initdata = {
 818         {
 819                 .name = "C1",
 820                 .desc = "MWAIT 0x00",
 821                 .flags = MWAIT2flg(0x00),
 822                 .exit_latency = 1,
 823                 .target_residency = 4,
 824                 .enter = &intel_idle,
 825                 .enter_s2idle = intel_idle_s2idle, },
 826         {
 827                 .name = "C4",
 828                 .desc = "MWAIT 0x30",
 829                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 830                 .exit_latency = 100,
 831                 .target_residency = 400,
 832                 .enter = &intel_idle,
 833                 .enter_s2idle = intel_idle_s2idle, },
 834         {
 835                 .name = "C6",
 836                 .desc = "MWAIT 0x52",
 837                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 838                 .exit_latency = 140,
 839                 .target_residency = 560,
 840                 .enter = &intel_idle,
 841                 .enter_s2idle = intel_idle_s2idle, },
 842         {
 843                 .name = "C7",
 844                 .desc = "MWAIT 0x60",
 845                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 846                 .exit_latency = 1200,
 847                 .target_residency = 4000,
 848                 .enter = &intel_idle,
 849                 .enter_s2idle = intel_idle_s2idle, },
 850         {
 851                 .name = "C9",
 852                 .desc = "MWAIT 0x64",
 853                 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
 854                 .exit_latency = 10000,
 855                 .target_residency = 20000,
 856                 .enter = &intel_idle,
 857                 .enter_s2idle = intel_idle_s2idle, },
 858         {
 859                 .enter = NULL }
 860 };
 861 static struct cpuidle_state avn_cstates[] __initdata = {
 862         {
 863                 .name = "C1",
 864                 .desc = "MWAIT 0x00",
 865                 .flags = MWAIT2flg(0x00),
 866                 .exit_latency = 2,
 867                 .target_residency = 2,
 868                 .enter = &intel_idle,
 869                 .enter_s2idle = intel_idle_s2idle, },
 870         {
 871                 .name = "C6",
 872                 .desc = "MWAIT 0x51",
 873                 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
 874                 .exit_latency = 15,
 875                 .target_residency = 45,
 876                 .enter = &intel_idle,
 877                 .enter_s2idle = intel_idle_s2idle, },
 878         {
 879                 .enter = NULL }
 880 };
 881 static struct cpuidle_state knl_cstates[] __initdata = {
 882         {
 883                 .name = "C1",
 884                 .desc = "MWAIT 0x00",
 885                 .flags = MWAIT2flg(0x00),
 886                 .exit_latency = 1,
 887                 .target_residency = 2,
 888                 .enter = &intel_idle,
 889                 .enter_s2idle = intel_idle_s2idle },
 890         {
 891                 .name = "C6",
 892                 .desc = "MWAIT 0x10",
 893                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 894                 .exit_latency = 120,
 895                 .target_residency = 500,
 896                 .enter = &intel_idle,
 897                 .enter_s2idle = intel_idle_s2idle },
 898         {
 899                 .enter = NULL }
 900 };
 901
 902 static struct cpuidle_state bxt_cstates[] __initdata = {
 903         {
 904                 .name = "C1",
 905                 .desc = "MWAIT 0x00",
 906                 .flags = MWAIT2flg(0x00),
 907                 .exit_latency = 2,
 908                 .target_residency = 2,
 909                 .enter = &intel_idle,
 910                 .enter_s2idle = intel_idle_s2idle, },
 911         {
 912                 .name = "C1E",
 913                 .desc = "MWAIT 0x01",
 914                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 915                 .exit_latency = 10,
 916                 .target_residency = 20,
 917                 .enter = &intel_idle,
 918                 .enter_s2idle = intel_idle_s2idle, },
 919         {
 920                 .name = "C6",
 921                 .desc = "MWAIT 0x20",
 922                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 923                 .exit_latency = 133,
 924                 .target_residency = 133,
 925                 .enter = &intel_idle,
 926                 .enter_s2idle = intel_idle_s2idle, },
 927         {
 928                 .name = "C7s",
 929                 .desc = "MWAIT 0x31",
 930                 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
 931                 .exit_latency = 155,
 932                 .target_residency = 155,
 933                 .enter = &intel_idle,
 934                 .enter_s2idle = intel_idle_s2idle, },
 935         {
 936                 .name = "C8",
 937                 .desc = "MWAIT 0x40",
 938                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 939                 .exit_latency = 1000,
 940                 .target_residency = 1000,
 941                 .enter = &intel_idle,
 942                 .enter_s2idle = intel_idle_s2idle, },
 943         {
 944                 .name = "C9",
 945                 .desc = "MWAIT 0x50",
 946                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 947                 .exit_latency = 2000,
 948                 .target_residency = 2000,
 949                 .enter = &intel_idle,
 950                 .enter_s2idle = intel_idle_s2idle, },
 951         {
 952                 .name = "C10",
 953                 .desc = "MWAIT 0x60",
 954                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 955                 .exit_latency = 10000,
 956                 .target_residency = 10000,
 957                 .enter = &intel_idle,
 958                 .enter_s2idle = intel_idle_s2idle, },
 959         {
 960                 .enter = NULL }
 961 };
 962
 963 static struct cpuidle_state dnv_cstates[] __initdata = {
 964         {
 965                 .name = "C1",
 966                 .desc = "MWAIT 0x00",
 967                 .flags = MWAIT2flg(0x00),
 968                 .exit_latency = 2,
 969                 .target_residency = 2,
 970                 .enter = &intel_idle,
 971                 .enter_s2idle = intel_idle_s2idle, },
 972         {
 973                 .name = "C1E",
 974                 .desc = "MWAIT 0x01",
 975                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 976                 .exit_latency = 10,
 977                 .target_residency = 20,
 978                 .enter = &intel_idle,
 979                 .enter_s2idle = intel_idle_s2idle, },
 980         {
 981                 .name = "C6",
 982                 .desc = "MWAIT 0x20",
 983                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 984                 .exit_latency = 50,
 985                 .target_residency = 500,
 986                 .enter = &intel_idle,
 987                 .enter_s2idle = intel_idle_s2idle, },
 988         {
 989                 .enter = NULL }
 990 };
 991
 992 /*
 993  * Note, depending on HW and FW revision, SnowRidge SoC may or may not support
 994  * C6, and this is indicated in the CPUID mwait leaf.
 995  */
 996 static struct cpuidle_state snr_cstates[] __initdata = {
 997         {
 998                 .name = "C1",
 999                 .desc = "MWAIT 0x00",
1000                 .flags = MWAIT2flg(0x00),
1001                 .exit_latency = 2,
1002                 .target_residency = 2,
1003                 .enter = &intel_idle,
1004                 .enter_s2idle = intel_idle_s2idle, },
1005         {
1006                 .name = "C1E",
1007                 .desc = "MWAIT 0x01",
1008                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1009                 .exit_latency = 15,
1010                 .target_residency = 25,
1011                 .enter = &intel_idle,
1012                 .enter_s2idle = intel_idle_s2idle, },
1013         {
1014                 .name = "C6",
1015                 .desc = "MWAIT 0x20",
1016                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
1017                 .exit_latency = 130,
1018                 .target_residency = 500,
1019                 .enter = &intel_idle,
1020                 .enter_s2idle = intel_idle_s2idle, },
1021         {
1022                 .enter = NULL }
1023 };
1024
1025 static const struct idle_cpu idle_cpu_nehalem __initconst = {
1026         .state_table = nehalem_cstates,
1027         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1028         .disable_promotion_to_c1e = true,
1029 };
1030
1031 static const struct idle_cpu idle_cpu_nhx __initconst = {
1032         .state_table = nehalem_cstates,
1033         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1034         .disable_promotion_to_c1e = true,
1035         .use_acpi = true,
1036 };
1037
1038 static const struct idle_cpu idle_cpu_atom __initconst = {
1039         .state_table = atom_cstates,
1040 };
1041
1042 static const struct idle_cpu idle_cpu_tangier __initconst = {
1043         .state_table = tangier_cstates,
1044 };
1045
1046 static const struct idle_cpu idle_cpu_lincroft __initconst = {
1047         .state_table = atom_cstates,
1048         .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
1049 };
1050
1051 static const struct idle_cpu idle_cpu_snb __initconst = {
1052         .state_table = snb_cstates,
1053         .disable_promotion_to_c1e = true,
1054 };
1055
1056 static const struct idle_cpu idle_cpu_snx __initconst = {
1057         .state_table = snb_cstates,
1058         .disable_promotion_to_c1e = true,
1059         .use_acpi = true,
1060 };
1061
1062 static const struct idle_cpu idle_cpu_byt __initconst = {
1063         .state_table = byt_cstates,
1064         .disable_promotion_to_c1e = true,
1065         .byt_auto_demotion_disable_flag = true,
1066 };
1067
1068 static const struct idle_cpu idle_cpu_cht __initconst = {
1069         .state_table = cht_cstates,
1070         .disable_promotion_to_c1e = true,
1071         .byt_auto_demotion_disable_flag = true,
1072 };
1073
1074 static const struct idle_cpu idle_cpu_ivb __initconst = {
1075         .state_table = ivb_cstates,
1076         .disable_promotion_to_c1e = true,
1077 };
1078
1079 static const struct idle_cpu idle_cpu_ivt __initconst = {
1080         .state_table = ivt_cstates,
1081         .disable_promotion_to_c1e = true,
1082         .use_acpi = true,
1083 };
1084
1085 static const struct idle_cpu idle_cpu_hsw __initconst = {
1086         .state_table = hsw_cstates,
1087         .disable_promotion_to_c1e = true,
1088 };
1089
1090 static const struct idle_cpu idle_cpu_hsx __initconst = {
1091         .state_table = hsw_cstates,
1092         .disable_promotion_to_c1e = true,
1093         .use_acpi = true,
1094 };
1095
1096 static const struct idle_cpu idle_cpu_bdw __initconst = {
1097         .state_table = bdw_cstates,
1098         .disable_promotion_to_c1e = true,
1099 };
1100
1101 static const struct idle_cpu idle_cpu_bdx __initconst = {
1102         .state_table = bdw_cstates,
1103         .disable_promotion_to_c1e = true,
1104         .use_acpi = true,
1105 };
1106
1107 static const struct idle_cpu idle_cpu_skl __initconst = {
1108         .state_table = skl_cstates,
1109         .disable_promotion_to_c1e = true,
1110 };
1111
1112 static const struct idle_cpu idle_cpu_skx __initconst = {
1113         .state_table = skx_cstates,
1114         .disable_promotion_to_c1e = true,
1115         .use_acpi = true,
1116 };
1117
1118 static const struct idle_cpu idle_cpu_icx __initconst = {
1119         .state_table = icx_cstates,
1120         .disable_promotion_to_c1e = true,
1121         .use_acpi = true,
1122 };
1123
1124 static const struct idle_cpu idle_cpu_avn __initconst = {
1125         .state_table = avn_cstates,
1126         .disable_promotion_to_c1e = true,
1127         .use_acpi = true,
1128 };
1129
1130 static const struct idle_cpu idle_cpu_knl __initconst = {
1131         .state_table = knl_cstates,
1132         .use_acpi = true,
1133 };
1134
1135 static const struct idle_cpu idle_cpu_bxt __initconst = {
1136         .state_table = bxt_cstates,
1137         .disable_promotion_to_c1e = true,
1138 };
1139
1140 static const struct idle_cpu idle_cpu_dnv __initconst = {
1141         .state_table = dnv_cstates,
1142         .disable_promotion_to_c1e = true,
1143         .use_acpi = true,
1144 };
1145
1146 static const struct idle_cpu idle_cpu_snr __initconst = {
1147         .state_table = snr_cstates,
1148         .disable_promotion_to_c1e = true,
1149         .use_acpi = true,
1150 };
1151
1152 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1153         X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP,          &idle_cpu_nhx),
1154         X86_MATCH_INTEL_FAM6_MODEL(NEHALEM,             &idle_cpu_nehalem),
1155         X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G,           &idle_cpu_nehalem),
1156         X86_MATCH_INTEL_FAM6_MODEL(WESTMERE,            &idle_cpu_nehalem),
1157         X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP,         &idle_cpu_nhx),
1158         X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX,          &idle_cpu_nhx),
1159         X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL,        &idle_cpu_atom),
1160         X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID,    &idle_cpu_lincroft),
1161         X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX,         &idle_cpu_nhx),
1162         X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE,         &idle_cpu_snb),
1163         X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X,       &idle_cpu_snx),
1164         X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL,       &idle_cpu_atom),
1165         X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT,     &idle_cpu_byt),
1166         X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &idle_cpu_tangier),
1167         X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT,        &idle_cpu_cht),
1168         X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE,           &idle_cpu_ivb),
1169         X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X,         &idle_cpu_ivt),
1170         X86_MATCH_INTEL_FAM6_MODEL(HASWELL,             &idle_cpu_hsw),
1171         X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X,           &idle_cpu_hsx),
1172         X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L,           &idle_cpu_hsw),
1173         X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G,           &idle_cpu_hsw),
1174         X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D,   &idle_cpu_avn),
1175         X86_MATCH_INTEL_FAM6_MODEL(BROADWELL,           &idle_cpu_bdw),
1176         X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G,         &idle_cpu_bdw),
1177         X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X,         &idle_cpu_bdx),
1178         X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D,         &idle_cpu_bdx),
1179         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,           &idle_cpu_skl),
1180         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,             &idle_cpu_skl),
1181         X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,          &idle_cpu_skl),
1182         X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,            &idle_cpu_skl),
1183         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X,           &idle_cpu_skx),
1184         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,           &idle_cpu_icx),
1185         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,           &idle_cpu_icx),
1186         X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,        &idle_cpu_knl),
1187         X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM,        &idle_cpu_knl),
1188         X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,       &idle_cpu_bxt),
1189         X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS,  &idle_cpu_bxt),
1190         X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,     &idle_cpu_dnv),
1191         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,      &idle_cpu_snr),
1192         {}
1193 };
1194
1195 static const struct x86_cpu_id intel_mwait_ids[] __initconst = {
1196         X86_MATCH_VENDOR_FAM_FEATURE(INTEL, 6, X86_FEATURE_MWAIT, NULL),
1197         {}
1198 };
1199
1200 static bool __init intel_idle_max_cstate_reached(int cstate)
1201 {
1202         if (cstate + 1 > max_cstate) {
1203                 pr_info("max_cstate %d reached\n", max_cstate);
1204                 return true;
1205         }
1206         return false;
1207 }
1208
1209 static bool __init intel_idle_state_needs_timer_stop(struct cpuidle_state *state)
1210 {
1211         unsigned long eax = flg2MWAIT(state->flags);
1212
1213         if (boot_cpu_has(X86_FEATURE_ARAT))
1214                 return false;
1215
1216         /*
1217          * Switch over to one-shot tick broadcast if the target C-state
1218          * is deeper than C1.
1219          */
1220         return !!((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK);
1221 }
1222
1223 #ifdef CONFIG_ACPI_PROCESSOR_CSTATE
1224 #include <acpi/processor.h>
1225
1226 static bool no_acpi __read_mostly;
1227 module_param(no_acpi, bool, 0444);
1228 MODULE_PARM_DESC(no_acpi, "Do not use ACPI _CST for building the idle states list");
1229
1230 static bool force_use_acpi __read_mostly; /* No effect if no_acpi is set. */
1231 module_param_named(use_acpi, force_use_acpi, bool, 0444);
1232 MODULE_PARM_DESC(use_acpi, "Use ACPI _CST for building the idle states list");
1233
1234 static struct acpi_processor_power acpi_state_table __initdata;
1235
1236 /**
1237  * intel_idle_cst_usable - Check if the _CST information can be used.
1238  *
1239  * Check if all of the C-states listed by _CST in the max_cstate range are
1240  * ACPI_CSTATE_FFH, which means that they should be entered via MWAIT.
1241  */
1242 static bool __init intel_idle_cst_usable(void)
1243 {
1244         int cstate, limit;
1245
1246         limit = min_t(int, min_t(int, CPUIDLE_STATE_MAX, max_cstate + 1),
1247                       acpi_state_table.count);
1248
1249         for (cstate = 1; cstate < limit; cstate++) {
1250                 struct acpi_processor_cx *cx = &acpi_state_table.states[cstate];
1251
1252                 if (cx->entry_method != ACPI_CSTATE_FFH)
1253                         return false;
1254         }
1255
1256         return true;
1257 }
1258
1259 static bool __init intel_idle_acpi_cst_extract(void)
1260 {
1261         unsigned int cpu;
1262
1263         if (no_acpi) {
1264                 pr_debug("Not allowed to use ACPI _CST\n");
1265                 return false;
1266         }
1267
1268         for_each_possible_cpu(cpu) {
1269                 struct acpi_processor *pr = per_cpu(processors, cpu);
1270
1271                 if (!pr)
1272                         continue;
1273
1274                 if (acpi_processor_evaluate_cst(pr->handle, cpu, &acpi_state_table))
1275                         continue;
1276
1277                 acpi_state_table.count++;
1278
1279                 if (!intel_idle_cst_usable())
1280                         continue;
1281
1282                 if (!acpi_processor_claim_cst_control())
1283                         break;
1284
1285                 return true;
1286         }
1287
1288         acpi_state_table.count = 0;
1289         pr_debug("ACPI _CST not found or not usable\n");
1290         return false;
1291 }
1292
1293 static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
1294 {
1295         int cstate, limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1296
1297         /*
1298          * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1299          * the interesting states are ACPI_CSTATE_FFH.
1300          */
1301         for (cstate = 1; cstate < limit; cstate++) {
1302                 struct acpi_processor_cx *cx;
1303                 struct cpuidle_state *state;
1304
1305                 if (intel_idle_max_cstate_reached(cstate - 1))
1306                         break;
1307
1308                 cx = &acpi_state_table.states[cstate];
1309
1310                 state = &drv->states[drv->state_count++];
1311
1312                 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d_ACPI", cstate);
1313                 strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1314                 state->exit_latency = cx->latency;
1315                 /*
1316                  * For C1-type C-states use the same number for both the exit
1317                  * latency and target residency, because that is the case for
1318                  * C1 in the majority of the static C-states tables above.
1319                  * For the other types of C-states, however, set the target
1320                  * residency to 3 times the exit latency which should lead to
1321                  * a reasonable balance between energy-efficiency and
1322                  * performance in the majority of interesting cases.
1323                  */
1324                 state->target_residency = cx->latency;
1325                 if (cx->type > ACPI_STATE_C1)
1326                         state->target_residency *= 3;
1327
1328                 state->flags = MWAIT2flg(cx->address);
1329                 if (cx->type > ACPI_STATE_C2)
1330                         state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
1331
1332                 if (disabled_states_mask & BIT(cstate))
1333                         state->flags |= CPUIDLE_FLAG_OFF;
1334
1335                 if (intel_idle_state_needs_timer_stop(state))
1336                         state->flags |= CPUIDLE_FLAG_TIMER_STOP;
1337
1338                 state->enter = intel_idle;
1339                 state->enter_s2idle = intel_idle_s2idle;
1340         }
1341 }
1342
1343 static bool __init intel_idle_off_by_default(u32 mwait_hint)
1344 {
1345         int cstate, limit;
1346
1347         /*
1348          * If there are no _CST C-states, do not disable any C-states by
1349          * default.
1350          */
1351         if (!acpi_state_table.count)
1352                 return false;
1353
1354         limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1355         /*
1356          * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1357          * the interesting states are ACPI_CSTATE_FFH.
1358          */
1359         for (cstate = 1; cstate < limit; cstate++) {
1360                 if (acpi_state_table.states[cstate].address == mwait_hint)
1361                         return false;
1362         }
1363         return true;
1364 }
1365 #else /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1366 #define force_use_acpi  (false)
1367
1368 static inline bool intel_idle_acpi_cst_extract(void) { return false; }
1369 static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
1370 static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
1371 #endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1372
1373 /**
1374  * ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
1375  *
1376  * Tune IVT multi-socket targets.
1377  * Assumption: num_sockets == (max_package_num + 1).
1378  */
1379 static void __init ivt_idle_state_table_update(void)
1380 {
1381         /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1382         int cpu, package_num, num_sockets = 1;
1383
1384         for_each_online_cpu(cpu) {
1385                 package_num = topology_physical_package_id(cpu);
1386                 if (package_num + 1 > num_sockets) {
1387                         num_sockets = package_num + 1;
1388
1389                         if (num_sockets > 4) {
1390                                 cpuidle_state_table = ivt_cstates_8s;
1391                                 return;
1392                         }
1393                 }
1394         }
1395
1396         if (num_sockets > 2)
1397                 cpuidle_state_table = ivt_cstates_4s;
1398
1399         /* else, 1 and 2 socket systems use default ivt_cstates */
1400 }
1401
1402 /**
1403  * irtl_2_usec - IRTL to microseconds conversion.
1404  * @irtl: IRTL MSR value.
1405  *
1406  * Translate the IRTL (Interrupt Response Time Limit) MSR value to microseconds.
1407  */
1408 static unsigned long long __init irtl_2_usec(unsigned long long irtl)
1409 {
1410         static const unsigned int irtl_ns_units[] __initconst = {
1411                 1, 32, 1024, 32768, 1048576, 33554432, 0, 0
1412         };
1413         unsigned long long ns;
1414
1415         if (!irtl)
1416                 return 0;
1417
1418         ns = irtl_ns_units[(irtl >> 10) & 0x7];
1419
1420         return div_u64((irtl & 0x3FF) * ns, NSEC_PER_USEC);
1421 }
1422
1423 /**
1424  * bxt_idle_state_table_update - Fix up the Broxton idle states table.
1425  *
1426  * On BXT, trust the IRTL (Interrupt Response Time Limit) MSR to show the
1427  * definitive maximum latency and use the same value for target_residency.
1428  */
1429 static void __init bxt_idle_state_table_update(void)
1430 {
1431         unsigned long long msr;
1432         unsigned int usec;
1433
1434         rdmsrl(MSR_PKGC6_IRTL, msr);
1435         usec = irtl_2_usec(msr);
1436         if (usec) {
1437                 bxt_cstates[2].exit_latency = usec;
1438                 bxt_cstates[2].target_residency = usec;
1439         }
1440
1441         rdmsrl(MSR_PKGC7_IRTL, msr);
1442         usec = irtl_2_usec(msr);
1443         if (usec) {
1444                 bxt_cstates[3].exit_latency = usec;
1445                 bxt_cstates[3].target_residency = usec;
1446         }
1447
1448         rdmsrl(MSR_PKGC8_IRTL, msr);
1449         usec = irtl_2_usec(msr);
1450         if (usec) {
1451                 bxt_cstates[4].exit_latency = usec;
1452                 bxt_cstates[4].target_residency = usec;
1453         }
1454
1455         rdmsrl(MSR_PKGC9_IRTL, msr);
1456         usec = irtl_2_usec(msr);
1457         if (usec) {
1458                 bxt_cstates[5].exit_latency = usec;
1459                 bxt_cstates[5].target_residency = usec;
1460         }
1461
1462         rdmsrl(MSR_PKGC10_IRTL, msr);
1463         usec = irtl_2_usec(msr);
1464         if (usec) {
1465                 bxt_cstates[6].exit_latency = usec;
1466                 bxt_cstates[6].target_residency = usec;
1467         }
1468
1469 }
1470
1471 /**
1472  * sklh_idle_state_table_update - Fix up the Sky Lake idle states table.
1473  *
1474  * On SKL-H (model 0x5e) skip C8 and C9 if C10 is enabled and SGX disabled.
1475  */
1476 static void __init sklh_idle_state_table_update(void)
1477 {
1478         unsigned long long msr;
1479         unsigned int eax, ebx, ecx, edx;
1480
1481
1482         /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1483         if (max_cstate <= 7)
1484                 return;
1485
1486         /* if PC10 not present in CPUID.MWAIT.EDX */
1487         if ((mwait_substates & (0xF << 28)) == 0)
1488                 return;
1489
1490         rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1491
1492         /* PC10 is not enabled in PKG C-state limit */
1493         if ((msr & 0xF) != 8)
1494                 return;
1495
1496         ecx = 0;
1497         cpuid(7, &eax, &ebx, &ecx, &edx);
1498
1499         /* if SGX is present */
1500         if (ebx & (1 << 2)) {
1501
1502                 rdmsrl(MSR_IA32_FEAT_CTL, msr);
1503
1504                 /* if SGX is enabled */
1505                 if (msr & (1 << 18))
1506                         return;
1507         }
1508
1509         skl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE;  /* C8-SKL */
1510         skl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE;  /* C9-SKL */
1511 }
1512
1513 /**
1514  * skx_idle_state_table_update - Adjust the Sky Lake/Cascade Lake
1515  * idle states table.
1516  */
1517 static void __init skx_idle_state_table_update(void)
1518 {
1519         unsigned long long msr;
1520
1521         rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1522
1523         /*
1524          * 000b: C0/C1 (no package C-state support)
1525          * 001b: C2
1526          * 010b: C6 (non-retention)
1527          * 011b: C6 (retention)
1528          * 111b: No Package C state limits.
1529          */
1530         if ((msr & 0x7) < 2) {
1531                 /*
1532                  * Uses the CC6 + PC0 latency and 3 times of
1533                  * latency for target_residency if the PC6
1534                  * is disabled in BIOS. This is consistent
1535                  * with how intel_idle driver uses _CST
1536                  * to set the target_residency.
1537                  */
1538                 skx_cstates[2].exit_latency = 92;
1539                 skx_cstates[2].target_residency = 276;
1540         }
1541 }
1542
1543 static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
1544 {
1545         unsigned int mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint) + 1;
1546         unsigned int num_substates = (mwait_substates >> mwait_cstate * 4) &
1547                                         MWAIT_SUBSTATE_MASK;
1548
1549         /* Ignore the C-state if there are NO sub-states in CPUID for it. */
1550         if (num_substates == 0)
1551                 return false;
1552
1553         if (mwait_cstate > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1554                 mark_tsc_unstable("TSC halts in idle states deeper than C2");
1555
1556         return true;
1557 }
1558
1559 static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
1560 {
1561         int cstate;
1562
1563         switch (boot_cpu_data.x86_model) {
1564         case INTEL_FAM6_IVYBRIDGE_X:
1565                 ivt_idle_state_table_update();
1566                 break;
1567         case INTEL_FAM6_ATOM_GOLDMONT:
1568         case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
1569                 bxt_idle_state_table_update();
1570                 break;
1571         case INTEL_FAM6_SKYLAKE:
1572                 sklh_idle_state_table_update();
1573                 break;
1574         case INTEL_FAM6_SKYLAKE_X:
1575                 skx_idle_state_table_update();
1576                 break;
1577         }
1578
1579         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1580                 unsigned int mwait_hint;
1581
1582                 if (intel_idle_max_cstate_reached(cstate))
1583                         break;
1584
1585                 if (!cpuidle_state_table[cstate].enter &&
1586                     !cpuidle_state_table[cstate].enter_s2idle)
1587                         break;
1588
1589                 /* If marked as unusable, skip this state. */
1590                 if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) {
1591                         pr_debug("state %s is disabled\n",
1592                                  cpuidle_state_table[cstate].name);
1593                         continue;
1594                 }
1595
1596                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1597                 if (!intel_idle_verify_cstate(mwait_hint))
1598                         continue;
1599
1600                 /* Structure copy. */
1601                 drv->states[drv->state_count] = cpuidle_state_table[cstate];
1602
1603                 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS) &&
1604                     cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_IBRS) {
1605                         drv->states[drv->state_count].enter = intel_idle_ibrs;
1606                 }
1607
1608                 if ((disabled_states_mask & BIT(drv->state_count)) ||
1609                     ((icpu->use_acpi || force_use_acpi) &&
1610                      intel_idle_off_by_default(mwait_hint) &&
1611                      !(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
1612                         drv->states[drv->state_count].flags |= CPUIDLE_FLAG_OFF;
1613
1614                 if (intel_idle_state_needs_timer_stop(&drv->states[drv->state_count]))
1615                         drv->states[drv->state_count].flags |= CPUIDLE_FLAG_TIMER_STOP;
1616
1617                 drv->state_count++;
1618         }
1619
1620         if (icpu->byt_auto_demotion_disable_flag) {
1621                 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1622                 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1623         }
1624 }
1625
1626 /**
1627  * intel_idle_cpuidle_driver_init - Create the list of available idle states.
1628  * @drv: cpuidle driver structure to initialize.
1629  */
1630 static void __init intel_idle_cpuidle_driver_init(struct cpuidle_driver *drv)
1631 {
1632         cpuidle_poll_state_init(drv);
1633
1634         if (disabled_states_mask & BIT(0))
1635                 drv->states[0].flags |= CPUIDLE_FLAG_OFF;
1636
1637         drv->state_count = 1;
1638
1639         if (icpu)
1640                 intel_idle_init_cstates_icpu(drv);
1641         else
1642                 intel_idle_init_cstates_acpi(drv);
1643 }
1644
1645 static void auto_demotion_disable(void)
1646 {
1647         unsigned long long msr_bits;
1648
1649         rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1650         msr_bits &= ~auto_demotion_disable_flags;
1651         wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1652 }
1653
1654 static void c1e_promotion_disable(void)
1655 {
1656         unsigned long long msr_bits;
1657
1658         rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
1659         msr_bits &= ~0x2;
1660         wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
1661 }
1662
1663 /**
1664  * intel_idle_cpu_init - Register the target CPU with the cpuidle core.
1665  * @cpu: CPU to initialize.
1666  *
1667  * Register a cpuidle device object for @cpu and update its MSRs in accordance
1668  * with the processor model flags.
1669  */
1670 static int intel_idle_cpu_init(unsigned int cpu)
1671 {
1672         struct cpuidle_device *dev;
1673
1674         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1675         dev->cpu = cpu;
1676
1677         if (cpuidle_register_device(dev)) {
1678                 pr_debug("cpuidle_register_device %d failed!\n", cpu);
1679                 return -EIO;
1680         }
1681
1682         if (auto_demotion_disable_flags)
1683                 auto_demotion_disable();
1684
1685         if (disable_promotion_to_c1e)
1686                 c1e_promotion_disable();
1687
1688         return 0;
1689 }
1690
1691 static int intel_idle_cpu_online(unsigned int cpu)
1692 {
1693         struct cpuidle_device *dev;
1694
1695         if (!boot_cpu_has(X86_FEATURE_ARAT))
1696                 tick_broadcast_enable();
1697
1698         /*
1699          * Some systems can hotplug a cpu at runtime after
1700          * the kernel has booted, we have to initialize the
1701          * driver in this case
1702          */
1703         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1704         if (!dev->registered)
1705                 return intel_idle_cpu_init(cpu);
1706
1707         return 0;
1708 }
1709
1710 /**
1711  * intel_idle_cpuidle_devices_uninit - Unregister all cpuidle devices.
1712  */
1713 static void __init intel_idle_cpuidle_devices_uninit(void)
1714 {
1715         int i;
1716
1717         for_each_online_cpu(i)
1718                 cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
1719 }
1720
1721 static int __init intel_idle_init(void)
1722 {
1723         const struct x86_cpu_id *id;
1724         unsigned int eax, ebx, ecx;
1725         int retval;
1726
1727         /* Do not load intel_idle at all for now if idle= is passed */
1728         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1729                 return -ENODEV;
1730
1731         if (max_cstate == 0) {
1732                 pr_debug("disabled\n");
1733                 return -EPERM;
1734         }
1735
1736         id = x86_match_cpu(intel_idle_ids);
1737         if (id) {
1738                 if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
1739                         pr_debug("Please enable MWAIT in BIOS SETUP\n");
1740                         return -ENODEV;
1741                 }
1742         } else {
1743                 id = x86_match_cpu(intel_mwait_ids);
1744                 if (!id)
1745                         return -ENODEV;
1746         }
1747
1748         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1749                 return -ENODEV;
1750
1751         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1752
1753         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1754             !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1755             !mwait_substates)
1756                         return -ENODEV;
1757
1758         pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
1759
1760         icpu = (const struct idle_cpu *)id->driver_data;
1761         if (icpu) {
1762                 cpuidle_state_table = icpu->state_table;
1763                 auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
1764                 disable_promotion_to_c1e = icpu->disable_promotion_to_c1e;
1765                 if (icpu->use_acpi || force_use_acpi)
1766                         intel_idle_acpi_cst_extract();
1767         } else if (!intel_idle_acpi_cst_extract()) {
1768                 return -ENODEV;
1769         }
1770
1771         pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
1772                  boot_cpu_data.x86_model);
1773
1774         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1775         if (!intel_idle_cpuidle_devices)
1776                 return -ENOMEM;
1777
1778         intel_idle_cpuidle_driver_init(&intel_idle_driver);
1779
1780         retval = cpuidle_register_driver(&intel_idle_driver);
1781         if (retval) {
1782                 struct cpuidle_driver *drv = cpuidle_get_driver();
1783                 printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
1784                        drv ? drv->name : "none");
1785                 goto init_driver_fail;
1786         }
1787
1788         retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
1789                                    intel_idle_cpu_online, NULL);
1790         if (retval < 0)
1791                 goto hp_setup_fail;
1792
1793         pr_debug("Local APIC timer is reliable in %s\n",
1794                  boot_cpu_has(X86_FEATURE_ARAT) ? "all C-states" : "C1");
1795
1796         return 0;
1797
1798 hp_setup_fail:
1799         intel_idle_cpuidle_devices_uninit();
1800         cpuidle_unregister_driver(&intel_idle_driver);
1801 init_driver_fail:
1802         free_percpu(intel_idle_cpuidle_devices);
1803         return retval;
1804
1805 }
1806 device_initcall(intel_idle_init);
1807
1808 /*
1809  * We are not really modular, but we used to support that.  Meaning we also
1810  * support "intel_idle.max_cstate=..." at boot and also a read-only export of
1811  * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
1812  * is the easiest way (currently) to continue doing that.
1813  */
1814 module_param(max_cstate, int, 0444);
1815 /*
1816  * The positions of the bits that are set in this number are the indices of the
1817  * idle states to be disabled by default (as reflected by the names of the
1818  * corresponding idle state directories in sysfs, "state0", "state1" ...
1819  * "state<i>" ..., where <i> is the index of the given state).
1820  */
1821 module_param_named(states_off, disabled_states_mask, uint, 0444);
1822 MODULE_PARM_DESC(states_off, "Mask of disabled idle states");