2 * linux/drivers/ide/pci/hpt366.c Version 1.06 Jun 27, 2007
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
21 * Note that final HPT370 support was done by force extraction of GPL.
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
56 * Alan Cox <alan@redhat.com>
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * does not allow for this speed anyway
65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * their primary channel is kind of virtual, it isn't tied to any pins)
67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
68 * HPT37x chip family; save space by introducing the separate transfer mode
69 * table in which the mode lookup is done
70 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
71 * the wrong PCI frequency since DPLL has already been calibrated by BIOS
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the rate masking/filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * supported DMA mode, and the chip settings table pointer filled, then, at
103 * the init_chipset stage, allocate per-chip instance and fill it with the
104 * rest of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
118 #include <linux/types.h>
119 #include <linux/module.h>
120 #include <linux/kernel.h>
121 #include <linux/delay.h>
122 #include <linux/timer.h>
123 #include <linux/mm.h>
124 #include <linux/ioport.h>
125 #include <linux/blkdev.h>
126 #include <linux/hdreg.h>
128 #include <linux/interrupt.h>
129 #include <linux/pci.h>
130 #include <linux/init.h>
131 #include <linux/ide.h>
133 #include <asm/uaccess.h>
137 /* various tuning parameters */
138 #define HPT_RESET_STATE_ENGINE
139 #undef HPT_DELAY_INTERRUPT
140 #define HPT_SERIALIZE_IO 0
142 static const char *quirk_drives[] = {
143 "QUANTUM FIREBALLlct08 08",
144 "QUANTUM FIREBALLP KA6.4",
145 "QUANTUM FIREBALLP LM20.4",
146 "QUANTUM FIREBALLP LM20.5",
150 static const char *bad_ata100_5[] = {
169 static const char *bad_ata66_4[] = {
185 "MAXTOR STM3320620A",
189 static const char *bad_ata66_3[] = {
194 static const char *bad_ata33[] = {
195 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
196 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
197 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
199 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
200 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
201 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
205 static u8 xfer_speeds[] = {
225 /* Key for bus clock timings
228 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
230 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
232 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
234 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
236 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
237 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
238 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
240 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
241 * task file register access.
244 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
249 static u32 forty_base_hpt36x[] = {
250 /* XFER_UDMA_6 */ 0x900fd943,
251 /* XFER_UDMA_5 */ 0x900fd943,
252 /* XFER_UDMA_4 */ 0x900fd943,
253 /* XFER_UDMA_3 */ 0x900ad943,
254 /* XFER_UDMA_2 */ 0x900bd943,
255 /* XFER_UDMA_1 */ 0x9008d943,
256 /* XFER_UDMA_0 */ 0x9008d943,
258 /* XFER_MW_DMA_2 */ 0xa008d943,
259 /* XFER_MW_DMA_1 */ 0xa010d955,
260 /* XFER_MW_DMA_0 */ 0xa010d9fc,
262 /* XFER_PIO_4 */ 0xc008d963,
263 /* XFER_PIO_3 */ 0xc010d974,
264 /* XFER_PIO_2 */ 0xc010d997,
265 /* XFER_PIO_1 */ 0xc010d9c7,
266 /* XFER_PIO_0 */ 0xc018d9d9
269 static u32 thirty_three_base_hpt36x[] = {
270 /* XFER_UDMA_6 */ 0x90c9a731,
271 /* XFER_UDMA_5 */ 0x90c9a731,
272 /* XFER_UDMA_4 */ 0x90c9a731,
273 /* XFER_UDMA_3 */ 0x90cfa731,
274 /* XFER_UDMA_2 */ 0x90caa731,
275 /* XFER_UDMA_1 */ 0x90cba731,
276 /* XFER_UDMA_0 */ 0x90c8a731,
278 /* XFER_MW_DMA_2 */ 0xa0c8a731,
279 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
280 /* XFER_MW_DMA_0 */ 0xa0c8a797,
282 /* XFER_PIO_4 */ 0xc0c8a731,
283 /* XFER_PIO_3 */ 0xc0c8a742,
284 /* XFER_PIO_2 */ 0xc0d0a753,
285 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
286 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
289 static u32 twenty_five_base_hpt36x[] = {
290 /* XFER_UDMA_6 */ 0x90c98521,
291 /* XFER_UDMA_5 */ 0x90c98521,
292 /* XFER_UDMA_4 */ 0x90c98521,
293 /* XFER_UDMA_3 */ 0x90cf8521,
294 /* XFER_UDMA_2 */ 0x90cf8521,
295 /* XFER_UDMA_1 */ 0x90cb8521,
296 /* XFER_UDMA_0 */ 0x90cb8521,
298 /* XFER_MW_DMA_2 */ 0xa0ca8521,
299 /* XFER_MW_DMA_1 */ 0xa0ca8532,
300 /* XFER_MW_DMA_0 */ 0xa0ca8575,
302 /* XFER_PIO_4 */ 0xc0ca8521,
303 /* XFER_PIO_3 */ 0xc0ca8532,
304 /* XFER_PIO_2 */ 0xc0ca8542,
305 /* XFER_PIO_1 */ 0xc0d08572,
306 /* XFER_PIO_0 */ 0xc0d08585
309 static u32 thirty_three_base_hpt37x[] = {
310 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
311 /* XFER_UDMA_5 */ 0x12446231,
312 /* XFER_UDMA_4 */ 0x12446231,
313 /* XFER_UDMA_3 */ 0x126c6231,
314 /* XFER_UDMA_2 */ 0x12486231,
315 /* XFER_UDMA_1 */ 0x124c6233,
316 /* XFER_UDMA_0 */ 0x12506297,
318 /* XFER_MW_DMA_2 */ 0x22406c31,
319 /* XFER_MW_DMA_1 */ 0x22406c33,
320 /* XFER_MW_DMA_0 */ 0x22406c97,
322 /* XFER_PIO_4 */ 0x06414e31,
323 /* XFER_PIO_3 */ 0x06414e42,
324 /* XFER_PIO_2 */ 0x06414e53,
325 /* XFER_PIO_1 */ 0x06814e93,
326 /* XFER_PIO_0 */ 0x06814ea7
329 static u32 fifty_base_hpt37x[] = {
330 /* XFER_UDMA_6 */ 0x12848242,
331 /* XFER_UDMA_5 */ 0x12848242,
332 /* XFER_UDMA_4 */ 0x12ac8242,
333 /* XFER_UDMA_3 */ 0x128c8242,
334 /* XFER_UDMA_2 */ 0x120c8242,
335 /* XFER_UDMA_1 */ 0x12148254,
336 /* XFER_UDMA_0 */ 0x121882ea,
338 /* XFER_MW_DMA_2 */ 0x22808242,
339 /* XFER_MW_DMA_1 */ 0x22808254,
340 /* XFER_MW_DMA_0 */ 0x228082ea,
342 /* XFER_PIO_4 */ 0x0a81f442,
343 /* XFER_PIO_3 */ 0x0a81f443,
344 /* XFER_PIO_2 */ 0x0a81f454,
345 /* XFER_PIO_1 */ 0x0ac1f465,
346 /* XFER_PIO_0 */ 0x0ac1f48a
349 static u32 sixty_six_base_hpt37x[] = {
350 /* XFER_UDMA_6 */ 0x1c869c62,
351 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
352 /* XFER_UDMA_4 */ 0x1c8a9c62,
353 /* XFER_UDMA_3 */ 0x1c8e9c62,
354 /* XFER_UDMA_2 */ 0x1c929c62,
355 /* XFER_UDMA_1 */ 0x1c9a9c62,
356 /* XFER_UDMA_0 */ 0x1c829c62,
358 /* XFER_MW_DMA_2 */ 0x2c829c62,
359 /* XFER_MW_DMA_1 */ 0x2c829c66,
360 /* XFER_MW_DMA_0 */ 0x2c829d2e,
362 /* XFER_PIO_4 */ 0x0c829c62,
363 /* XFER_PIO_3 */ 0x0c829c84,
364 /* XFER_PIO_2 */ 0x0c829ca6,
365 /* XFER_PIO_1 */ 0x0d029d26,
366 /* XFER_PIO_0 */ 0x0d029d5e
369 #define HPT366_DEBUG_DRIVE_INFO 0
370 #define HPT371_ALLOW_ATA133_6 1
371 #define HPT302_ALLOW_ATA133_6 1
372 #define HPT372_ALLOW_ATA133_6 1
373 #define HPT370_ALLOW_ATA100_5 0
374 #define HPT366_ALLOW_ATA66_4 1
375 #define HPT366_ALLOW_ATA66_3 1
376 #define HPT366_MAX_DEVS 8
378 /* Supported ATA clock frequencies */
389 * Hold all the HighPoint chip information in one place.
393 u8 chip_type; /* Chip type */
394 u8 max_mode; /* Speeds allowed */
395 u8 dpll_clk; /* DPLL clock in MHz */
396 u8 pci_clk; /* PCI clock in MHz */
397 u32 **settings; /* Chipset settings table */
400 /* Supported HighPoint chips */
415 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
416 twenty_five_base_hpt36x,
417 thirty_three_base_hpt36x,
423 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
425 thirty_three_base_hpt37x,
428 sixty_six_base_hpt37x
431 static struct hpt_info hpt36x __devinitdata = {
433 .max_mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1,
434 .dpll_clk = 0, /* no DPLL */
435 .settings = hpt36x_settings
438 static struct hpt_info hpt370 __devinitdata = {
440 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2,
442 .settings = hpt37x_settings
445 static struct hpt_info hpt370a __devinitdata = {
446 .chip_type = HPT370A,
447 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2,
449 .settings = hpt37x_settings
452 static struct hpt_info hpt374 __devinitdata = {
456 .settings = hpt37x_settings
459 static struct hpt_info hpt372 __devinitdata = {
461 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
463 .settings = hpt37x_settings
466 static struct hpt_info hpt372a __devinitdata = {
467 .chip_type = HPT372A,
468 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
470 .settings = hpt37x_settings
473 static struct hpt_info hpt302 __devinitdata = {
475 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3,
477 .settings = hpt37x_settings
480 static struct hpt_info hpt371 __devinitdata = {
482 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3,
484 .settings = hpt37x_settings
487 static struct hpt_info hpt372n __devinitdata = {
488 .chip_type = HPT372N,
489 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
491 .settings = hpt37x_settings
494 static struct hpt_info hpt302n __devinitdata = {
495 .chip_type = HPT302N,
496 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3,
498 .settings = hpt37x_settings
501 static struct hpt_info hpt371n __devinitdata = {
502 .chip_type = HPT371N,
503 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3,
505 .settings = hpt37x_settings
508 static int check_in_drive_list(ide_drive_t *drive, const char **list)
510 struct hd_driveid *id = drive->id;
513 if (!strcmp(*list++,id->model))
519 * Note for the future; the SATA hpt37x we must set
520 * either PIO or UDMA modes 0,4,5
523 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
525 struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev);
526 u8 chip_type = info->chip_type;
527 u8 mode = info->max_mode;
536 if (chip_type >= HPT374)
538 if (!check_in_drive_list(drive, bad_ata100_5))
539 goto check_bad_ata33;
545 * CHECK ME, Does this need to be changed to HPT374 ??
547 if (chip_type >= HPT370)
548 goto check_bad_ata33;
549 if (HPT366_ALLOW_ATA66_4 &&
550 !check_in_drive_list(drive, bad_ata66_4))
551 goto check_bad_ata33;
554 if (HPT366_ALLOW_ATA66_3 &&
555 !check_in_drive_list(drive, bad_ata66_3))
556 goto check_bad_ata33;
562 if (chip_type >= HPT370A)
564 if (!check_in_drive_list(drive, bad_ata33))
575 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
580 * Lookup the transfer mode table to get the index into
583 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
585 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
586 if (xfer_speeds[i] == speed)
589 * NOTE: info->settings only points to the pointer
590 * to the list of the actual register values
592 return (*info->settings)[i];
595 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
597 ide_hwif_t *hwif = HWIF(drive);
598 struct pci_dev *dev = hwif->pci_dev;
599 struct hpt_info *info = pci_get_drvdata(dev);
600 u8 speed = ide_rate_filter(drive, xferspeed);
601 u8 itr_addr = drive->dn ? 0x44 : 0x40;
603 u32 itr_mask, new_itr;
605 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */
606 if (drive->media != ide_disk)
607 speed = min_t(u8, speed, XFER_PIO_4);
609 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
610 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
612 new_itr = get_speed_setting(speed, info);
615 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
616 * to avoid problems handling I/O errors later
618 pci_read_config_dword(dev, itr_addr, &old_itr);
619 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
620 new_itr &= ~0xc0000000;
622 pci_write_config_dword(dev, itr_addr, new_itr);
624 return ide_config_drive_speed(drive, speed);
627 static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
629 ide_hwif_t *hwif = HWIF(drive);
630 struct pci_dev *dev = hwif->pci_dev;
631 struct hpt_info *info = pci_get_drvdata(dev);
632 u8 speed = ide_rate_filter(drive, xferspeed);
633 u8 itr_addr = 0x40 + (drive->dn * 4);
635 u32 itr_mask, new_itr;
637 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */
638 if (drive->media != ide_disk)
639 speed = min_t(u8, speed, XFER_PIO_4);
641 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
642 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
644 new_itr = get_speed_setting(speed, info);
646 pci_read_config_dword(dev, itr_addr, &old_itr);
647 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
649 if (speed < XFER_MW_DMA_0)
650 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
651 pci_write_config_dword(dev, itr_addr, new_itr);
653 return ide_config_drive_speed(drive, speed);
656 static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
658 ide_hwif_t *hwif = HWIF(drive);
659 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
661 if (info->chip_type >= HPT370)
662 return hpt37x_tune_chipset(drive, speed);
663 else /* hpt368: hpt_minimum_revision(dev, 2) */
664 return hpt36x_tune_chipset(drive, speed);
667 static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
669 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
670 (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
673 static int hpt3xx_quirkproc(ide_drive_t *drive)
675 struct hd_driveid *id = drive->id;
676 const char **list = quirk_drives;
679 if (strstr(id->model, *list++))
684 static void hpt3xx_intrproc(ide_drive_t *drive)
686 ide_hwif_t *hwif = HWIF(drive);
688 if (drive->quirk_list)
690 /* drives in the quirk_list may not like intr setups/cleanups */
691 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
694 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
696 ide_hwif_t *hwif = HWIF(drive);
697 struct pci_dev *dev = hwif->pci_dev;
698 struct hpt_info *info = pci_get_drvdata(dev);
700 if (drive->quirk_list) {
701 if (info->chip_type >= HPT370) {
704 pci_read_config_byte(dev, 0x5a, &scr1);
705 if (((scr1 & 0x10) >> 4) != mask) {
710 pci_write_config_byte(dev, 0x5a, scr1);
714 disable_irq(hwif->irq);
716 enable_irq (hwif->irq);
719 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
723 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
725 drive->init_speed = 0;
727 if (ide_tune_dma(drive))
730 if (ide_use_fast_pio(drive))
731 hpt3xx_tune_drive(drive, 255);
737 * This is specific to the HPT366 UDMA chipset
738 * by HighPoint|Triones Technologies, Inc.
740 static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
742 struct pci_dev *dev = HWIF(drive)->pci_dev;
743 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
745 pci_read_config_byte(dev, 0x50, &mcr1);
746 pci_read_config_byte(dev, 0x52, &mcr3);
747 pci_read_config_byte(dev, 0x5a, &scr1);
748 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
749 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
751 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
752 return __ide_dma_lostirq(drive);
755 static void hpt370_clear_engine(ide_drive_t *drive)
757 ide_hwif_t *hwif = HWIF(drive);
759 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
763 static void hpt370_irq_timeout(ide_drive_t *drive)
765 ide_hwif_t *hwif = HWIF(drive);
769 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
770 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
772 /* get DMA command mode */
773 dma_cmd = hwif->INB(hwif->dma_command);
775 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
776 hpt370_clear_engine(drive);
779 static void hpt370_ide_dma_start(ide_drive_t *drive)
781 #ifdef HPT_RESET_STATE_ENGINE
782 hpt370_clear_engine(drive);
784 ide_dma_start(drive);
787 static int hpt370_ide_dma_end(ide_drive_t *drive)
789 ide_hwif_t *hwif = HWIF(drive);
790 u8 dma_stat = hwif->INB(hwif->dma_status);
792 if (dma_stat & 0x01) {
795 dma_stat = hwif->INB(hwif->dma_status);
797 hpt370_irq_timeout(drive);
799 return __ide_dma_end(drive);
802 static int hpt370_ide_dma_timeout(ide_drive_t *drive)
804 hpt370_irq_timeout(drive);
805 return __ide_dma_timeout(drive);
808 /* returns 1 if DMA IRQ issued, 0 otherwise */
809 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
811 ide_hwif_t *hwif = HWIF(drive);
815 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
817 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
821 dma_stat = inb(hwif->dma_status);
822 /* return 1 if INTR asserted */
826 if (!drive->waiting_for_dma)
827 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
828 drive->name, __FUNCTION__);
832 static int hpt374_ide_dma_end(ide_drive_t *drive)
834 ide_hwif_t *hwif = HWIF(drive);
835 struct pci_dev *dev = hwif->pci_dev;
836 u8 mcr = 0, mcr_addr = hwif->select_data;
837 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
839 pci_read_config_byte(dev, 0x6a, &bwsr);
840 pci_read_config_byte(dev, mcr_addr, &mcr);
842 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
843 return __ide_dma_end(drive);
847 * hpt3xxn_set_clock - perform clock switching dance
848 * @hwif: hwif to switch
849 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
851 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
854 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
856 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
858 if ((scr2 & 0x7f) == mode)
861 /* Tristate the bus */
862 hwif->OUTB(0x80, hwif->dma_master + 0x73);
863 hwif->OUTB(0x80, hwif->dma_master + 0x77);
865 /* Switch clock and reset channels */
866 hwif->OUTB(mode, hwif->dma_master + 0x7b);
867 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
870 * Reset the state machines.
871 * NOTE: avoid accidentally enabling the disabled channels.
873 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
874 hwif->dma_master + 0x70);
875 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
876 hwif->dma_master + 0x74);
879 hwif->OUTB(0x00, hwif->dma_master + 0x79);
881 /* Reconnect channels to bus */
882 hwif->OUTB(0x00, hwif->dma_master + 0x73);
883 hwif->OUTB(0x00, hwif->dma_master + 0x77);
887 * hpt3xxn_rw_disk - prepare for I/O
888 * @drive: drive for command
889 * @rq: block request structure
891 * This is called when a disk I/O is issued to HPT3xxN.
892 * We need it because of the clock switching.
895 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
897 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
901 * Set/get power state for a drive.
902 * NOTE: affects both drives on each channel.
904 * When we turn the power back on, we need to re-initialize things.
906 #define TRISTATE_BIT 0x8000
908 static int hpt3xx_busproc(ide_drive_t *drive, int state)
910 ide_hwif_t *hwif = HWIF(drive);
911 struct pci_dev *dev = hwif->pci_dev;
912 u8 mcr_addr = hwif->select_data + 2;
913 u8 resetmask = hwif->channel ? 0x80 : 0x40;
917 hwif->bus_state = state;
919 /* Grab the status. */
920 pci_read_config_word(dev, mcr_addr, &mcr);
921 pci_read_config_byte(dev, 0x59, &bsr2);
924 * Set the state. We don't set it if we don't need to do so.
925 * Make sure that the drive knows that it has failed if it's off.
929 if (!(bsr2 & resetmask))
931 hwif->drives[0].failures = hwif->drives[1].failures = 0;
933 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
934 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
937 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
939 mcr &= ~TRISTATE_BIT;
941 case BUSSTATE_TRISTATE:
942 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
950 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
951 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
953 pci_write_config_word(dev, mcr_addr, mcr);
954 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
959 * hpt37x_calibrate_dpll - calibrate the DPLL
962 * Perform a calibration cycle on the DPLL.
963 * Returns 1 if this succeeds
965 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
967 u32 dpll = (f_high << 16) | f_low | 0x100;
971 pci_write_config_dword(dev, 0x5c, dpll);
973 /* Wait for oscillator ready */
974 for(i = 0; i < 0x5000; ++i) {
976 pci_read_config_byte(dev, 0x5b, &scr2);
980 /* See if it stays ready (we'll just bail out if it's not yet) */
981 for(i = 0; i < 0x1000; ++i) {
982 pci_read_config_byte(dev, 0x5b, &scr2);
983 /* DPLL destabilized? */
987 /* Turn off tuning, we have the DPLL set */
988 pci_read_config_dword (dev, 0x5c, &dpll);
989 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
993 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
995 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
996 unsigned long io_base = pci_resource_start(dev, 4);
997 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
998 enum ata_clock clock;
1001 printk(KERN_ERR "%s: out of memory!\n", name);
1006 * Copy everything from a static "template" structure
1007 * to just allocated per-chip hpt_info structure.
1009 *info = *(struct hpt_info *)pci_get_drvdata(dev);
1012 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1013 * We don't seem to be using it.
1015 if (dev->resource[PCI_ROM_RESOURCE].start)
1016 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1017 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1019 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1020 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1021 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1022 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1025 * First, try to estimate the PCI clock frequency...
1027 if (info->chip_type >= HPT370) {
1032 /* Interrupt force enable. */
1033 pci_read_config_byte(dev, 0x5a, &scr1);
1035 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1038 * HighPoint does this for HPT372A.
1039 * NOTE: This register is only writeable via I/O space.
1041 if (info->chip_type == HPT372A)
1042 outb(0x0e, io_base + 0x9c);
1045 * Default to PCI clock. Make sure MA15/16 are set to output
1046 * to prevent drives having problems with 40-pin cables.
1048 pci_write_config_byte(dev, 0x5b, 0x23);
1051 * We'll have to read f_CNT value in order to determine
1052 * the PCI clock frequency according to the following ratio:
1054 * f_CNT = Fpci * 192 / Fdpll
1056 * First try reading the register in which the HighPoint BIOS
1057 * saves f_CNT value before reprogramming the DPLL from its
1058 * default setting (which differs for the various chips).
1059 * NOTE: This register is only accessible via I/O space.
1061 * In case the signature check fails, we'll have to resort to
1062 * reading the f_CNT register itself in hopes that nobody has
1063 * touched the DPLL yet...
1065 temp = inl(io_base + 0x90);
1066 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1069 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1072 /* Calculate the average value of f_CNT. */
1073 for (temp = i = 0; i < 128; i++) {
1074 pci_read_config_word(dev, 0x78, &f_cnt);
1075 temp += f_cnt & 0x1ff;
1080 f_cnt = temp & 0x1ff;
1082 dpll_clk = info->dpll_clk;
1083 pci_clk = (f_cnt * dpll_clk) / 192;
1085 /* Clamp PCI clock to bands. */
1088 else if(pci_clk < 45)
1090 else if(pci_clk < 55)
1095 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1096 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1100 pci_read_config_dword(dev, 0x40, &itr1);
1102 /* Detect PCI clock by looking at cmd_high_time. */
1103 switch((itr1 >> 8) & 0x07) {
1117 /* Let's assume we'll use PCI clock for the ATA clock... */
1120 clock = ATA_CLOCK_25MHZ;
1124 clock = ATA_CLOCK_33MHZ;
1127 clock = ATA_CLOCK_40MHZ;
1130 clock = ATA_CLOCK_50MHZ;
1133 clock = ATA_CLOCK_66MHZ;
1138 * Only try the DPLL if we don't have a table for the PCI clock that
1139 * we are running at for HPT370/A, always use it for anything newer...
1141 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1142 * We also don't like using the DPLL because this causes glitches
1143 * on PRST-/SRST- when the state engine gets reset...
1145 if (info->chip_type >= HPT374 || info->settings[clock] == NULL) {
1146 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1150 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1151 * supported/enabled, use 50 MHz DPLL clock otherwise...
1153 if (info->max_mode == 0x04) {
1155 clock = ATA_CLOCK_66MHZ;
1156 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1158 clock = ATA_CLOCK_50MHZ;
1161 if (info->settings[clock] == NULL) {
1162 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1167 /* Select the DPLL clock. */
1168 pci_write_config_byte(dev, 0x5b, 0x21);
1171 * Adjust the DPLL based upon PCI clock, enable it,
1172 * and wait for stabilization...
1174 f_low = (pci_clk * 48) / dpll_clk;
1176 for (adjust = 0; adjust < 8; adjust++) {
1177 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1181 * See if it'll settle at a fractionally different clock
1184 f_low -= adjust >> 1;
1186 f_low += adjust >> 1;
1189 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1194 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1196 /* Mark the fact that we're not using the DPLL. */
1199 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1203 * Advance the table pointer to a slot which points to the list
1204 * of the register values settings matching the clock being used.
1206 info->settings += clock;
1208 /* Store the clock frequencies. */
1209 info->dpll_clk = dpll_clk;
1210 info->pci_clk = pci_clk;
1212 /* Point to this chip's own instance of the hpt_info structure. */
1213 pci_set_drvdata(dev, info);
1215 if (info->chip_type >= HPT370) {
1219 * Reset the state engines.
1220 * NOTE: Avoid accidentally enabling the disabled channels.
1222 pci_read_config_byte (dev, 0x50, &mcr1);
1223 pci_read_config_byte (dev, 0x54, &mcr4);
1224 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1225 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1230 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1231 * the MISC. register to stretch the UltraDMA Tss timing.
1232 * NOTE: This register is only writeable via I/O space.
1234 if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1236 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1241 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1243 struct pci_dev *dev = hwif->pci_dev;
1244 struct hpt_info *info = pci_get_drvdata(dev);
1245 int serialize = HPT_SERIALIZE_IO;
1246 u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02;
1247 u8 chip_type = info->chip_type;
1248 u8 new_mcr, old_mcr = 0;
1250 /* Cache the channel's MISC. control registers' offset */
1251 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1253 hwif->tuneproc = &hpt3xx_tune_drive;
1254 hwif->speedproc = &hpt3xx_tune_chipset;
1255 hwif->quirkproc = &hpt3xx_quirkproc;
1256 hwif->intrproc = &hpt3xx_intrproc;
1257 hwif->maskproc = &hpt3xx_maskproc;
1258 hwif->busproc = &hpt3xx_busproc;
1259 hwif->udma_filter = &hpt3xx_udma_filter;
1262 * HPT3xxN chips have some complications:
1264 * - on 33 MHz PCI we must clock switch
1265 * - on 66 MHz PCI we must NOT use the PCI clock
1267 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1269 * Clock is shared between the channels,
1270 * so we'll have to serialize them... :-(
1273 hwif->rw_disk = &hpt3xxn_rw_disk;
1276 /* Serialize access to this device if needed */
1277 if (serialize && hwif->mate)
1278 hwif->serialized = hwif->mate->serialized = 1;
1281 * Disable the "fast interrupt" prediction. Don't hold off
1282 * on interrupts. (== 0x01 despite what the docs say)
1284 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1286 if (info->chip_type >= HPT374)
1287 new_mcr = old_mcr & ~0x07;
1288 else if (info->chip_type >= HPT370) {
1292 #ifdef HPT_DELAY_INTERRUPT
1297 } else /* HPT366 and HPT368 */
1298 new_mcr = old_mcr & ~0x80;
1300 if (new_mcr != old_mcr)
1301 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1303 if (!hwif->dma_base) {
1304 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1308 hwif->ultra_mask = 0x7f;
1309 hwif->mwdma_mask = 0x07;
1312 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1313 * address lines to access an external EEPROM. To read valid
1314 * cable detect state the pins must be enabled as inputs.
1316 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1318 * HPT374 PCI function 1
1319 * - set bit 15 of reg 0x52 to enable TCBLID as input
1320 * - set bit 15 of reg 0x56 to enable FCBLID as input
1322 u8 mcr_addr = hwif->select_data + 2;
1325 pci_read_config_word (dev, mcr_addr, &mcr);
1326 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1327 /* now read cable id register */
1328 pci_read_config_byte (dev, 0x5a, &scr1);
1329 pci_write_config_word(dev, mcr_addr, mcr);
1330 } else if (chip_type >= HPT370) {
1332 * HPT370/372 and 374 pcifn 0
1333 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1337 pci_read_config_byte (dev, 0x5b, &scr2);
1338 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1339 /* now read cable id register */
1340 pci_read_config_byte (dev, 0x5a, &scr1);
1341 pci_write_config_byte(dev, 0x5b, scr2);
1343 pci_read_config_byte (dev, 0x5a, &scr1);
1345 if (!hwif->udma_four)
1346 hwif->udma_four = (scr1 & ata66) ? 0 : 1;
1348 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1350 if (chip_type >= HPT374) {
1351 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1352 hwif->ide_dma_end = &hpt374_ide_dma_end;
1353 } else if (chip_type >= HPT370) {
1354 hwif->dma_start = &hpt370_ide_dma_start;
1355 hwif->ide_dma_end = &hpt370_ide_dma_end;
1356 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1358 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1362 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1365 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1367 struct pci_dev *dev = hwif->pci_dev;
1368 u8 masterdma = 0, slavedma = 0;
1369 u8 dma_new = 0, dma_old = 0;
1370 unsigned long flags;
1372 dma_old = hwif->INB(dmabase + 2);
1374 local_irq_save(flags);
1377 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1378 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1380 if (masterdma & 0x30) dma_new |= 0x20;
1381 if ( slavedma & 0x30) dma_new |= 0x40;
1382 if (dma_new != dma_old)
1383 hwif->OUTB(dma_new, dmabase + 2);
1385 local_irq_restore(flags);
1387 ide_setup_dma(hwif, dmabase, 8);
1390 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1392 struct pci_dev *dev2;
1394 if (PCI_FUNC(dev->devfn) & 1)
1397 pci_set_drvdata(dev, &hpt374);
1399 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1402 pci_set_drvdata(dev2, &hpt374);
1404 if (dev2->irq != dev->irq) {
1405 /* FIXME: we need a core pci_set_interrupt() */
1406 dev2->irq = dev->irq;
1407 printk(KERN_WARNING "%s: PCI config space interrupt "
1408 "fixed.\n", d->name);
1410 ret = ide_setup_pci_devices(dev, dev2, d);
1415 return ide_setup_pci_device(dev, d);
1418 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1420 pci_set_drvdata(dev, &hpt372n);
1422 return ide_setup_pci_device(dev, d);
1425 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1427 struct hpt_info *info;
1428 u8 rev = 0, mcr1 = 0;
1430 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1433 d->name = "HPT371N";
1440 * HPT371 chips physically have only one channel, the secondary one,
1441 * but the primary channel registers do exist! Go figure...
1442 * So, we manually disable the non-existing channel here
1443 * (if the BIOS hasn't done this already).
1445 pci_read_config_byte(dev, 0x50, &mcr1);
1447 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1449 pci_set_drvdata(dev, info);
1451 return ide_setup_pci_device(dev, d);
1454 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1456 struct hpt_info *info;
1459 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1462 d->name = "HPT372N";
1467 pci_set_drvdata(dev, info);
1469 return ide_setup_pci_device(dev, d);
1472 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1474 struct hpt_info *info;
1477 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1480 d->name = "HPT302N";
1485 pci_set_drvdata(dev, info);
1487 return ide_setup_pci_device(dev, d);
1490 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1492 struct pci_dev *dev2;
1494 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1495 "HPT370", "HPT370A", "HPT372",
1497 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1498 &hpt370, &hpt370a, &hpt372,
1501 if (PCI_FUNC(dev->devfn) & 1)
1504 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1509 d->name = chipset_names[rev];
1511 pci_set_drvdata(dev, info[rev]);
1517 * HPT36x chips have one channel per function and have
1518 * both channel enable bits located differently and visible
1519 * to both functions -- really stupid design decision... :-(
1520 * Bit 4 is for the primary channel, bit 5 for the secondary.
1523 d->enablebits[0].mask = d->enablebits[0].val = 0x10;
1525 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1526 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1529 pci_set_drvdata(dev2, info[rev]);
1532 * Now we'll have to force both channels enabled if
1533 * at least one of them has been enabled by BIOS...
1535 pci_read_config_byte(dev, 0x50, &mcr1);
1537 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1539 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1540 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1541 if (pin1 != pin2 && dev->irq == dev2->irq) {
1542 d->bootable = ON_BOARD;
1543 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1544 d->name, pin1, pin2);
1546 ret = ide_setup_pci_devices(dev, dev2, d);
1552 return ide_setup_pci_device(dev, d);
1555 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1558 .init_setup = init_setup_hpt366,
1559 .init_chipset = init_chipset_hpt366,
1560 .init_hwif = init_hwif_hpt366,
1561 .init_dma = init_dma_hpt366,
1564 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1565 .bootable = OFF_BOARD,
1569 .init_setup = init_setup_hpt372a,
1570 .init_chipset = init_chipset_hpt366,
1571 .init_hwif = init_hwif_hpt366,
1572 .init_dma = init_dma_hpt366,
1575 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1576 .bootable = OFF_BOARD,
1580 .init_setup = init_setup_hpt302,
1581 .init_chipset = init_chipset_hpt366,
1582 .init_hwif = init_hwif_hpt366,
1583 .init_dma = init_dma_hpt366,
1586 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1587 .bootable = OFF_BOARD,
1591 .init_setup = init_setup_hpt371,
1592 .init_chipset = init_chipset_hpt366,
1593 .init_hwif = init_hwif_hpt366,
1594 .init_dma = init_dma_hpt366,
1597 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1598 .bootable = OFF_BOARD,
1602 .init_setup = init_setup_hpt374,
1603 .init_chipset = init_chipset_hpt366,
1604 .init_hwif = init_hwif_hpt366,
1605 .init_dma = init_dma_hpt366,
1606 .channels = 2, /* 4 */
1608 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1609 .bootable = OFF_BOARD,
1613 .init_setup = init_setup_hpt372n,
1614 .init_chipset = init_chipset_hpt366,
1615 .init_hwif = init_hwif_hpt366,
1616 .init_dma = init_dma_hpt366,
1617 .channels = 2, /* 4 */
1619 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1620 .bootable = OFF_BOARD,
1626 * hpt366_init_one - called when an HPT366 is found
1627 * @dev: the hpt366 device
1628 * @id: the matching pci id
1630 * Called when the PCI registration layer (or the IDE initialization)
1631 * finds a device matching our IDE device tables.
1633 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1634 * structure depending on the chip's revision, we'd better pass a local
1635 * copy down the call chain...
1637 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1639 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1641 return d.init_setup(dev, &d);
1644 static struct pci_device_id hpt366_pci_tbl[] = {
1645 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1646 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1647 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1648 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1649 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1650 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1653 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1655 static struct pci_driver driver = {
1656 .name = "HPT366_IDE",
1657 .id_table = hpt366_pci_tbl,
1658 .probe = hpt366_init_one,
1661 static int __init hpt366_ide_init(void)
1663 return ide_pci_register_driver(&driver);
1666 module_init(hpt366_ide_init);
1668 MODULE_AUTHOR("Andre Hedrick");
1669 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1670 MODULE_LICENSE("GPL");