2 * linux/drivers/ide/pci/hpt366.c Version 1.10 Jun 29, 2007
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
21 * Note that final HPT370 support was done by force extraction of GPL.
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
56 * Alan Cox <alan@redhat.com>
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * does not allow for this speed anyway
65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * their primary channel is kind of virtual, it isn't tied to any pins)
67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
68 * HPT37x chip family; save space by introducing the separate transfer mode
69 * table in which the mode lookup is done
70 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
71 * the wrong PCI frequency since DPLL has already been calibrated by BIOS
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the UltraDMA filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * - set the correct hwif->ultra_mask for each individual chip
116 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
119 #include <linux/types.h>
120 #include <linux/module.h>
121 #include <linux/kernel.h>
122 #include <linux/delay.h>
123 #include <linux/timer.h>
124 #include <linux/mm.h>
125 #include <linux/ioport.h>
126 #include <linux/blkdev.h>
127 #include <linux/hdreg.h>
129 #include <linux/interrupt.h>
130 #include <linux/pci.h>
131 #include <linux/init.h>
132 #include <linux/ide.h>
134 #include <asm/uaccess.h>
138 /* various tuning parameters */
139 #define HPT_RESET_STATE_ENGINE
140 #undef HPT_DELAY_INTERRUPT
141 #define HPT_SERIALIZE_IO 0
143 static const char *quirk_drives[] = {
144 "QUANTUM FIREBALLlct08 08",
145 "QUANTUM FIREBALLP KA6.4",
146 "QUANTUM FIREBALLP LM20.4",
147 "QUANTUM FIREBALLP LM20.5",
151 static const char *bad_ata100_5[] = {
170 static const char *bad_ata66_4[] = {
186 "MAXTOR STM3320620A",
190 static const char *bad_ata66_3[] = {
195 static const char *bad_ata33[] = {
196 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
197 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
198 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
200 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
201 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
202 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
206 static u8 xfer_speeds[] = {
226 /* Key for bus clock timings
229 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
231 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
233 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
235 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
237 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
238 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
239 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
241 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
242 * task file register access.
245 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
250 static u32 forty_base_hpt36x[] = {
251 /* XFER_UDMA_6 */ 0x900fd943,
252 /* XFER_UDMA_5 */ 0x900fd943,
253 /* XFER_UDMA_4 */ 0x900fd943,
254 /* XFER_UDMA_3 */ 0x900ad943,
255 /* XFER_UDMA_2 */ 0x900bd943,
256 /* XFER_UDMA_1 */ 0x9008d943,
257 /* XFER_UDMA_0 */ 0x9008d943,
259 /* XFER_MW_DMA_2 */ 0xa008d943,
260 /* XFER_MW_DMA_1 */ 0xa010d955,
261 /* XFER_MW_DMA_0 */ 0xa010d9fc,
263 /* XFER_PIO_4 */ 0xc008d963,
264 /* XFER_PIO_3 */ 0xc010d974,
265 /* XFER_PIO_2 */ 0xc010d997,
266 /* XFER_PIO_1 */ 0xc010d9c7,
267 /* XFER_PIO_0 */ 0xc018d9d9
270 static u32 thirty_three_base_hpt36x[] = {
271 /* XFER_UDMA_6 */ 0x90c9a731,
272 /* XFER_UDMA_5 */ 0x90c9a731,
273 /* XFER_UDMA_4 */ 0x90c9a731,
274 /* XFER_UDMA_3 */ 0x90cfa731,
275 /* XFER_UDMA_2 */ 0x90caa731,
276 /* XFER_UDMA_1 */ 0x90cba731,
277 /* XFER_UDMA_0 */ 0x90c8a731,
279 /* XFER_MW_DMA_2 */ 0xa0c8a731,
280 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
281 /* XFER_MW_DMA_0 */ 0xa0c8a797,
283 /* XFER_PIO_4 */ 0xc0c8a731,
284 /* XFER_PIO_3 */ 0xc0c8a742,
285 /* XFER_PIO_2 */ 0xc0d0a753,
286 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
287 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
290 static u32 twenty_five_base_hpt36x[] = {
291 /* XFER_UDMA_6 */ 0x90c98521,
292 /* XFER_UDMA_5 */ 0x90c98521,
293 /* XFER_UDMA_4 */ 0x90c98521,
294 /* XFER_UDMA_3 */ 0x90cf8521,
295 /* XFER_UDMA_2 */ 0x90cf8521,
296 /* XFER_UDMA_1 */ 0x90cb8521,
297 /* XFER_UDMA_0 */ 0x90cb8521,
299 /* XFER_MW_DMA_2 */ 0xa0ca8521,
300 /* XFER_MW_DMA_1 */ 0xa0ca8532,
301 /* XFER_MW_DMA_0 */ 0xa0ca8575,
303 /* XFER_PIO_4 */ 0xc0ca8521,
304 /* XFER_PIO_3 */ 0xc0ca8532,
305 /* XFER_PIO_2 */ 0xc0ca8542,
306 /* XFER_PIO_1 */ 0xc0d08572,
307 /* XFER_PIO_0 */ 0xc0d08585
310 static u32 thirty_three_base_hpt37x[] = {
311 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
312 /* XFER_UDMA_5 */ 0x12446231,
313 /* XFER_UDMA_4 */ 0x12446231,
314 /* XFER_UDMA_3 */ 0x126c6231,
315 /* XFER_UDMA_2 */ 0x12486231,
316 /* XFER_UDMA_1 */ 0x124c6233,
317 /* XFER_UDMA_0 */ 0x12506297,
319 /* XFER_MW_DMA_2 */ 0x22406c31,
320 /* XFER_MW_DMA_1 */ 0x22406c33,
321 /* XFER_MW_DMA_0 */ 0x22406c97,
323 /* XFER_PIO_4 */ 0x06414e31,
324 /* XFER_PIO_3 */ 0x06414e42,
325 /* XFER_PIO_2 */ 0x06414e53,
326 /* XFER_PIO_1 */ 0x06814e93,
327 /* XFER_PIO_0 */ 0x06814ea7
330 static u32 fifty_base_hpt37x[] = {
331 /* XFER_UDMA_6 */ 0x12848242,
332 /* XFER_UDMA_5 */ 0x12848242,
333 /* XFER_UDMA_4 */ 0x12ac8242,
334 /* XFER_UDMA_3 */ 0x128c8242,
335 /* XFER_UDMA_2 */ 0x120c8242,
336 /* XFER_UDMA_1 */ 0x12148254,
337 /* XFER_UDMA_0 */ 0x121882ea,
339 /* XFER_MW_DMA_2 */ 0x22808242,
340 /* XFER_MW_DMA_1 */ 0x22808254,
341 /* XFER_MW_DMA_0 */ 0x228082ea,
343 /* XFER_PIO_4 */ 0x0a81f442,
344 /* XFER_PIO_3 */ 0x0a81f443,
345 /* XFER_PIO_2 */ 0x0a81f454,
346 /* XFER_PIO_1 */ 0x0ac1f465,
347 /* XFER_PIO_0 */ 0x0ac1f48a
350 static u32 sixty_six_base_hpt37x[] = {
351 /* XFER_UDMA_6 */ 0x1c869c62,
352 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
353 /* XFER_UDMA_4 */ 0x1c8a9c62,
354 /* XFER_UDMA_3 */ 0x1c8e9c62,
355 /* XFER_UDMA_2 */ 0x1c929c62,
356 /* XFER_UDMA_1 */ 0x1c9a9c62,
357 /* XFER_UDMA_0 */ 0x1c829c62,
359 /* XFER_MW_DMA_2 */ 0x2c829c62,
360 /* XFER_MW_DMA_1 */ 0x2c829c66,
361 /* XFER_MW_DMA_0 */ 0x2c829d2e,
363 /* XFER_PIO_4 */ 0x0c829c62,
364 /* XFER_PIO_3 */ 0x0c829c84,
365 /* XFER_PIO_2 */ 0x0c829ca6,
366 /* XFER_PIO_1 */ 0x0d029d26,
367 /* XFER_PIO_0 */ 0x0d029d5e
370 #define HPT366_DEBUG_DRIVE_INFO 0
371 #define HPT371_ALLOW_ATA133_6 1
372 #define HPT302_ALLOW_ATA133_6 1
373 #define HPT372_ALLOW_ATA133_6 1
374 #define HPT370_ALLOW_ATA100_5 0
375 #define HPT366_ALLOW_ATA66_4 1
376 #define HPT366_ALLOW_ATA66_3 1
377 #define HPT366_MAX_DEVS 8
379 /* Supported ATA clock frequencies */
390 * Hold all the HighPoint chip information in one place.
394 u8 chip_type; /* Chip type */
395 u8 max_ultra; /* Max. UltraDMA mode allowed */
396 u8 dpll_clk; /* DPLL clock in MHz */
397 u8 pci_clk; /* PCI clock in MHz */
398 u32 **settings; /* Chipset settings table */
401 /* Supported HighPoint chips */
416 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
417 twenty_five_base_hpt36x,
418 thirty_three_base_hpt36x,
424 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
426 thirty_three_base_hpt37x,
429 sixty_six_base_hpt37x
432 static struct hpt_info hpt36x __devinitdata = {
434 .max_ultra = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? 4 : 3) : 2,
435 .dpll_clk = 0, /* no DPLL */
436 .settings = hpt36x_settings
439 static struct hpt_info hpt370 __devinitdata = {
441 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
443 .settings = hpt37x_settings
446 static struct hpt_info hpt370a __devinitdata = {
447 .chip_type = HPT370A,
448 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
450 .settings = hpt37x_settings
453 static struct hpt_info hpt374 __devinitdata = {
457 .settings = hpt37x_settings
460 static struct hpt_info hpt372 __devinitdata = {
462 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
464 .settings = hpt37x_settings
467 static struct hpt_info hpt372a __devinitdata = {
468 .chip_type = HPT372A,
469 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
471 .settings = hpt37x_settings
474 static struct hpt_info hpt302 __devinitdata = {
476 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
478 .settings = hpt37x_settings
481 static struct hpt_info hpt371 __devinitdata = {
483 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
485 .settings = hpt37x_settings
488 static struct hpt_info hpt372n __devinitdata = {
489 .chip_type = HPT372N,
490 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
492 .settings = hpt37x_settings
495 static struct hpt_info hpt302n __devinitdata = {
496 .chip_type = HPT302N,
497 .max_ultra = HPT302_ALLOW_ATA133_6 ? 6 : 5,
499 .settings = hpt37x_settings
502 static struct hpt_info hpt371n __devinitdata = {
503 .chip_type = HPT371N,
504 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
506 .settings = hpt37x_settings
509 static int check_in_drive_list(ide_drive_t *drive, const char **list)
511 struct hd_driveid *id = drive->id;
514 if (!strcmp(*list++,id->model))
520 * Note for the future; the SATA hpt37x we must set
521 * either PIO or UDMA modes 0,4,5
524 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
526 struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev);
529 switch (info->chip_type) {
531 if (!HPT370_ALLOW_ATA100_5 ||
532 check_in_drive_list(drive, bad_ata100_5))
537 if (!HPT370_ALLOW_ATA100_5 ||
538 check_in_drive_list(drive, bad_ata100_5))
544 if (!HPT366_ALLOW_ATA66_4 ||
545 check_in_drive_list(drive, bad_ata66_4))
550 if (!HPT366_ALLOW_ATA66_3 ||
551 check_in_drive_list(drive, bad_ata66_3))
558 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
561 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
566 * Lookup the transfer mode table to get the index into
569 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
571 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
572 if (xfer_speeds[i] == speed)
575 * NOTE: info->settings only points to the pointer
576 * to the list of the actual register values
578 return (*info->settings)[i];
581 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
583 ide_hwif_t *hwif = HWIF(drive);
584 struct pci_dev *dev = hwif->pci_dev;
585 struct hpt_info *info = pci_get_drvdata(dev);
586 u8 speed = ide_rate_filter(drive, xferspeed);
587 u8 itr_addr = drive->dn ? 0x44 : 0x40;
589 u32 itr_mask, new_itr;
591 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */
592 if (drive->media != ide_disk)
593 speed = min_t(u8, speed, XFER_PIO_4);
595 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
596 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
598 new_itr = get_speed_setting(speed, info);
601 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
602 * to avoid problems handling I/O errors later
604 pci_read_config_dword(dev, itr_addr, &old_itr);
605 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
606 new_itr &= ~0xc0000000;
608 pci_write_config_dword(dev, itr_addr, new_itr);
610 return ide_config_drive_speed(drive, speed);
613 static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
615 ide_hwif_t *hwif = HWIF(drive);
616 struct pci_dev *dev = hwif->pci_dev;
617 struct hpt_info *info = pci_get_drvdata(dev);
618 u8 speed = ide_rate_filter(drive, xferspeed);
619 u8 itr_addr = 0x40 + (drive->dn * 4);
621 u32 itr_mask, new_itr;
623 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */
624 if (drive->media != ide_disk)
625 speed = min_t(u8, speed, XFER_PIO_4);
627 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
628 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
630 new_itr = get_speed_setting(speed, info);
632 pci_read_config_dword(dev, itr_addr, &old_itr);
633 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
635 if (speed < XFER_MW_DMA_0)
636 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
637 pci_write_config_dword(dev, itr_addr, new_itr);
639 return ide_config_drive_speed(drive, speed);
642 static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
644 ide_hwif_t *hwif = HWIF(drive);
645 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
647 if (info->chip_type >= HPT370)
648 return hpt37x_tune_chipset(drive, speed);
649 else /* hpt368: hpt_minimum_revision(dev, 2) */
650 return hpt36x_tune_chipset(drive, speed);
653 static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
655 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
656 (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
659 static int hpt3xx_quirkproc(ide_drive_t *drive)
661 struct hd_driveid *id = drive->id;
662 const char **list = quirk_drives;
665 if (strstr(id->model, *list++))
670 static void hpt3xx_intrproc(ide_drive_t *drive)
672 ide_hwif_t *hwif = HWIF(drive);
674 if (drive->quirk_list)
676 /* drives in the quirk_list may not like intr setups/cleanups */
677 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
680 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
682 ide_hwif_t *hwif = HWIF(drive);
683 struct pci_dev *dev = hwif->pci_dev;
684 struct hpt_info *info = pci_get_drvdata(dev);
686 if (drive->quirk_list) {
687 if (info->chip_type >= HPT370) {
690 pci_read_config_byte(dev, 0x5a, &scr1);
691 if (((scr1 & 0x10) >> 4) != mask) {
696 pci_write_config_byte(dev, 0x5a, scr1);
700 disable_irq(hwif->irq);
702 enable_irq (hwif->irq);
705 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
709 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
711 drive->init_speed = 0;
713 if (ide_tune_dma(drive))
716 if (ide_use_fast_pio(drive))
717 hpt3xx_tune_drive(drive, 255);
723 * This is specific to the HPT366 UDMA chipset
724 * by HighPoint|Triones Technologies, Inc.
726 static void hpt366_dma_lost_irq(ide_drive_t *drive)
728 struct pci_dev *dev = HWIF(drive)->pci_dev;
729 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
731 pci_read_config_byte(dev, 0x50, &mcr1);
732 pci_read_config_byte(dev, 0x52, &mcr3);
733 pci_read_config_byte(dev, 0x5a, &scr1);
734 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
735 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
737 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
738 ide_dma_lost_irq(drive);
741 static void hpt370_clear_engine(ide_drive_t *drive)
743 ide_hwif_t *hwif = HWIF(drive);
745 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
749 static void hpt370_irq_timeout(ide_drive_t *drive)
751 ide_hwif_t *hwif = HWIF(drive);
755 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
756 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
758 /* get DMA command mode */
759 dma_cmd = hwif->INB(hwif->dma_command);
761 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
762 hpt370_clear_engine(drive);
765 static void hpt370_ide_dma_start(ide_drive_t *drive)
767 #ifdef HPT_RESET_STATE_ENGINE
768 hpt370_clear_engine(drive);
770 ide_dma_start(drive);
773 static int hpt370_ide_dma_end(ide_drive_t *drive)
775 ide_hwif_t *hwif = HWIF(drive);
776 u8 dma_stat = hwif->INB(hwif->dma_status);
778 if (dma_stat & 0x01) {
781 dma_stat = hwif->INB(hwif->dma_status);
783 hpt370_irq_timeout(drive);
785 return __ide_dma_end(drive);
788 static void hpt370_dma_timeout(ide_drive_t *drive)
790 hpt370_irq_timeout(drive);
791 ide_dma_timeout(drive);
794 /* returns 1 if DMA IRQ issued, 0 otherwise */
795 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
797 ide_hwif_t *hwif = HWIF(drive);
801 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
803 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
807 dma_stat = inb(hwif->dma_status);
808 /* return 1 if INTR asserted */
812 if (!drive->waiting_for_dma)
813 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
814 drive->name, __FUNCTION__);
818 static int hpt374_ide_dma_end(ide_drive_t *drive)
820 ide_hwif_t *hwif = HWIF(drive);
821 struct pci_dev *dev = hwif->pci_dev;
822 u8 mcr = 0, mcr_addr = hwif->select_data;
823 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
825 pci_read_config_byte(dev, 0x6a, &bwsr);
826 pci_read_config_byte(dev, mcr_addr, &mcr);
828 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
829 return __ide_dma_end(drive);
833 * hpt3xxn_set_clock - perform clock switching dance
834 * @hwif: hwif to switch
835 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
837 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
840 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
842 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
844 if ((scr2 & 0x7f) == mode)
847 /* Tristate the bus */
848 hwif->OUTB(0x80, hwif->dma_master + 0x73);
849 hwif->OUTB(0x80, hwif->dma_master + 0x77);
851 /* Switch clock and reset channels */
852 hwif->OUTB(mode, hwif->dma_master + 0x7b);
853 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
856 * Reset the state machines.
857 * NOTE: avoid accidentally enabling the disabled channels.
859 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
860 hwif->dma_master + 0x70);
861 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
862 hwif->dma_master + 0x74);
865 hwif->OUTB(0x00, hwif->dma_master + 0x79);
867 /* Reconnect channels to bus */
868 hwif->OUTB(0x00, hwif->dma_master + 0x73);
869 hwif->OUTB(0x00, hwif->dma_master + 0x77);
873 * hpt3xxn_rw_disk - prepare for I/O
874 * @drive: drive for command
875 * @rq: block request structure
877 * This is called when a disk I/O is issued to HPT3xxN.
878 * We need it because of the clock switching.
881 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
883 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
887 * Set/get power state for a drive.
888 * NOTE: affects both drives on each channel.
890 * When we turn the power back on, we need to re-initialize things.
892 #define TRISTATE_BIT 0x8000
894 static int hpt3xx_busproc(ide_drive_t *drive, int state)
896 ide_hwif_t *hwif = HWIF(drive);
897 struct pci_dev *dev = hwif->pci_dev;
898 u8 mcr_addr = hwif->select_data + 2;
899 u8 resetmask = hwif->channel ? 0x80 : 0x40;
903 hwif->bus_state = state;
905 /* Grab the status. */
906 pci_read_config_word(dev, mcr_addr, &mcr);
907 pci_read_config_byte(dev, 0x59, &bsr2);
910 * Set the state. We don't set it if we don't need to do so.
911 * Make sure that the drive knows that it has failed if it's off.
915 if (!(bsr2 & resetmask))
917 hwif->drives[0].failures = hwif->drives[1].failures = 0;
919 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
920 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
923 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
925 mcr &= ~TRISTATE_BIT;
927 case BUSSTATE_TRISTATE:
928 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
936 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
937 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
939 pci_write_config_word(dev, mcr_addr, mcr);
940 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
945 * hpt37x_calibrate_dpll - calibrate the DPLL
948 * Perform a calibration cycle on the DPLL.
949 * Returns 1 if this succeeds
951 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
953 u32 dpll = (f_high << 16) | f_low | 0x100;
957 pci_write_config_dword(dev, 0x5c, dpll);
959 /* Wait for oscillator ready */
960 for(i = 0; i < 0x5000; ++i) {
962 pci_read_config_byte(dev, 0x5b, &scr2);
966 /* See if it stays ready (we'll just bail out if it's not yet) */
967 for(i = 0; i < 0x1000; ++i) {
968 pci_read_config_byte(dev, 0x5b, &scr2);
969 /* DPLL destabilized? */
973 /* Turn off tuning, we have the DPLL set */
974 pci_read_config_dword (dev, 0x5c, &dpll);
975 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
979 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
981 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
982 unsigned long io_base = pci_resource_start(dev, 4);
983 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
984 enum ata_clock clock;
987 printk(KERN_ERR "%s: out of memory!\n", name);
992 * Copy everything from a static "template" structure
993 * to just allocated per-chip hpt_info structure.
995 *info = *(struct hpt_info *)pci_get_drvdata(dev);
998 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
999 * We don't seem to be using it.
1001 if (dev->resource[PCI_ROM_RESOURCE].start)
1002 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1003 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1005 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1006 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1007 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1008 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1011 * First, try to estimate the PCI clock frequency...
1013 if (info->chip_type >= HPT370) {
1018 /* Interrupt force enable. */
1019 pci_read_config_byte(dev, 0x5a, &scr1);
1021 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1024 * HighPoint does this for HPT372A.
1025 * NOTE: This register is only writeable via I/O space.
1027 if (info->chip_type == HPT372A)
1028 outb(0x0e, io_base + 0x9c);
1031 * Default to PCI clock. Make sure MA15/16 are set to output
1032 * to prevent drives having problems with 40-pin cables.
1034 pci_write_config_byte(dev, 0x5b, 0x23);
1037 * We'll have to read f_CNT value in order to determine
1038 * the PCI clock frequency according to the following ratio:
1040 * f_CNT = Fpci * 192 / Fdpll
1042 * First try reading the register in which the HighPoint BIOS
1043 * saves f_CNT value before reprogramming the DPLL from its
1044 * default setting (which differs for the various chips).
1045 * NOTE: This register is only accessible via I/O space.
1047 * In case the signature check fails, we'll have to resort to
1048 * reading the f_CNT register itself in hopes that nobody has
1049 * touched the DPLL yet...
1051 temp = inl(io_base + 0x90);
1052 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1055 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1058 /* Calculate the average value of f_CNT. */
1059 for (temp = i = 0; i < 128; i++) {
1060 pci_read_config_word(dev, 0x78, &f_cnt);
1061 temp += f_cnt & 0x1ff;
1066 f_cnt = temp & 0x1ff;
1068 dpll_clk = info->dpll_clk;
1069 pci_clk = (f_cnt * dpll_clk) / 192;
1071 /* Clamp PCI clock to bands. */
1074 else if(pci_clk < 45)
1076 else if(pci_clk < 55)
1081 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1082 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1086 pci_read_config_dword(dev, 0x40, &itr1);
1088 /* Detect PCI clock by looking at cmd_high_time. */
1089 switch((itr1 >> 8) & 0x07) {
1103 /* Let's assume we'll use PCI clock for the ATA clock... */
1106 clock = ATA_CLOCK_25MHZ;
1110 clock = ATA_CLOCK_33MHZ;
1113 clock = ATA_CLOCK_40MHZ;
1116 clock = ATA_CLOCK_50MHZ;
1119 clock = ATA_CLOCK_66MHZ;
1124 * Only try the DPLL if we don't have a table for the PCI clock that
1125 * we are running at for HPT370/A, always use it for anything newer...
1127 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1128 * We also don't like using the DPLL because this causes glitches
1129 * on PRST-/SRST- when the state engine gets reset...
1131 if (info->chip_type >= HPT374 || info->settings[clock] == NULL) {
1132 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1136 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1137 * supported/enabled, use 50 MHz DPLL clock otherwise...
1139 if (info->max_ultra == 6) {
1141 clock = ATA_CLOCK_66MHZ;
1142 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1144 clock = ATA_CLOCK_50MHZ;
1147 if (info->settings[clock] == NULL) {
1148 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1153 /* Select the DPLL clock. */
1154 pci_write_config_byte(dev, 0x5b, 0x21);
1157 * Adjust the DPLL based upon PCI clock, enable it,
1158 * and wait for stabilization...
1160 f_low = (pci_clk * 48) / dpll_clk;
1162 for (adjust = 0; adjust < 8; adjust++) {
1163 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1167 * See if it'll settle at a fractionally different clock
1170 f_low -= adjust >> 1;
1172 f_low += adjust >> 1;
1175 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1180 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1182 /* Mark the fact that we're not using the DPLL. */
1185 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1189 * Advance the table pointer to a slot which points to the list
1190 * of the register values settings matching the clock being used.
1192 info->settings += clock;
1194 /* Store the clock frequencies. */
1195 info->dpll_clk = dpll_clk;
1196 info->pci_clk = pci_clk;
1198 /* Point to this chip's own instance of the hpt_info structure. */
1199 pci_set_drvdata(dev, info);
1201 if (info->chip_type >= HPT370) {
1205 * Reset the state engines.
1206 * NOTE: Avoid accidentally enabling the disabled channels.
1208 pci_read_config_byte (dev, 0x50, &mcr1);
1209 pci_read_config_byte (dev, 0x54, &mcr4);
1210 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1211 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1216 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1217 * the MISC. register to stretch the UltraDMA Tss timing.
1218 * NOTE: This register is only writeable via I/O space.
1220 if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1222 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1227 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1229 struct pci_dev *dev = hwif->pci_dev;
1230 struct hpt_info *info = pci_get_drvdata(dev);
1231 int serialize = HPT_SERIALIZE_IO;
1232 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1233 u8 chip_type = info->chip_type;
1234 u8 new_mcr, old_mcr = 0;
1236 /* Cache the channel's MISC. control registers' offset */
1237 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1239 hwif->tuneproc = &hpt3xx_tune_drive;
1240 hwif->speedproc = &hpt3xx_tune_chipset;
1241 hwif->quirkproc = &hpt3xx_quirkproc;
1242 hwif->intrproc = &hpt3xx_intrproc;
1243 hwif->maskproc = &hpt3xx_maskproc;
1244 hwif->busproc = &hpt3xx_busproc;
1246 if (chip_type <= HPT370A)
1247 hwif->udma_filter = &hpt3xx_udma_filter;
1250 * HPT3xxN chips have some complications:
1252 * - on 33 MHz PCI we must clock switch
1253 * - on 66 MHz PCI we must NOT use the PCI clock
1255 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1257 * Clock is shared between the channels,
1258 * so we'll have to serialize them... :-(
1261 hwif->rw_disk = &hpt3xxn_rw_disk;
1264 /* Serialize access to this device if needed */
1265 if (serialize && hwif->mate)
1266 hwif->serialized = hwif->mate->serialized = 1;
1269 * Disable the "fast interrupt" prediction. Don't hold off
1270 * on interrupts. (== 0x01 despite what the docs say)
1272 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1274 if (info->chip_type >= HPT374)
1275 new_mcr = old_mcr & ~0x07;
1276 else if (info->chip_type >= HPT370) {
1280 #ifdef HPT_DELAY_INTERRUPT
1285 } else /* HPT366 and HPT368 */
1286 new_mcr = old_mcr & ~0x80;
1288 if (new_mcr != old_mcr)
1289 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1291 if (!hwif->dma_base) {
1292 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1296 hwif->ultra_mask = hwif->cds->udma_mask;
1297 hwif->mwdma_mask = 0x07;
1300 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1301 * address lines to access an external EEPROM. To read valid
1302 * cable detect state the pins must be enabled as inputs.
1304 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1306 * HPT374 PCI function 1
1307 * - set bit 15 of reg 0x52 to enable TCBLID as input
1308 * - set bit 15 of reg 0x56 to enable FCBLID as input
1310 u8 mcr_addr = hwif->select_data + 2;
1313 pci_read_config_word (dev, mcr_addr, &mcr);
1314 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1315 /* now read cable id register */
1316 pci_read_config_byte (dev, 0x5a, &scr1);
1317 pci_write_config_word(dev, mcr_addr, mcr);
1318 } else if (chip_type >= HPT370) {
1320 * HPT370/372 and 374 pcifn 0
1321 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1325 pci_read_config_byte (dev, 0x5b, &scr2);
1326 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1327 /* now read cable id register */
1328 pci_read_config_byte (dev, 0x5a, &scr1);
1329 pci_write_config_byte(dev, 0x5b, scr2);
1331 pci_read_config_byte (dev, 0x5a, &scr1);
1333 if (!hwif->udma_four)
1334 hwif->udma_four = (scr1 & ata66) ? 0 : 1;
1336 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1338 if (chip_type >= HPT374) {
1339 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1340 hwif->ide_dma_end = &hpt374_ide_dma_end;
1341 } else if (chip_type >= HPT370) {
1342 hwif->dma_start = &hpt370_ide_dma_start;
1343 hwif->ide_dma_end = &hpt370_ide_dma_end;
1344 hwif->dma_timeout = &hpt370_dma_timeout;
1346 hwif->dma_lost_irq = &hpt366_dma_lost_irq;
1350 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1353 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1355 struct pci_dev *dev = hwif->pci_dev;
1356 u8 masterdma = 0, slavedma = 0;
1357 u8 dma_new = 0, dma_old = 0;
1358 unsigned long flags;
1360 dma_old = hwif->INB(dmabase + 2);
1362 local_irq_save(flags);
1365 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1366 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1368 if (masterdma & 0x30) dma_new |= 0x20;
1369 if ( slavedma & 0x30) dma_new |= 0x40;
1370 if (dma_new != dma_old)
1371 hwif->OUTB(dma_new, dmabase + 2);
1373 local_irq_restore(flags);
1375 ide_setup_dma(hwif, dmabase, 8);
1378 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1380 struct pci_dev *dev2;
1382 if (PCI_FUNC(dev->devfn) & 1)
1385 pci_set_drvdata(dev, &hpt374);
1387 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1390 pci_set_drvdata(dev2, &hpt374);
1392 if (dev2->irq != dev->irq) {
1393 /* FIXME: we need a core pci_set_interrupt() */
1394 dev2->irq = dev->irq;
1395 printk(KERN_WARNING "%s: PCI config space interrupt "
1396 "fixed.\n", d->name);
1398 ret = ide_setup_pci_devices(dev, dev2, d);
1403 return ide_setup_pci_device(dev, d);
1406 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1408 pci_set_drvdata(dev, &hpt372n);
1410 return ide_setup_pci_device(dev, d);
1413 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1415 struct hpt_info *info;
1416 u8 rev = 0, mcr1 = 0;
1418 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1421 d->name = "HPT371N";
1428 * HPT371 chips physically have only one channel, the secondary one,
1429 * but the primary channel registers do exist! Go figure...
1430 * So, we manually disable the non-existing channel here
1431 * (if the BIOS hasn't done this already).
1433 pci_read_config_byte(dev, 0x50, &mcr1);
1435 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1437 pci_set_drvdata(dev, info);
1439 return ide_setup_pci_device(dev, d);
1442 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1444 struct hpt_info *info;
1447 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1450 d->name = "HPT372N";
1455 pci_set_drvdata(dev, info);
1457 return ide_setup_pci_device(dev, d);
1460 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1462 struct hpt_info *info;
1465 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1468 d->name = "HPT302N";
1473 pci_set_drvdata(dev, info);
1475 return ide_setup_pci_device(dev, d);
1478 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1480 struct pci_dev *dev2;
1482 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1483 "HPT370", "HPT370A", "HPT372",
1485 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1486 &hpt370, &hpt370a, &hpt372,
1489 if (PCI_FUNC(dev->devfn) & 1)
1492 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1499 * HPT36x chips have one channel per function and have
1500 * both channel enable bits located differently and visible
1501 * to both functions -- really stupid design decision... :-(
1502 * Bit 4 is for the primary channel, bit 5 for the secondary.
1505 d->enablebits[0].mask = d->enablebits[0].val = 0x10;
1507 d->udma_mask = HPT366_ALLOW_ATA66_3 ?
1508 (HPT366_ALLOW_ATA66_4 ? 0x1f : 0x0f) : 0x07;
1512 d->udma_mask = HPT370_ALLOW_ATA100_5 ? 0x3f : 0x1f;
1519 d->udma_mask = HPT372_ALLOW_ATA133_6 ? 0x7f : 0x3f;
1523 d->name = chipset_names[rev];
1525 pci_set_drvdata(dev, info[rev]);
1530 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1531 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1534 pci_set_drvdata(dev2, info[rev]);
1537 * Now we'll have to force both channels enabled if
1538 * at least one of them has been enabled by BIOS...
1540 pci_read_config_byte(dev, 0x50, &mcr1);
1542 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1544 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1545 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1546 if (pin1 != pin2 && dev->irq == dev2->irq) {
1547 d->bootable = ON_BOARD;
1548 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1549 d->name, pin1, pin2);
1551 ret = ide_setup_pci_devices(dev, dev2, d);
1557 return ide_setup_pci_device(dev, d);
1560 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1563 .init_setup = init_setup_hpt366,
1564 .init_chipset = init_chipset_hpt366,
1565 .init_hwif = init_hwif_hpt366,
1566 .init_dma = init_dma_hpt366,
1569 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1570 .bootable = OFF_BOARD,
1574 .init_setup = init_setup_hpt372a,
1575 .init_chipset = init_chipset_hpt366,
1576 .init_hwif = init_hwif_hpt366,
1577 .init_dma = init_dma_hpt366,
1580 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1581 .udma_mask = HPT372_ALLOW_ATA133_6 ? 0x7f : 0x3f,
1582 .bootable = OFF_BOARD,
1586 .init_setup = init_setup_hpt302,
1587 .init_chipset = init_chipset_hpt366,
1588 .init_hwif = init_hwif_hpt366,
1589 .init_dma = init_dma_hpt366,
1592 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1593 .udma_mask = HPT302_ALLOW_ATA133_6 ? 0x7f : 0x3f,
1594 .bootable = OFF_BOARD,
1598 .init_setup = init_setup_hpt371,
1599 .init_chipset = init_chipset_hpt366,
1600 .init_hwif = init_hwif_hpt366,
1601 .init_dma = init_dma_hpt366,
1604 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1605 .udma_mask = HPT371_ALLOW_ATA133_6 ? 0x7f : 0x3f,
1606 .bootable = OFF_BOARD,
1610 .init_setup = init_setup_hpt374,
1611 .init_chipset = init_chipset_hpt366,
1612 .init_hwif = init_hwif_hpt366,
1613 .init_dma = init_dma_hpt366,
1614 .channels = 2, /* 4 */
1616 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1618 .bootable = OFF_BOARD,
1622 .init_setup = init_setup_hpt372n,
1623 .init_chipset = init_chipset_hpt366,
1624 .init_hwif = init_hwif_hpt366,
1625 .init_dma = init_dma_hpt366,
1626 .channels = 2, /* 4 */
1628 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1629 .udma_mask = HPT372_ALLOW_ATA133_6 ? 0x7f : 0x3f,
1630 .bootable = OFF_BOARD,
1636 * hpt366_init_one - called when an HPT366 is found
1637 * @dev: the hpt366 device
1638 * @id: the matching pci id
1640 * Called when the PCI registration layer (or the IDE initialization)
1641 * finds a device matching our IDE device tables.
1643 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1644 * structure depending on the chip's revision, we'd better pass a local
1645 * copy down the call chain...
1647 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1649 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1651 return d.init_setup(dev, &d);
1654 static struct pci_device_id hpt366_pci_tbl[] = {
1655 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1656 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1657 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1658 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1659 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1660 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1663 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1665 static struct pci_driver driver = {
1666 .name = "HPT366_IDE",
1667 .id_table = hpt366_pci_tbl,
1668 .probe = hpt366_init_one,
1671 static int __init hpt366_ide_init(void)
1673 return ide_pci_register_driver(&driver);
1676 module_init(hpt366_ide_init);
1678 MODULE_AUTHOR("Andre Hedrick");
1679 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1680 MODULE_LICENSE("GPL");