1 // SPDX-License-Identifier: GPL-2.0-only
3 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
4 * Due to massive hardware bugs, UltraDMA is only supported
5 * on the 646U2 and not on the 646U.
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
8 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
10 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
12 * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/pci.h>
18 #include <linux/ide.h>
19 #include <linux/init.h>
23 #define DRV_NAME "cmd64x"
26 * CMD64x specific registers definition.
29 #define CFR_INTR_CH0 0x04
37 #define ARTTIM23_DIS_RA2 0x04
38 #define ARTTIM23_DIS_RA3 0x08
39 #define ARTTIM23_INTR_CH1 0x10
46 #define MRDMODE_INTR_CH0 0x04
47 #define MRDMODE_INTR_CH1 0x08
48 #define UDIDETCR0 0x73
52 #define UDIDETCR1 0x7B
55 static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
57 ide_hwif_t *hwif = drive->hwif;
58 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
59 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
60 const unsigned long T = 1000000 / bus_speed;
61 static const u8 recovery_values[] =
62 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
63 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
64 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
65 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
69 ide_timing_compute(drive, mode, &t, T, 0);
72 * In case we've got too long recovery phase, try to lengthen
76 t.active += t.recover - 16;
79 if (t.active > 16) /* shouldn't actually happen... */
83 * Convert values to internal chipset representation
85 t.recover = recovery_values[t.recover];
88 /* Program the active/recovery counts into the DRWTIM register */
89 pci_write_config_byte(dev, drwtim_regs[drive->dn],
90 (t.active << 4) | t.recover);
93 * The primary channel has individual address setup timing registers
94 * for each drive and the hardware selects the slowest timing itself.
95 * The secondary channel has one common register and we have to select
96 * the slowest address setup timing ourselves.
99 ide_drive_t *pair = ide_get_pair_dev(drive);
102 struct ide_timing tp;
104 ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);
105 ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP);
106 if (pair->dma_mode) {
107 ide_timing_compute(pair, pair->dma_mode,
109 ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP);
114 if (t.setup > 5) /* shouldn't actually happen... */
118 * Program the address setup clocks into the ARTTIM registers.
119 * Avoid clearing the secondary channel's interrupt bit.
121 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
123 arttim &= ~ARTTIM23_INTR_CH1;
125 arttim |= setup_values[t.setup];
126 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
130 * Attempts to set drive's PIO mode.
131 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
134 static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
136 const u8 pio = drive->pio_mode - XFER_PIO_0;
139 * Filter out the prefetch control values
140 * to prevent PIO5 from being programmed
142 if (pio == 8 || pio == 9)
145 cmd64x_program_timings(drive, XFER_PIO_0 + pio);
148 static void cmd64x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
150 struct pci_dev *dev = to_pci_dev(hwif->dev);
151 u8 unit = drive->dn & 0x01;
152 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
153 const u8 speed = drive->dma_mode;
155 pci_read_config_byte(dev, pciU, ®U);
156 regU &= ~(unit ? 0xCA : 0x35);
160 regU |= unit ? 0x0A : 0x05;
163 regU |= unit ? 0x4A : 0x15;
166 regU |= unit ? 0x8A : 0x25;
169 regU |= unit ? 0x42 : 0x11;
172 regU |= unit ? 0x82 : 0x21;
175 regU |= unit ? 0xC2 : 0x31;
180 cmd64x_program_timings(drive, speed);
184 pci_write_config_byte(dev, pciU, regU);
187 static void cmd648_clear_irq(ide_drive_t *drive)
189 ide_hwif_t *hwif = drive->hwif;
190 struct pci_dev *dev = to_pci_dev(hwif->dev);
191 unsigned long base = pci_resource_start(dev, 4);
192 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
194 u8 mrdmode = inb(base + 1);
196 /* clear the interrupt bit */
197 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
201 static void cmd64x_clear_irq(ide_drive_t *drive)
203 ide_hwif_t *hwif = drive->hwif;
204 struct pci_dev *dev = to_pci_dev(hwif->dev);
205 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
206 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
210 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
211 /* clear the interrupt bit */
212 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
215 static int cmd648_test_irq(ide_hwif_t *hwif)
217 struct pci_dev *dev = to_pci_dev(hwif->dev);
218 unsigned long base = pci_resource_start(dev, 4);
219 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
221 u8 mrdmode = inb(base + 1);
223 pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
224 hwif->name, mrdmode, irq_mask);
226 return (mrdmode & irq_mask) ? 1 : 0;
229 static int cmd64x_test_irq(ide_hwif_t *hwif)
231 struct pci_dev *dev = to_pci_dev(hwif->dev);
232 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
233 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
237 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
239 pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
240 hwif->name, irq_stat, irq_mask);
242 return (irq_stat & irq_mask) ? 1 : 0;
246 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
247 * event order for DMA transfers.
250 static int cmd646_1_dma_end(ide_drive_t *drive)
252 ide_hwif_t *hwif = drive->hwif;
253 u8 dma_stat = 0, dma_cmd = 0;
256 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
257 /* read DMA command state */
258 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
260 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
261 /* clear the INTR & ERROR bits */
262 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
263 /* verify good DMA status */
264 return (dma_stat & 7) != 4;
267 static int init_chipset_cmd64x(struct pci_dev *dev)
271 /* Set a good latency timer and cache line size value. */
272 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
273 /* FIXME: pci_set_master() to ensure a good latency timer value */
276 * Enable interrupts, select MEMORY READ LINE for reads.
278 * NOTE: although not mentioned in the PCI0646U specs,
279 * bits 0-1 are write only and won't be read back as
280 * set or not -- PCI0646U2 specs clarify this point.
282 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
284 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
289 static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
291 struct pci_dev *dev = to_pci_dev(hwif->dev);
292 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
294 switch (dev->device) {
295 case PCI_DEVICE_ID_CMD_648:
296 case PCI_DEVICE_ID_CMD_649:
297 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
298 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
300 return ATA_CBL_PATA40;
304 static const struct ide_port_ops cmd64x_port_ops = {
305 .set_pio_mode = cmd64x_set_pio_mode,
306 .set_dma_mode = cmd64x_set_dma_mode,
307 .clear_irq = cmd64x_clear_irq,
308 .test_irq = cmd64x_test_irq,
309 .cable_detect = cmd64x_cable_detect,
312 static const struct ide_port_ops cmd648_port_ops = {
313 .set_pio_mode = cmd64x_set_pio_mode,
314 .set_dma_mode = cmd64x_set_dma_mode,
315 .clear_irq = cmd648_clear_irq,
316 .test_irq = cmd648_test_irq,
317 .cable_detect = cmd64x_cable_detect,
320 static const struct ide_dma_ops cmd646_rev1_dma_ops = {
321 .dma_host_set = ide_dma_host_set,
322 .dma_setup = ide_dma_setup,
323 .dma_start = ide_dma_start,
324 .dma_end = cmd646_1_dma_end,
325 .dma_test_irq = ide_dma_test_irq,
326 .dma_lost_irq = ide_dma_lost_irq,
327 .dma_timer_expiry = ide_dma_sff_timer_expiry,
328 .dma_sff_read_status = ide_dma_sff_read_status,
331 static const struct ide_port_info cmd64x_chipsets[] = {
334 .init_chipset = init_chipset_cmd64x,
335 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
336 .port_ops = &cmd64x_port_ops,
337 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
338 IDE_HFLAG_ABUSE_PREFETCH |
340 .pio_mask = ATA_PIO5,
341 .mwdma_mask = ATA_MWDMA2,
342 .udma_mask = 0x00, /* no udma */
346 .init_chipset = init_chipset_cmd64x,
347 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
348 .port_ops = &cmd648_port_ops,
349 .host_flags = IDE_HFLAG_ABUSE_PREFETCH |
351 .pio_mask = ATA_PIO5,
352 .mwdma_mask = ATA_MWDMA2,
353 .udma_mask = ATA_UDMA2,
357 .init_chipset = init_chipset_cmd64x,
358 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
359 .port_ops = &cmd648_port_ops,
360 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
361 .pio_mask = ATA_PIO5,
362 .mwdma_mask = ATA_MWDMA2,
363 .udma_mask = ATA_UDMA4,
367 .init_chipset = init_chipset_cmd64x,
368 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
369 .port_ops = &cmd648_port_ops,
370 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
371 .pio_mask = ATA_PIO5,
372 .mwdma_mask = ATA_MWDMA2,
373 .udma_mask = ATA_UDMA5,
377 static int cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
379 struct ide_port_info d;
380 u8 idx = id->driver_data;
382 d = cmd64x_chipsets[idx];
386 * UltraDMA only supported on PCI646U and PCI646U2, which
387 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
388 * Actually, although the CMD tech support people won't
389 * tell me the details, the 0x03 revision cannot support
390 * UDMA correctly without hardware modifications, and even
391 * then it only works with Quantum disks due to some
392 * hold time assumptions in the 646U part which are fixed
395 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
397 if (dev->revision < 5) {
400 * The original PCI0646 didn't have the primary
401 * channel enable bit, it appeared starting with
402 * PCI0646U (i.e. revision ID 3).
404 if (dev->revision < 3) {
405 d.enablebits[0].reg = 0;
406 d.port_ops = &cmd64x_port_ops;
407 if (dev->revision == 1)
408 d.dma_ops = &cmd646_rev1_dma_ops;
413 return ide_pci_init_one(dev, &d, NULL);
416 static const struct pci_device_id cmd64x_pci_tbl[] = {
417 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
418 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
419 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
420 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
423 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
425 static struct pci_driver cmd64x_pci_driver = {
426 .name = "CMD64x_IDE",
427 .id_table = cmd64x_pci_tbl,
428 .probe = cmd64x_init_one,
429 .remove = ide_pci_remove,
430 .suspend = ide_pci_suspend,
431 .resume = ide_pci_resume,
434 static int __init cmd64x_ide_init(void)
436 return ide_pci_register_driver(&cmd64x_pci_driver);
439 static void __exit cmd64x_ide_exit(void)
441 pci_unregister_driver(&cmd64x_pci_driver);
444 module_init(cmd64x_ide_init);
445 module_exit(cmd64x_ide_exit);
447 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
448 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
449 MODULE_LICENSE("GPL");