drivers/i2c/zynq_i2c.c

   1 /*
   2  * Driver for the Zynq-7000 PS I2C controller
   3  * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   4  *
   5  * Author: Joe Hershberger <joe.hershberger@ni.com>
   6  * Copyright (c) 2012 Joe Hershberger.
   7  *
   8  * Copyright (c) 2012-2013 Xilinx, Michal Simek
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <i2c.h>
  16 #include <asm/errno.h>
  17 #include <asm/arch/hardware.h>
  18
  19 /* i2c register set */
  20 struct zynq_i2c_registers {
  21         u32 control;
  22         u32 status;
  23         u32 address;
  24         u32 data;
  25         u32 interrupt_status;
  26         u32 transfer_size;
  27         u32 slave_mon_pause;
  28         u32 time_out;
  29         u32 interrupt_mask;
  30         u32 interrupt_enable;
  31         u32 interrupt_disable;
  32 };
  33
  34 /* Control register fields */
  35 #define ZYNQ_I2C_CONTROL_RW             0x00000001
  36 #define ZYNQ_I2C_CONTROL_MS             0x00000002
  37 #define ZYNQ_I2C_CONTROL_NEA            0x00000004
  38 #define ZYNQ_I2C_CONTROL_ACKEN          0x00000008
  39 #define ZYNQ_I2C_CONTROL_HOLD           0x00000010
  40 #define ZYNQ_I2C_CONTROL_SLVMON         0x00000020
  41 #define ZYNQ_I2C_CONTROL_CLR_FIFO       0x00000040
  42 #define ZYNQ_I2C_CONTROL_DIV_B_SHIFT    8
  43 #define ZYNQ_I2C_CONTROL_DIV_B_MASK     0x00003F00
  44 #define ZYNQ_I2C_CONTROL_DIV_A_SHIFT    14
  45 #define ZYNQ_I2C_CONTROL_DIV_A_MASK     0x0000C000
  46
  47 /* Status register values */
  48 #define ZYNQ_I2C_STATUS_RXDV    0x00000020
  49 #define ZYNQ_I2C_STATUS_TXDV    0x00000040
  50 #define ZYNQ_I2C_STATUS_RXOVF   0x00000080
  51 #define ZYNQ_I2C_STATUS_BA      0x00000100
  52
  53 /* Interrupt register fields */
  54 #define ZYNQ_I2C_INTERRUPT_COMP         0x00000001
  55 #define ZYNQ_I2C_INTERRUPT_DATA         0x00000002
  56 #define ZYNQ_I2C_INTERRUPT_NACK         0x00000004
  57 #define ZYNQ_I2C_INTERRUPT_TO           0x00000008
  58 #define ZYNQ_I2C_INTERRUPT_SLVRDY       0x00000010
  59 #define ZYNQ_I2C_INTERRUPT_RXOVF        0x00000020
  60 #define ZYNQ_I2C_INTERRUPT_TXOVF        0x00000040
  61 #define ZYNQ_I2C_INTERRUPT_RXUNF        0x00000080
  62 #define ZYNQ_I2C_INTERRUPT_ARBLOST      0x00000200
  63
  64 #define ZYNQ_I2C_FIFO_DEPTH             16
  65 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX     255 /* Controller transfer limit */
  66
  67 static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap)
  68 {
  69         return adap->hwadapnr ?
  70                 /* Zynq PS I2C1 */
  71                 (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
  72                 /* Zynq PS I2C0 */
  73                 (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
  74 }
  75
  76 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
  77 static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
  78                           int slaveadd)
  79 {
  80         struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
  81
  82         /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
  83         writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
  84                 (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
  85
  86         /* Enable master mode, ack, and 7-bit addressing */
  87         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
  88                 ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
  89 }
  90
  91 #ifdef DEBUG
  92 static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
  93 {
  94         int int_status;
  95         int status;
  96         int_status = readl(&zynq_i2c->interrupt_status);
  97
  98         status = readl(&zynq_i2c->status);
  99         if (int_status || status) {
 100                 debug("Status: ");
 101                 if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
 102                         debug("COMP ");
 103                 if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
 104                         debug("DATA ");
 105                 if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
 106                         debug("NACK ");
 107                 if (int_status & ZYNQ_I2C_INTERRUPT_TO)
 108                         debug("TO ");
 109                 if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
 110                         debug("SLVRDY ");
 111                 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
 112                         debug("RXOVF ");
 113                 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
 114                         debug("TXOVF ");
 115                 if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
 116                         debug("RXUNF ");
 117                 if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
 118                         debug("ARBLOST ");
 119                 if (status & ZYNQ_I2C_STATUS_RXDV)
 120                         debug("RXDV ");
 121                 if (status & ZYNQ_I2C_STATUS_TXDV)
 122                         debug("TXDV ");
 123                 if (status & ZYNQ_I2C_STATUS_RXOVF)
 124                         debug("RXOVF ");
 125                 if (status & ZYNQ_I2C_STATUS_BA)
 126                         debug("BA ");
 127                 debug("TS%d ", readl(&zynq_i2c->transfer_size));
 128                 debug("\n");
 129         }
 130 }
 131 #endif
 132
 133 /* Wait for an interrupt */
 134 static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
 135 {
 136         int timeout, int_status;
 137
 138         for (timeout = 0; timeout < 100; timeout++) {
 139                 udelay(100);
 140                 int_status = readl(&zynq_i2c->interrupt_status);
 141                 if (int_status & mask)
 142                         break;
 143         }
 144 #ifdef DEBUG
 145         zynq_i2c_debug_status(zynq_i2c);
 146 #endif
 147         /* Clear interrupt status flags */
 148         writel(int_status & mask, &zynq_i2c->interrupt_status);
 149
 150         return int_status & mask;
 151 }
 152
 153 /*
 154  * I2C probe called by cmd_i2c when doing 'i2c probe'.
 155  * Begin read, nak data byte, end.
 156  */
 157 static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
 158 {
 159         struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 160
 161         /* Attempt to read a byte */
 162         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 163                 ZYNQ_I2C_CONTROL_RW);
 164         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 165         writel(0xFF, &zynq_i2c->interrupt_status);
 166         writel(dev, &zynq_i2c->address);
 167         writel(1, &zynq_i2c->transfer_size);
 168
 169         return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
 170                 ZYNQ_I2C_INTERRUPT_NACK) &
 171                 ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
 172 }
 173
 174 /*
 175  * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 176  * Begin write, send address byte(s), begin read, receive data bytes, end.
 177  */
 178 static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 179                          int alen, u8 *data, int length)
 180 {
 181         u32 status;
 182         u32 i = 0;
 183         u8 *cur_data = data;
 184         struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 185
 186         /* Check the hardware can handle the requested bytes */
 187         if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
 188                 return -EINVAL;
 189
 190         /* Write the register address */
 191         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 192                 ZYNQ_I2C_CONTROL_HOLD);
 193         /*
 194          * Temporarily disable restart (by clearing hold)
 195          * It doesn't seem to work.
 196          */
 197         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 198         writel(0xFF, &zynq_i2c->interrupt_status);
 199         if (alen) {
 200                 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
 201                 writel(dev, &zynq_i2c->address);
 202                 while (alen--)
 203                         writel(addr >> (8 * alen), &zynq_i2c->data);
 204
 205                 /* Wait for the address to be sent */
 206                 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
 207                         /* Release the bus */
 208                         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 209                         return -ETIMEDOUT;
 210                 }
 211                 debug("Device acked address\n");
 212         }
 213
 214         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 215                 ZYNQ_I2C_CONTROL_RW);
 216         /* Start reading data */
 217         writel(dev, &zynq_i2c->address);
 218         writel(length, &zynq_i2c->transfer_size);
 219
 220         /* Wait for data */
 221         do {
 222                 status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
 223                         ZYNQ_I2C_INTERRUPT_DATA);
 224                 if (!status) {
 225                         /* Release the bus */
 226                         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 227                         return -ETIMEDOUT;
 228                 }
 229                 debug("Read %d bytes\n",
 230                       length - readl(&zynq_i2c->transfer_size));
 231                 for (; i < length - readl(&zynq_i2c->transfer_size); i++)
 232                         *(cur_data++) = readl(&zynq_i2c->data);
 233         } while (readl(&zynq_i2c->transfer_size) != 0);
 234         /* All done... release the bus */
 235         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 236
 237 #ifdef DEBUG
 238         zynq_i2c_debug_status(zynq_i2c);
 239 #endif
 240         return 0;
 241 }
 242
 243 /*
 244  * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 245  * Begin write, send address byte(s), send data bytes, end.
 246  */
 247 static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 248                           int alen, u8 *data, int length)
 249 {
 250         u8 *cur_data = data;
 251         struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 252
 253         /* Write the register address */
 254         setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 255                 ZYNQ_I2C_CONTROL_HOLD);
 256         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
 257         writel(0xFF, &zynq_i2c->interrupt_status);
 258         writel(dev, &zynq_i2c->address);
 259         if (alen) {
 260                 while (alen--)
 261                         writel(addr >> (8 * alen), &zynq_i2c->data);
 262                 /* Start the tranfer */
 263                 if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
 264                         /* Release the bus */
 265                         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 266                         return -ETIMEDOUT;
 267                 }
 268                 debug("Device acked address\n");
 269         }
 270
 271         while (length--) {
 272                 writel(*(cur_data++), &zynq_i2c->data);
 273                 if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
 274                         if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
 275                                 /* Release the bus */
 276                                 clrbits_le32(&zynq_i2c->control,
 277                                              ZYNQ_I2C_CONTROL_HOLD);
 278                                 return -ETIMEDOUT;
 279                         }
 280                 }
 281         }
 282
 283         /* All done... release the bus */
 284         clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 285         /* Wait for the address and data to be sent */
 286         if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
 287                 return -ETIMEDOUT;
 288         return 0;
 289 }
 290
 291 static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
 292                         unsigned int speed)
 293 {
 294         if (speed != 1000000)
 295                 return -EINVAL;
 296
 297         return 0;
 298 }
 299
 300 U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
 301                          zynq_i2c_write, zynq_i2c_set_bus_speed,
 302                          CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
 303                          0)
 304 U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
 305                          zynq_i2c_write, zynq_i2c_set_bus_speed,
 306                          CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
 307                          1)