2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
3 * Copyright (c) 2010-2011 NVIDIA Corporation
4 * NVIDIA Corporation <www.nvidia.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/clock.h>
30 #include <asm/arch/funcmux.h>
31 #include <asm/arch/gpio.h>
32 #include <asm/arch/pinmux.h>
33 #include <asm/arch-tegra/clk_rst.h>
34 #include <asm/arch-tegra/tegra_i2c.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 static unsigned int i2c_bus_num;
40 /* Information about i2c controller */
43 enum periph_id periph_id;
46 struct i2c_control *control;
47 struct i2c_ctlr *regs;
48 int is_dvc; /* DVC type, rather than I2C */
49 int is_scs; /* single clock source (T114+) */
50 int inited; /* bus is inited */
53 static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS];
55 static void set_packet_mode(struct i2c_bus *i2c_bus)
59 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
61 if (i2c_bus->is_dvc) {
62 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
64 writel(config, &dvc->cnfg);
66 writel(config, &i2c_bus->regs->cnfg);
68 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
69 * issues, i.e., some slaves may be wrongly detected.
71 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
75 static void i2c_reset_controller(struct i2c_bus *i2c_bus)
77 /* Reset I2C controller. */
78 reset_periph(i2c_bus->periph_id, 1);
80 /* re-program config register to packet mode */
81 set_packet_mode(i2c_bus);
84 static void i2c_init_controller(struct i2c_bus *i2c_bus)
87 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
88 * here, in section 23.3.1, but in fact we seem to need a factor of
89 * 16 to get the right frequency.
91 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
92 i2c_bus->speed * 2 * 8);
94 if (i2c_bus->is_scs) {
96 * T114 I2C went to a single clock source for standard/fast and
97 * HS clock speeds. The new clock rate setting calculation is:
98 * SCL = CLK_SOURCE.I2C /
99 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
100 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
102 * NOTE: We do this here, after the initial clock/pll start,
103 * because if we read the clk_div reg before the controller
104 * is running, we hang, and we need it for the new calc.
106 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
107 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
108 clk_div_stdfst_mode);
110 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
111 CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) *
115 /* Reset I2C controller. */
116 i2c_reset_controller(i2c_bus);
118 /* Configure I2C controller. */
119 if (i2c_bus->is_dvc) { /* only for DVC I2C */
120 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
122 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
125 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
128 static void send_packet_headers(
129 struct i2c_bus *i2c_bus,
130 struct i2c_trans_info *trans,
135 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
136 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
137 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
138 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
139 writel(data, &i2c_bus->control->tx_fifo);
140 debug("pkt header 1 sent (0x%x)\n", data);
142 /* prepare header2 */
143 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
144 writel(data, &i2c_bus->control->tx_fifo);
145 debug("pkt header 2 sent (0x%x)\n", data);
147 /* prepare IO specific header: configure the slave address */
148 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
150 /* Enable Read if it is not a write transaction */
151 if (!(trans->flags & I2C_IS_WRITE))
152 data |= PKT_HDR3_READ_MODE_MASK;
154 /* Write I2C specific header */
155 writel(data, &i2c_bus->control->tx_fifo);
156 debug("pkt header 3 sent (0x%x)\n", data);
159 static int wait_for_tx_fifo_empty(struct i2c_control *control)
162 int timeout_us = I2C_TIMEOUT_USEC;
164 while (timeout_us >= 0) {
165 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
166 >> TX_FIFO_EMPTY_CNT_SHIFT;
167 if (count == I2C_FIFO_DEPTH)
176 static int wait_for_rx_fifo_notempty(struct i2c_control *control)
179 int timeout_us = I2C_TIMEOUT_USEC;
181 while (timeout_us >= 0) {
182 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
183 >> TX_FIFO_FULL_CNT_SHIFT;
193 static int wait_for_transfer_complete(struct i2c_control *control)
196 int timeout_us = I2C_TIMEOUT_USEC;
198 while (timeout_us >= 0) {
199 int_status = readl(&control->int_status);
200 if (int_status & I2C_INT_NO_ACK_MASK)
202 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
204 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
214 static int send_recv_packets(struct i2c_bus *i2c_bus,
215 struct i2c_trans_info *trans)
217 struct i2c_control *control = i2c_bus->control;
224 int is_write = trans->flags & I2C_IS_WRITE;
226 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
227 int_status = readl(&control->int_status);
228 writel(int_status, &control->int_status);
230 send_packet_headers(i2c_bus, trans, 1);
232 words = DIV_ROUND_UP(trans->num_bytes, 4);
233 last_bytes = trans->num_bytes & 3;
237 u32 *wptr = (u32 *)dptr;
240 /* deal with word alignment */
241 if ((unsigned)dptr & 3) {
242 memcpy(&local, dptr, sizeof(u32));
243 writel(local, &control->tx_fifo);
244 debug("pkt data sent (0x%x)\n", local);
246 writel(*wptr, &control->tx_fifo);
247 debug("pkt data sent (0x%x)\n", *wptr);
249 if (!wait_for_tx_fifo_empty(control)) {
254 if (!wait_for_rx_fifo_notempty(control)) {
259 * for the last word, we read into our local buffer,
260 * in case that caller did not provide enough buffer.
262 local = readl(&control->rx_fifo);
263 if ((words == 1) && last_bytes)
264 memcpy(dptr, (char *)&local, last_bytes);
265 else if ((unsigned)dptr & 3)
266 memcpy(dptr, &local, sizeof(u32));
269 debug("pkt data received (0x%x)\n", local);
275 if (wait_for_transfer_complete(control)) {
281 /* error, reset the controller. */
282 i2c_reset_controller(i2c_bus);
287 static int tegra_i2c_write_data(u32 addr, u8 *data, u32 len)
290 struct i2c_trans_info trans_info;
292 trans_info.address = addr;
293 trans_info.buf = data;
294 trans_info.flags = I2C_IS_WRITE;
295 trans_info.num_bytes = len;
296 trans_info.is_10bit_address = 0;
298 error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
300 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
305 static int tegra_i2c_read_data(u32 addr, u8 *data, u32 len)
308 struct i2c_trans_info trans_info;
310 trans_info.address = addr | 1;
311 trans_info.buf = data;
312 trans_info.flags = 0;
313 trans_info.num_bytes = len;
314 trans_info.is_10bit_address = 0;
316 error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
318 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
323 #ifndef CONFIG_OF_CONTROL
324 #error "Please enable device tree support to use this driver"
327 unsigned int i2c_get_bus_speed(void)
329 return i2c_controllers[i2c_bus_num].speed;
332 int i2c_set_bus_speed(unsigned int speed)
334 struct i2c_bus *i2c_bus;
336 i2c_bus = &i2c_controllers[i2c_bus_num];
337 i2c_bus->speed = speed;
338 i2c_init_controller(i2c_bus);
343 static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus)
345 i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");
348 * We don't have a binding for pinmux yet. Leave it out for now. So
349 * far no one needs anything other than the default.
351 i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
352 i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0);
353 i2c_bus->periph_id = clock_decode_periph_id(blob, node);
356 * We can't specify the pinmux config in the fdt, so I2C2 will not
357 * work on Seaboard. It normally has no devices on it anyway.
358 * You could add in this little hack if you need to use it.
359 * The correct solution is a pinmux binding in the fdt.
361 * if (i2c_bus->periph_id == PERIPH_ID_I2C2)
362 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
364 if (i2c_bus->periph_id == -1)
365 return -FDT_ERR_NOTFOUND;
371 * Process a list of nodes, adding them to our list of I2C ports.
373 * @param blob fdt blob
374 * @param node_list list of nodes to process (any <=0 are ignored)
375 * @param count number of nodes to process
376 * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
377 * @param is_scs 1 if this HW uses a single clock source (T114+)
378 * @return 0 if ok, -1 on error
380 static int process_nodes(const void *blob, int node_list[], int count,
381 int is_dvc, int is_scs)
383 struct i2c_bus *i2c_bus;
386 /* build the i2c_controllers[] for each controller */
387 for (i = 0; i < count; i++) {
388 int node = node_list[i];
393 i2c_bus = &i2c_controllers[i];
396 if (i2c_get_config(blob, node, i2c_bus)) {
397 printf("i2c_init_board: failed to decode bus %d\n", i);
401 i2c_bus->is_scs = is_scs;
403 i2c_bus->is_dvc = is_dvc;
406 &((struct dvc_ctlr *)i2c_bus->regs)->control;
408 i2c_bus->control = &i2c_bus->regs->control;
410 debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
411 is_dvc ? "dvc" : "i2c", i, i2c_bus->regs,
412 i2c_bus->periph_id, i2c_bus->speed);
413 i2c_init_controller(i2c_bus);
417 /* Mark position as used */
424 /* Sadly there is no error return from this function */
425 void i2c_init_board(void)
427 int node_list[TEGRA_I2C_NUM_CONTROLLERS];
428 const void *blob = gd->fdt_blob;
431 /* First check for newer (T114+) I2C ports */
432 count = fdtdec_find_aliases_for_id(blob, "i2c",
433 COMPAT_NVIDIA_TEGRA114_I2C, node_list,
434 TEGRA_I2C_NUM_CONTROLLERS);
435 if (process_nodes(blob, node_list, count, 0, 1))
438 /* Now get the older (T20/T30) normal I2C ports */
439 count = fdtdec_find_aliases_for_id(blob, "i2c",
440 COMPAT_NVIDIA_TEGRA20_I2C, node_list,
441 TEGRA_I2C_NUM_CONTROLLERS);
442 if (process_nodes(blob, node_list, count, 0, 0))
445 /* Now look for dvc ports */
446 count = fdtdec_add_aliases_for_id(blob, "i2c",
447 COMPAT_NVIDIA_TEGRA20_DVC, node_list,
448 TEGRA_I2C_NUM_CONTROLLERS);
449 if (process_nodes(blob, node_list, count, 1, 0))
453 void i2c_init(int speed, int slaveaddr)
455 /* This will override the speed selected in the fdt for that port */
456 debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
457 i2c_set_bus_speed(speed);
460 /* i2c write version without the register address */
461 int i2c_write_data(uchar chip, uchar *buffer, int len)
465 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
466 debug("write_data: ");
467 /* use rc for counter */
468 for (rc = 0; rc < len; ++rc)
469 debug(" 0x%02x", buffer[rc]);
472 /* Shift 7-bit address over for lower-level i2c functions */
473 rc = tegra_i2c_write_data(chip << 1, buffer, len);
475 debug("i2c_write_data(): rc=%d\n", rc);
480 /* i2c read version without the register address */
481 int i2c_read_data(uchar chip, uchar *buffer, int len)
485 debug("inside i2c_read_data():\n");
486 /* Shift 7-bit address over for lower-level i2c functions */
487 rc = tegra_i2c_read_data(chip << 1, buffer, len);
489 debug("i2c_read_data(): rc=%d\n", rc);
493 debug("i2c_read_data: ");
494 /* reuse rc for counter*/
495 for (rc = 0; rc < len; ++rc)
496 debug(" 0x%02x", buffer[rc]);
502 /* Probe to see if a chip is present. */
503 int i2c_probe(uchar chip)
508 debug("i2c_probe: addr=0x%x\n", chip);
510 rc = i2c_write_data(chip, ®, 1);
512 debug("Error probing 0x%x.\n", chip);
518 static int i2c_addr_ok(const uint addr, const int alen)
520 /* We support 7 or 10 bit addresses, so one or two bytes each */
521 return alen == 1 || alen == 2;
525 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
530 debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n",
532 if (!i2c_addr_ok(addr, alen)) {
533 debug("i2c_read: Bad address %x.%d.\n", addr, alen);
536 for (offset = 0; offset < len; offset++) {
539 for (i = 0; i < alen; i++) {
541 (addr + offset) >> (8 * i);
543 if (i2c_write_data(chip, data, alen)) {
544 debug("i2c_read: error sending (0x%x)\n",
549 if (i2c_read_data(chip, buffer + offset, 1)) {
550 debug("i2c_read: error reading (0x%x)\n", addr);
559 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
564 debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n",
566 if (!i2c_addr_ok(addr, alen)) {
567 debug("i2c_write: Bad address %x.%d.\n", addr, alen);
570 for (offset = 0; offset < len; offset++) {
571 uchar data[alen + 1];
572 for (i = 0; i < alen; i++)
573 data[alen - i - 1] = (addr + offset) >> (8 * i);
574 data[alen] = buffer[offset];
575 if (i2c_write_data(chip, data, alen + 1)) {
576 debug("i2c_write: error sending (0x%x)\n", addr);
584 #if defined(CONFIG_I2C_MULTI_BUS)
586 * Functions for multiple I2C bus handling
588 unsigned int i2c_get_bus_num(void)
593 int i2c_set_bus_num(unsigned int bus)
595 if (bus >= TEGRA_I2C_NUM_CONTROLLERS || !i2c_controllers[bus].inited)
603 int tegra_i2c_get_dvc_bus_num(void)
607 for (i = 0; i < CONFIG_SYS_MAX_I2C_BUS; i++) {
608 struct i2c_bus *bus = &i2c_controllers[i];
610 if (bus->inited && bus->is_dvc)