Merge branch 'master_net/phy/prep-cleanup' of https://source.denx.de/u-boot/custodian...
[platform/kernel/u-boot.git] / drivers / i2c / tegra_i2c.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
4  * Copyright (c) 2010-2011 NVIDIA Corporation
5  *  NVIDIA Corporation <www.nvidia.com>
6  */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <i2c.h>
12 #include <log.h>
13 #include <asm/io.h>
14 #include <clk.h>
15 #include <reset.h>
16 #ifndef CONFIG_TEGRA186
17 #include <asm/arch/clock.h>
18 #include <asm/arch/funcmux.h>
19 #endif
20 #include <asm/arch/gpio.h>
21 #include <asm/arch-tegra/tegra_i2c.h>
22 #include <linux/delay.h>
23 #include <linux/err.h>
24
25 enum i2c_type {
26         TYPE_114,
27         TYPE_STD,
28         TYPE_DVC,
29 };
30
31 /* Information about i2c controller */
32 struct i2c_bus {
33         int                     id;
34         struct reset_ctl        reset_ctl;
35         struct clk              clk;
36         int                     speed;
37         int                     pinmux_config;
38         struct i2c_control      *control;
39         struct i2c_ctlr         *regs;
40         enum i2c_type           type;
41         int                     inited; /* bus is inited */
42 };
43
44 static void set_packet_mode(struct i2c_bus *i2c_bus)
45 {
46         u32 config;
47
48         config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
49
50         if (i2c_bus->type == TYPE_DVC) {
51                 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
52
53                 writel(config, &dvc->cnfg);
54         } else {
55                 writel(config, &i2c_bus->regs->cnfg);
56                 /*
57                  * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
58                  * issues, i.e., some slaves may be wrongly detected.
59                  */
60                 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
61         }
62 }
63
64 static void i2c_reset_controller(struct i2c_bus *i2c_bus)
65 {
66         /* Reset I2C controller. */
67         reset_assert(&i2c_bus->reset_ctl);
68         udelay(1);
69         reset_deassert(&i2c_bus->reset_ctl);
70         udelay(1);
71
72         /* re-program config register to packet mode */
73         set_packet_mode(i2c_bus);
74 }
75
76 static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
77 {
78         int ret;
79
80         ret = reset_assert(&i2c_bus->reset_ctl);
81         if (ret)
82                 return ret;
83         ret = clk_enable(&i2c_bus->clk);
84         if (ret)
85                 return ret;
86         ret = clk_set_rate(&i2c_bus->clk, rate);
87         if (IS_ERR_VALUE(ret))
88                 return ret;
89         ret = reset_deassert(&i2c_bus->reset_ctl);
90         if (ret)
91                 return ret;
92
93         return 0;
94 }
95
96 static void i2c_init_controller(struct i2c_bus *i2c_bus)
97 {
98         if (!i2c_bus->speed)
99                 return;
100         debug("%s: speed=%d\n", __func__, i2c_bus->speed);
101         /*
102          * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
103          * here, in section 23.3.1, but in fact we seem to need a factor of
104          * 16 to get the right frequency.
105          */
106         i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
107
108         if (i2c_bus->type == TYPE_114) {
109                 /*
110                  * T114 I2C went to a single clock source for standard/fast and
111                  * HS clock speeds. The new clock rate setting calculation is:
112                  *  SCL = CLK_SOURCE.I2C /
113                  *   (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
114                  *   I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
115                  *
116                  * NOTE: We do this here, after the initial clock/pll start,
117                  * because if we read the clk_div reg before the controller
118                  * is running, we hang, and we need it for the new calc.
119                  */
120                 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
121                 unsigned rate = CLK_MULT_STD_FAST_MODE *
122                                 (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
123                 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
124                         clk_div_stdfst_mode);
125
126                 i2c_init_clock(i2c_bus, rate);
127         }
128
129         /* Reset I2C controller. */
130         i2c_reset_controller(i2c_bus);
131
132         /* Configure I2C controller. */
133         if (i2c_bus->type == TYPE_DVC) {        /* only for DVC I2C */
134                 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
135
136                 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
137         }
138
139 #ifndef CONFIG_TEGRA186
140         funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
141 #endif
142 }
143
144 static void send_packet_headers(
145         struct i2c_bus *i2c_bus,
146         struct i2c_trans_info *trans,
147         u32 packet_id,
148         bool end_with_repeated_start)
149 {
150         u32 data;
151
152         /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
153         data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
154         data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
155         data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
156         writel(data, &i2c_bus->control->tx_fifo);
157         debug("pkt header 1 sent (0x%x)\n", data);
158
159         /* prepare header2 */
160         data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
161         writel(data, &i2c_bus->control->tx_fifo);
162         debug("pkt header 2 sent (0x%x)\n", data);
163
164         /* prepare IO specific header: configure the slave address */
165         data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
166
167         /* Enable Read if it is not a write transaction */
168         if (!(trans->flags & I2C_IS_WRITE))
169                 data |= PKT_HDR3_READ_MODE_MASK;
170         if (end_with_repeated_start)
171                 data |= PKT_HDR3_REPEAT_START_MASK;
172
173         /* Write I2C specific header */
174         writel(data, &i2c_bus->control->tx_fifo);
175         debug("pkt header 3 sent (0x%x)\n", data);
176 }
177
178 static int wait_for_tx_fifo_empty(struct i2c_control *control)
179 {
180         u32 count;
181         int timeout_us = I2C_TIMEOUT_USEC;
182
183         while (timeout_us >= 0) {
184                 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
185                                 >> TX_FIFO_EMPTY_CNT_SHIFT;
186                 if (count == I2C_FIFO_DEPTH)
187                         return 1;
188                 udelay(10);
189                 timeout_us -= 10;
190         }
191
192         return 0;
193 }
194
195 static int wait_for_rx_fifo_notempty(struct i2c_control *control)
196 {
197         u32 count;
198         int timeout_us = I2C_TIMEOUT_USEC;
199
200         while (timeout_us >= 0) {
201                 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
202                                 >> TX_FIFO_FULL_CNT_SHIFT;
203                 if (count)
204                         return 1;
205                 udelay(10);
206                 timeout_us -= 10;
207         }
208
209         return 0;
210 }
211
212 static int wait_for_transfer_complete(struct i2c_control *control)
213 {
214         int int_status;
215         int timeout_us = I2C_TIMEOUT_USEC;
216
217         while (timeout_us >= 0) {
218                 int_status = readl(&control->int_status);
219                 if (int_status & I2C_INT_NO_ACK_MASK)
220                         return -int_status;
221                 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
222                         return -int_status;
223                 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
224                         return 0;
225
226                 udelay(10);
227                 timeout_us -= 10;
228         }
229
230         return -1;
231 }
232
233 static int send_recv_packets(struct i2c_bus *i2c_bus,
234                              struct i2c_trans_info *trans)
235 {
236         struct i2c_control *control = i2c_bus->control;
237         u32 int_status;
238         u32 words;
239         u8 *dptr;
240         u32 local;
241         uchar last_bytes;
242         int error = 0;
243         int is_write = trans->flags & I2C_IS_WRITE;
244
245         /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
246         int_status = readl(&control->int_status);
247         writel(int_status, &control->int_status);
248
249         send_packet_headers(i2c_bus, trans, 1,
250                             trans->flags & I2C_USE_REPEATED_START);
251
252         words = DIV_ROUND_UP(trans->num_bytes, 4);
253         last_bytes = trans->num_bytes & 3;
254         dptr = trans->buf;
255
256         while (words) {
257                 u32 *wptr = (u32 *)dptr;
258
259                 if (is_write) {
260                         /* deal with word alignment */
261                         if ((words == 1) && last_bytes) {
262                                 local = 0;
263                                 memcpy(&local, dptr, last_bytes);
264                         } else if ((unsigned long)dptr & 3) {
265                                 memcpy(&local, dptr, sizeof(u32));
266                         } else {
267                                 local = *wptr;
268                         }
269                         writel(local, &control->tx_fifo);
270                         debug("pkt data sent (0x%x)\n", local);
271                         if (!wait_for_tx_fifo_empty(control)) {
272                                 error = -1;
273                                 goto exit;
274                         }
275                 } else {
276                         if (!wait_for_rx_fifo_notempty(control)) {
277                                 error = -1;
278                                 goto exit;
279                         }
280                         /*
281                          * for the last word, we read into our local buffer,
282                          * in case that caller did not provide enough buffer.
283                          */
284                         local = readl(&control->rx_fifo);
285                         if ((words == 1) && last_bytes)
286                                 memcpy(dptr, (char *)&local, last_bytes);
287                         else if ((unsigned long)dptr & 3)
288                                 memcpy(dptr, &local, sizeof(u32));
289                         else
290                                 *wptr = local;
291                         debug("pkt data received (0x%x)\n", local);
292                 }
293                 words--;
294                 dptr += sizeof(u32);
295         }
296
297         if (wait_for_transfer_complete(control)) {
298                 error = -1;
299                 goto exit;
300         }
301         return 0;
302 exit:
303         /* error, reset the controller. */
304         i2c_reset_controller(i2c_bus);
305
306         return error;
307 }
308
309 static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
310                                 u32 len, bool end_with_repeated_start)
311 {
312         int error;
313         struct i2c_trans_info trans_info;
314
315         trans_info.address = addr;
316         trans_info.buf = data;
317         trans_info.flags = I2C_IS_WRITE;
318         if (end_with_repeated_start)
319                 trans_info.flags |= I2C_USE_REPEATED_START;
320         trans_info.num_bytes = len;
321         trans_info.is_10bit_address = 0;
322
323         error = send_recv_packets(i2c_bus, &trans_info);
324         if (error)
325                 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
326
327         return error;
328 }
329
330 static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
331                                u32 len)
332 {
333         int error;
334         struct i2c_trans_info trans_info;
335
336         trans_info.address = addr | 1;
337         trans_info.buf = data;
338         trans_info.flags = 0;
339         trans_info.num_bytes = len;
340         trans_info.is_10bit_address = 0;
341
342         error = send_recv_packets(i2c_bus, &trans_info);
343         if (error)
344                 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
345
346         return error;
347 }
348
349 static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
350 {
351         struct i2c_bus *i2c_bus = dev_get_priv(dev);
352
353         i2c_bus->speed = speed;
354         i2c_init_controller(i2c_bus);
355
356         return 0;
357 }
358
359 static int tegra_i2c_probe(struct udevice *dev)
360 {
361         struct i2c_bus *i2c_bus = dev_get_priv(dev);
362         int ret;
363         bool is_dvc;
364
365         i2c_bus->id = dev_seq(dev);
366         i2c_bus->type = dev_get_driver_data(dev);
367         i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
368         if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
369                 debug("%s: Cannot get regs address\n", __func__);
370                 return -EINVAL;
371         }
372
373         ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
374         if (ret) {
375                 pr_err("reset_get_by_name() failed: %d\n", ret);
376                 return ret;
377         }
378         ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
379         if (ret) {
380                 pr_err("clk_get_by_name() failed: %d\n", ret);
381                 return ret;
382         }
383
384 #ifndef CONFIG_TEGRA186
385         /*
386          * We don't have a binding for pinmux yet. Leave it out for now. So
387          * far no one needs anything other than the default.
388          */
389         i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
390
391         /*
392          * We can't specify the pinmux config in the fdt, so I2C2 will not
393          * work on Seaboard. It normally has no devices on it anyway.
394          * You could add in this little hack if you need to use it.
395          * The correct solution is a pinmux binding in the fdt.
396          *
397          *      if (i2c_bus->clk.id == PERIPH_ID_I2C2)
398          *              i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
399          */
400 #endif
401
402         is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
403         if (is_dvc) {
404                 i2c_bus->control =
405                         &((struct dvc_ctlr *)i2c_bus->regs)->control;
406         } else {
407                 i2c_bus->control = &i2c_bus->regs->control;
408         }
409         i2c_init_controller(i2c_bus);
410         debug("%s: controller bus %d at %p, speed %d: ",
411               is_dvc ? "dvc" : "i2c", dev_seq(dev), i2c_bus->regs,
412               i2c_bus->speed);
413
414         return 0;
415 }
416
417 /* i2c write version without the register address */
418 static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
419                           int len, bool end_with_repeated_start)
420 {
421         int rc;
422
423         debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
424         debug("write_data: ");
425         /* use rc for counter */
426         for (rc = 0; rc < len; ++rc)
427                 debug(" 0x%02x", buffer[rc]);
428         debug("\n");
429
430         /* Shift 7-bit address over for lower-level i2c functions */
431         rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
432                                   end_with_repeated_start);
433         if (rc)
434                 debug("i2c_write_data(): rc=%d\n", rc);
435
436         return rc;
437 }
438
439 /* i2c read version without the register address */
440 static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
441                          int len)
442 {
443         int rc;
444
445         debug("inside i2c_read_data():\n");
446         /* Shift 7-bit address over for lower-level i2c functions */
447         rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
448         if (rc) {
449                 debug("i2c_read_data(): rc=%d\n", rc);
450                 return rc;
451         }
452
453         debug("i2c_read_data: ");
454         /* reuse rc for counter*/
455         for (rc = 0; rc < len; ++rc)
456                 debug(" 0x%02x", buffer[rc]);
457         debug("\n");
458
459         return 0;
460 }
461
462 /* Probe to see if a chip is present. */
463 static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
464                                 uint chip_flags)
465 {
466         struct i2c_bus *i2c_bus = dev_get_priv(bus);
467         int rc;
468         u8 reg;
469
470         /* Shift 7-bit address over for lower-level i2c functions */
471         rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
472                                   false);
473
474         return rc;
475 }
476
477 static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
478                           int nmsgs)
479 {
480         struct i2c_bus *i2c_bus = dev_get_priv(bus);
481         int ret;
482
483         debug("i2c_xfer: %d messages\n", nmsgs);
484         for (; nmsgs > 0; nmsgs--, msg++) {
485                 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
486
487                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
488                 if (msg->flags & I2C_M_RD) {
489                         ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
490                                             msg->len);
491                 } else {
492                         ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
493                                              msg->len, next_is_read);
494                 }
495                 if (ret) {
496                         debug("i2c_write: error sending\n");
497                         return -EREMOTEIO;
498                 }
499         }
500
501         return 0;
502 }
503
504 int tegra_i2c_get_dvc_bus(struct udevice **busp)
505 {
506         return uclass_first_device_drvdata(UCLASS_I2C, TYPE_DVC, busp);
507 }
508
509 static const struct dm_i2c_ops tegra_i2c_ops = {
510         .xfer           = tegra_i2c_xfer,
511         .probe_chip     = tegra_i2c_probe_chip,
512         .set_bus_speed  = tegra_i2c_set_bus_speed,
513 };
514
515 static const struct udevice_id tegra_i2c_ids[] = {
516         { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
517         { .compatible = "nvidia,tegra124-i2c", .data = TYPE_114 },
518         { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
519         { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
520         { }
521 };
522
523 U_BOOT_DRIVER(i2c_tegra) = {
524         .name   = "i2c_tegra",
525         .id     = UCLASS_I2C,
526         .of_match = tegra_i2c_ids,
527         .probe  = tegra_i2c_probe,
528         .priv_auto      = sizeof(struct i2c_bus),
529         .ops    = &tegra_i2c_ops,
530 };