1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
4 * Copyright (c) 2010-2011 NVIDIA Corporation
5 * NVIDIA Corporation <www.nvidia.com>
16 #ifndef CONFIG_TEGRA186
17 #include <asm/arch/clock.h>
18 #include <asm/arch/funcmux.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch-tegra/tegra_i2c.h>
22 #include <linux/err.h>
30 /* Information about i2c controller */
33 struct reset_ctl reset_ctl;
37 struct i2c_control *control;
38 struct i2c_ctlr *regs;
40 int inited; /* bus is inited */
43 static void set_packet_mode(struct i2c_bus *i2c_bus)
47 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
49 if (i2c_bus->type == TYPE_DVC) {
50 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
52 writel(config, &dvc->cnfg);
54 writel(config, &i2c_bus->regs->cnfg);
56 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
57 * issues, i.e., some slaves may be wrongly detected.
59 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
63 static void i2c_reset_controller(struct i2c_bus *i2c_bus)
65 /* Reset I2C controller. */
66 reset_assert(&i2c_bus->reset_ctl);
68 reset_deassert(&i2c_bus->reset_ctl);
71 /* re-program config register to packet mode */
72 set_packet_mode(i2c_bus);
75 static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
79 ret = reset_assert(&i2c_bus->reset_ctl);
82 ret = clk_enable(&i2c_bus->clk);
85 ret = clk_set_rate(&i2c_bus->clk, rate);
86 if (IS_ERR_VALUE(ret))
88 ret = reset_deassert(&i2c_bus->reset_ctl);
95 static void i2c_init_controller(struct i2c_bus *i2c_bus)
99 debug("%s: speed=%d\n", __func__, i2c_bus->speed);
101 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
102 * here, in section 23.3.1, but in fact we seem to need a factor of
103 * 16 to get the right frequency.
105 i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
107 if (i2c_bus->type == TYPE_114) {
109 * T114 I2C went to a single clock source for standard/fast and
110 * HS clock speeds. The new clock rate setting calculation is:
111 * SCL = CLK_SOURCE.I2C /
112 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
113 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
115 * NOTE: We do this here, after the initial clock/pll start,
116 * because if we read the clk_div reg before the controller
117 * is running, we hang, and we need it for the new calc.
119 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
120 unsigned rate = CLK_MULT_STD_FAST_MODE *
121 (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
122 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
123 clk_div_stdfst_mode);
125 i2c_init_clock(i2c_bus, rate);
128 /* Reset I2C controller. */
129 i2c_reset_controller(i2c_bus);
131 /* Configure I2C controller. */
132 if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
133 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
135 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
138 #ifndef CONFIG_TEGRA186
139 funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
143 static void send_packet_headers(
144 struct i2c_bus *i2c_bus,
145 struct i2c_trans_info *trans,
147 bool end_with_repeated_start)
151 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
152 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
153 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
154 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
155 writel(data, &i2c_bus->control->tx_fifo);
156 debug("pkt header 1 sent (0x%x)\n", data);
158 /* prepare header2 */
159 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
160 writel(data, &i2c_bus->control->tx_fifo);
161 debug("pkt header 2 sent (0x%x)\n", data);
163 /* prepare IO specific header: configure the slave address */
164 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
166 /* Enable Read if it is not a write transaction */
167 if (!(trans->flags & I2C_IS_WRITE))
168 data |= PKT_HDR3_READ_MODE_MASK;
169 if (end_with_repeated_start)
170 data |= PKT_HDR3_REPEAT_START_MASK;
172 /* Write I2C specific header */
173 writel(data, &i2c_bus->control->tx_fifo);
174 debug("pkt header 3 sent (0x%x)\n", data);
177 static int wait_for_tx_fifo_empty(struct i2c_control *control)
180 int timeout_us = I2C_TIMEOUT_USEC;
182 while (timeout_us >= 0) {
183 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
184 >> TX_FIFO_EMPTY_CNT_SHIFT;
185 if (count == I2C_FIFO_DEPTH)
194 static int wait_for_rx_fifo_notempty(struct i2c_control *control)
197 int timeout_us = I2C_TIMEOUT_USEC;
199 while (timeout_us >= 0) {
200 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
201 >> TX_FIFO_FULL_CNT_SHIFT;
211 static int wait_for_transfer_complete(struct i2c_control *control)
214 int timeout_us = I2C_TIMEOUT_USEC;
216 while (timeout_us >= 0) {
217 int_status = readl(&control->int_status);
218 if (int_status & I2C_INT_NO_ACK_MASK)
220 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
222 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
232 static int send_recv_packets(struct i2c_bus *i2c_bus,
233 struct i2c_trans_info *trans)
235 struct i2c_control *control = i2c_bus->control;
242 int is_write = trans->flags & I2C_IS_WRITE;
244 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
245 int_status = readl(&control->int_status);
246 writel(int_status, &control->int_status);
248 send_packet_headers(i2c_bus, trans, 1,
249 trans->flags & I2C_USE_REPEATED_START);
251 words = DIV_ROUND_UP(trans->num_bytes, 4);
252 last_bytes = trans->num_bytes & 3;
256 u32 *wptr = (u32 *)dptr;
259 /* deal with word alignment */
260 if ((words == 1) && last_bytes) {
262 memcpy(&local, dptr, last_bytes);
263 } else if ((unsigned long)dptr & 3) {
264 memcpy(&local, dptr, sizeof(u32));
268 writel(local, &control->tx_fifo);
269 debug("pkt data sent (0x%x)\n", local);
270 if (!wait_for_tx_fifo_empty(control)) {
275 if (!wait_for_rx_fifo_notempty(control)) {
280 * for the last word, we read into our local buffer,
281 * in case that caller did not provide enough buffer.
283 local = readl(&control->rx_fifo);
284 if ((words == 1) && last_bytes)
285 memcpy(dptr, (char *)&local, last_bytes);
286 else if ((unsigned long)dptr & 3)
287 memcpy(dptr, &local, sizeof(u32));
290 debug("pkt data received (0x%x)\n", local);
296 if (wait_for_transfer_complete(control)) {
302 /* error, reset the controller. */
303 i2c_reset_controller(i2c_bus);
308 static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
309 u32 len, bool end_with_repeated_start)
312 struct i2c_trans_info trans_info;
314 trans_info.address = addr;
315 trans_info.buf = data;
316 trans_info.flags = I2C_IS_WRITE;
317 if (end_with_repeated_start)
318 trans_info.flags |= I2C_USE_REPEATED_START;
319 trans_info.num_bytes = len;
320 trans_info.is_10bit_address = 0;
322 error = send_recv_packets(i2c_bus, &trans_info);
324 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
329 static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
333 struct i2c_trans_info trans_info;
335 trans_info.address = addr | 1;
336 trans_info.buf = data;
337 trans_info.flags = 0;
338 trans_info.num_bytes = len;
339 trans_info.is_10bit_address = 0;
341 error = send_recv_packets(i2c_bus, &trans_info);
343 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
348 static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
350 struct i2c_bus *i2c_bus = dev_get_priv(dev);
352 i2c_bus->speed = speed;
353 i2c_init_controller(i2c_bus);
358 static int tegra_i2c_probe(struct udevice *dev)
360 struct i2c_bus *i2c_bus = dev_get_priv(dev);
364 i2c_bus->id = dev->seq;
365 i2c_bus->type = dev_get_driver_data(dev);
366 i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
367 if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
368 debug("%s: Cannot get regs address\n", __func__);
372 ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
374 pr_err("reset_get_by_name() failed: %d\n", ret);
377 ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
379 pr_err("clk_get_by_name() failed: %d\n", ret);
383 #ifndef CONFIG_TEGRA186
385 * We don't have a binding for pinmux yet. Leave it out for now. So
386 * far no one needs anything other than the default.
388 i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
391 * We can't specify the pinmux config in the fdt, so I2C2 will not
392 * work on Seaboard. It normally has no devices on it anyway.
393 * You could add in this little hack if you need to use it.
394 * The correct solution is a pinmux binding in the fdt.
396 * if (i2c_bus->clk.id == PERIPH_ID_I2C2)
397 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
401 is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
404 &((struct dvc_ctlr *)i2c_bus->regs)->control;
406 i2c_bus->control = &i2c_bus->regs->control;
408 i2c_init_controller(i2c_bus);
409 debug("%s: controller bus %d at %p, speed %d: ",
410 is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed);
415 /* i2c write version without the register address */
416 static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
417 int len, bool end_with_repeated_start)
421 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
422 debug("write_data: ");
423 /* use rc for counter */
424 for (rc = 0; rc < len; ++rc)
425 debug(" 0x%02x", buffer[rc]);
428 /* Shift 7-bit address over for lower-level i2c functions */
429 rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
430 end_with_repeated_start);
432 debug("i2c_write_data(): rc=%d\n", rc);
437 /* i2c read version without the register address */
438 static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
443 debug("inside i2c_read_data():\n");
444 /* Shift 7-bit address over for lower-level i2c functions */
445 rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
447 debug("i2c_read_data(): rc=%d\n", rc);
451 debug("i2c_read_data: ");
452 /* reuse rc for counter*/
453 for (rc = 0; rc < len; ++rc)
454 debug(" 0x%02x", buffer[rc]);
460 /* Probe to see if a chip is present. */
461 static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
464 struct i2c_bus *i2c_bus = dev_get_priv(bus);
468 /* Shift 7-bit address over for lower-level i2c functions */
469 rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, ®, sizeof(reg),
475 static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
478 struct i2c_bus *i2c_bus = dev_get_priv(bus);
481 debug("i2c_xfer: %d messages\n", nmsgs);
482 for (; nmsgs > 0; nmsgs--, msg++) {
483 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
485 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
486 if (msg->flags & I2C_M_RD) {
487 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
490 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
491 msg->len, next_is_read);
494 debug("i2c_write: error sending\n");
502 int tegra_i2c_get_dvc_bus(struct udevice **busp)
504 return uclass_first_device_drvdata(UCLASS_I2C, TYPE_DVC, busp);
507 static const struct dm_i2c_ops tegra_i2c_ops = {
508 .xfer = tegra_i2c_xfer,
509 .probe_chip = tegra_i2c_probe_chip,
510 .set_bus_speed = tegra_i2c_set_bus_speed,
513 static const struct udevice_id tegra_i2c_ids[] = {
514 { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
515 { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
516 { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
520 U_BOOT_DRIVER(i2c_tegra) = {
523 .of_match = tegra_i2c_ids,
524 .probe = tegra_i2c_probe,
525 .priv_auto_alloc_size = sizeof(struct i2c_bus),
526 .ops = &tegra_i2c_ops,