drivers/i2c/sun8i_rsb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   4  *
   5  * Based on allwinner u-boot sources rsb code which is:
   6  * (C) Copyright 2007-2013
   7  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   8  * lixiang <lixiang@allwinnertech.com>
   9  */
  10
  11 #include <axp_pmic.h>
  12 #include <common.h>
  13 #include <dm.h>
  14 #include <errno.h>
  15 #include <i2c.h>
  16 #include <time.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/prcm.h>
  20 #include <asm/arch/rsb.h>
  21
  22 static int sun8i_rsb_await_trans(struct sunxi_rsb_reg *base)
  23 {
  24         unsigned long tmo = timer_get_us() + 1000000;
  25         u32 stat;
  26         int ret;
  27
  28         while (1) {
  29                 stat = readl(&base->stat);
  30                 if (stat & RSB_STAT_LBSY_INT) {
  31                         ret = -EBUSY;
  32                         break;
  33                 }
  34                 if (stat & RSB_STAT_TERR_INT) {
  35                         ret = -EIO;
  36                         break;
  37                 }
  38                 if (stat & RSB_STAT_TOVER_INT) {
  39                         ret = 0;
  40                         break;
  41                 }
  42                 if (timer_get_us() > tmo) {
  43                         ret = -ETIME;
  44                         break;
  45                 }
  46         }
  47         writel(stat, &base->stat); /* Clear status bits */
  48
  49         return ret;
  50 }
  51
  52 static int sun8i_rsb_do_trans(struct sunxi_rsb_reg *base)
  53 {
  54         setbits_le32(&base->ctrl, RSB_CTRL_START_TRANS);
  55
  56         return sun8i_rsb_await_trans(base);
  57 }
  58
  59 static int sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr,
  60                           u8 reg_addr, u8 *data)
  61 {
  62         int ret;
  63
  64         writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
  65         writel(reg_addr, &base->addr);
  66         writel(RSB_CMD_BYTE_READ, &base->cmd);
  67
  68         ret = sun8i_rsb_do_trans(base);
  69         if (ret)
  70                 return ret;
  71
  72         *data = readl(&base->data) & 0xff;
  73
  74         return 0;
  75 }
  76
  77 static int sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr,
  78                            u8 reg_addr, u8 data)
  79 {
  80         writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
  81         writel(reg_addr, &base->addr);
  82         writel(data, &base->data);
  83         writel(RSB_CMD_BYTE_WRITE, &base->cmd);
  84
  85         return sun8i_rsb_do_trans(base);
  86 }
  87
  88 static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
  89                                         u16 device_addr, u16 runtime_addr)
  90 {
  91         writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
  92                RSB_DEVADDR_DEVICE_ADDR(device_addr), &base->devaddr);
  93         writel(RSB_CMD_SET_RTSADDR, &base->cmd);
  94
  95         return sun8i_rsb_do_trans(base);
  96 }
  97
  98 static void sun8i_rsb_cfg_io(void)
  99 {
 100 #ifdef CONFIG_MACH_SUN8I
 101         sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
 102         sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
 103         sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
 104         sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
 105         sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
 106         sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
 107 #elif defined CONFIG_MACH_SUN9I
 108         sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
 109         sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
 110         sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
 111         sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
 112         sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
 113         sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
 114 #else
 115 #error unsupported MACH_SUNXI
 116 #endif
 117 }
 118
 119 static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
 120 {
 121         u32 div = 0;
 122         u32 cd_odly = 0;
 123
 124         /* Source is Hosc24M, set RSB clk to 3Mhz */
 125         div = 24000000 / 3000000 / 2 - 1;
 126         cd_odly = div >> 1;
 127         if (!cd_odly)
 128                 cd_odly = 1;
 129
 130         writel((cd_odly << 8) | div, &base->ccr);
 131 }
 132
 133 static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
 134 {
 135         unsigned long tmo = timer_get_us() + 1000000;
 136
 137         writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
 138                &base->dmcr);
 139
 140         while (readl(&base->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
 141                 if (timer_get_us() > tmo)
 142                         return -ETIME;
 143         }
 144
 145         return sun8i_rsb_await_trans(base);
 146 }
 147
 148 static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
 149 {
 150         /* Enable RSB and PIO clk, and de-assert their resets */
 151         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
 152
 153         /* Setup external pins */
 154         sun8i_rsb_cfg_io();
 155
 156         writel(RSB_CTRL_SOFT_RST, &base->ctrl);
 157         sun8i_rsb_set_clk(base);
 158
 159         return sun8i_rsb_set_device_mode(base);
 160 }
 161
 162 #if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
 163 int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data)
 164 {
 165         struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 166
 167         return sun8i_rsb_read(base, runtime_addr, reg_addr, data);
 168 }
 169
 170 int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data)
 171 {
 172         struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 173
 174         return sun8i_rsb_write(base, runtime_addr, reg_addr, data);
 175 }
 176
 177 int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
 178 {
 179         struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 180
 181         return sun8i_rsb_set_device_address(base, device_addr, runtime_addr);
 182 }
 183
 184 int rsb_init(void)
 185 {
 186         struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 187
 188         return sun8i_rsb_init(base);
 189 }
 190 #endif
 191
 192 #if CONFIG_IS_ENABLED(DM_I2C)
 193 struct sun8i_rsb_priv {
 194         struct sunxi_rsb_reg *base;
 195 };
 196
 197 /*
 198  * The mapping from hardware address to runtime address is fixed, and shared
 199  * among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux.
 200  */
 201 static int sun8i_rsb_get_runtime_address(u16 device_addr)
 202 {
 203         if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR)
 204                 return AXP_PMIC_PRI_RUNTIME_ADDR;
 205         if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR)
 206                 return AXP_PMIC_SEC_RUNTIME_ADDR;
 207
 208         return -ENXIO;
 209 }
 210
 211 static int sun8i_rsb_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 212 {
 213         int runtime_addr = sun8i_rsb_get_runtime_address(msg->addr);
 214         struct sun8i_rsb_priv *priv = dev_get_priv(bus);
 215
 216         if (runtime_addr < 0)
 217                 return runtime_addr;
 218
 219         /* The hardware only supports SMBus-style transfers. */
 220         if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
 221                 return sun8i_rsb_read(priv->base, runtime_addr,
 222                                       msg[0].buf[0], &msg[1].buf[0]);
 223
 224         if (nmsgs == 1 && msg[0].len == 2)
 225                 return sun8i_rsb_write(priv->base, runtime_addr,
 226                                        msg[0].buf[0], msg[0].buf[1]);
 227
 228         return -EINVAL;
 229 }
 230
 231 static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr,
 232                                 uint chip_flags)
 233 {
 234         int runtime_addr = sun8i_rsb_get_runtime_address(chip_addr);
 235         struct sun8i_rsb_priv *priv = dev_get_priv(bus);
 236
 237         if (runtime_addr < 0)
 238                 return runtime_addr;
 239
 240         return sun8i_rsb_set_device_address(priv->base, chip_addr, runtime_addr);
 241 }
 242
 243 static int sun8i_rsb_probe(struct udevice *bus)
 244 {
 245         struct sun8i_rsb_priv *priv = dev_get_priv(bus);
 246
 247         priv->base = dev_read_addr_ptr(bus);
 248
 249         return sun8i_rsb_init(priv->base);
 250 }
 251
 252 static int sun8i_rsb_child_pre_probe(struct udevice *child)
 253 {
 254         struct dm_i2c_chip *chip = dev_get_parent_plat(child);
 255
 256         /* Ensure each transfer is for a single register. */
 257         chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
 258
 259         return 0;
 260 }
 261
 262 static const struct dm_i2c_ops sun8i_rsb_ops = {
 263         .xfer           = sun8i_rsb_xfer,
 264         .probe_chip     = sun8i_rsb_probe_chip,
 265 };
 266
 267 static const struct udevice_id sun8i_rsb_ids[] = {
 268         { .compatible = "allwinner,sun8i-a23-rsb" },
 269         { /* sentinel */ }
 270 };
 271
 272 U_BOOT_DRIVER(sun8i_rsb) = {
 273         .name                   = "sun8i_rsb",
 274         .id                     = UCLASS_I2C,
 275         .of_match               = sun8i_rsb_ids,
 276         .probe                  = sun8i_rsb_probe,
 277         .child_pre_probe        = sun8i_rsb_child_pre_probe,
 278         .priv_auto              = sizeof(struct sun8i_rsb_priv),
 279         .ops                    = &sun8i_rsb_ops,
 280 };
 281 #endif /* CONFIG_IS_ENABLED(DM_I2C) */