drivers/i2c/sun6i_p2wi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Sunxi A31 Power Management Unit
   4  *
   5  * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
   6  * http://linux-sunxi.org
   7  *
   8  * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
   9  *
  10  * (C) Copyright 2006-2013
  11  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  12  * Berg Xing <bergxing@allwinnertech.com>
  13  * Tom Cubie <tangliang@allwinnertech.com>
  14  */
  15
  16 #include <axp_pmic.h>
  17 #include <clk.h>
  18 #include <common.h>
  19 #include <dm.h>
  20 #include <errno.h>
  21 #include <i2c.h>
  22 #include <reset.h>
  23 #include <time.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/cpu.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/p2wi.h>
  28 #include <asm/arch/prcm.h>
  29 #include <asm/arch/sys_proto.h>
  30
  31 static int sun6i_p2wi_await_trans(struct sunxi_p2wi_reg *base)
  32 {
  33         unsigned long tmo = timer_get_us() + 1000000;
  34         int ret;
  35         u8 reg;
  36
  37         while (1) {
  38                 reg = readl(&base->status);
  39                 if (reg & P2WI_STAT_TRANS_ERR) {
  40                         ret = -EIO;
  41                         break;
  42                 }
  43                 if (reg & P2WI_STAT_TRANS_DONE) {
  44                         ret = 0;
  45                         break;
  46                 }
  47                 if (timer_get_us() > tmo) {
  48                         ret = -ETIME;
  49                         break;
  50                 }
  51         }
  52         writel(reg, &base->status); /* Clear status bits */
  53
  54         return ret;
  55 }
  56
  57 static int sun6i_p2wi_read(struct sunxi_p2wi_reg *base, const u8 addr, u8 *data)
  58 {
  59         int ret;
  60
  61         writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0);
  62         writel(P2WI_DATA_NUM_BYTES(1) |
  63                P2WI_DATA_NUM_BYTES_READ, &base->numbytes);
  64         writel(P2WI_STAT_TRANS_DONE, &base->status);
  65         writel(P2WI_CTRL_TRANS_START, &base->ctrl);
  66
  67         ret = sun6i_p2wi_await_trans(base);
  68
  69         *data = readl(&base->data0) & P2WI_DATA_BYTE_1_MASK;
  70
  71         return ret;
  72 }
  73
  74 static int sun6i_p2wi_write(struct sunxi_p2wi_reg *base, const u8 addr, u8 data)
  75 {
  76         writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0);
  77         writel(P2WI_DATA_BYTE_1(data), &base->data0);
  78         writel(P2WI_DATA_NUM_BYTES(1), &base->numbytes);
  79         writel(P2WI_STAT_TRANS_DONE, &base->status);
  80         writel(P2WI_CTRL_TRANS_START, &base->ctrl);
  81
  82         return sun6i_p2wi_await_trans(base);
  83 }
  84
  85 static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base,
  86                                           u8 slave_addr, u8 ctrl_reg,
  87                                           u8 init_data)
  88 {
  89         unsigned long tmo = timer_get_us() + 1000000;
  90
  91         writel(P2WI_PM_DEV_ADDR(slave_addr) |
  92                P2WI_PM_CTRL_ADDR(ctrl_reg) |
  93                P2WI_PM_INIT_DATA(init_data) |
  94                P2WI_PM_INIT_SEND,
  95                &base->pm);
  96
  97         while ((readl(&base->pm) & P2WI_PM_INIT_SEND)) {
  98                 if (timer_get_us() > tmo)
  99                         return -ETIME;
 100         }
 101
 102         return 0;
 103 }
 104
 105 static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base)
 106 {
 107         /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
 108         writel(P2WI_CTRL_RESET, &base->ctrl);
 109         sdelay(0x100);
 110         writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
 111                &base->cc);
 112 }
 113
 114 #if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
 115 int p2wi_read(const u8 addr, u8 *data)
 116 {
 117         struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 118
 119         return sun6i_p2wi_read(base, addr, data);
 120 }
 121
 122 int p2wi_write(const u8 addr, u8 data)
 123 {
 124         struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 125
 126         return sun6i_p2wi_write(base, addr, data);
 127 }
 128
 129 int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
 130 {
 131         struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 132
 133         return sun6i_p2wi_change_to_p2wi_mode(base, slave_addr, ctrl_reg,
 134                                               init_data);
 135 }
 136
 137 void p2wi_init(void)
 138 {
 139         struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 140
 141         /* Enable p2wi and PIO clk, and de-assert their resets */
 142         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
 143
 144         sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
 145         sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
 146
 147         sun6i_p2wi_init(base);
 148 }
 149 #endif
 150
 151 #if CONFIG_IS_ENABLED(DM_I2C)
 152 struct sun6i_p2wi_priv {
 153         struct sunxi_p2wi_reg *base;
 154 };
 155
 156 static int sun6i_p2wi_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 157 {
 158         struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
 159
 160         /* The hardware only supports SMBus-style transfers. */
 161         if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
 162                 return sun6i_p2wi_read(priv->base,
 163                                        msg[0].buf[0], &msg[1].buf[0]);
 164
 165         if (nmsgs == 1 && msg[0].len == 2)
 166                 return sun6i_p2wi_write(priv->base,
 167                                         msg[0].buf[0], msg[0].buf[1]);
 168
 169         return -EINVAL;
 170 }
 171
 172 static int sun6i_p2wi_probe_chip(struct udevice *bus, uint chip_addr,
 173                                  uint chip_flags)
 174 {
 175         struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
 176
 177         return sun6i_p2wi_change_to_p2wi_mode(priv->base, chip_addr,
 178                                               AXP_PMIC_MODE_REG,
 179                                               AXP_PMIC_MODE_P2WI);
 180 }
 181
 182 static int sun6i_p2wi_probe(struct udevice *bus)
 183 {
 184         struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
 185         struct reset_ctl *reset;
 186         struct clk *clk;
 187
 188         priv->base = dev_read_addr_ptr(bus);
 189
 190         reset = devm_reset_control_get(bus, NULL);
 191         if (!IS_ERR(reset))
 192                 reset_deassert(reset);
 193
 194         clk = devm_clk_get(bus, NULL);
 195         if (!IS_ERR(clk))
 196                 clk_enable(clk);
 197
 198         sun6i_p2wi_init(priv->base);
 199
 200         return 0;
 201 }
 202
 203 static int sun6i_p2wi_child_pre_probe(struct udevice *child)
 204 {
 205         struct dm_i2c_chip *chip = dev_get_parent_plat(child);
 206         struct udevice *bus = child->parent;
 207
 208         /* Ensure each transfer is for a single register. */
 209         chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
 210
 211         return sun6i_p2wi_probe_chip(bus, chip->chip_addr, 0);
 212 }
 213
 214 static const struct dm_i2c_ops sun6i_p2wi_ops = {
 215         .xfer           = sun6i_p2wi_xfer,
 216         .probe_chip     = sun6i_p2wi_probe_chip,
 217 };
 218
 219 static const struct udevice_id sun6i_p2wi_ids[] = {
 220         { .compatible = "allwinner,sun6i-a31-p2wi" },
 221         { /* sentinel */ }
 222 };
 223
 224 U_BOOT_DRIVER(sun6i_p2wi) = {
 225         .name                   = "sun6i_p2wi",
 226         .id                     = UCLASS_I2C,
 227         .of_match               = sun6i_p2wi_ids,
 228         .probe                  = sun6i_p2wi_probe,
 229         .child_pre_probe        = sun6i_p2wi_child_pre_probe,
 230         .priv_auto              = sizeof(struct sun6i_p2wi_priv),
 231         .ops                    = &sun6i_p2wi_ops,
 232 };
 233 #endif /* CONFIG_IS_ENABLED(DM_I2C) */