drivers/i2c/sun6i_p2wi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Sunxi A31 Power Management Unit
   4  *
   5  * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
   6  * http://linux-sunxi.org
   7  *
   8  * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
   9  *
  10  * (C) Copyright 2006-2013
  11  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  12  * Berg Xing <bergxing@allwinnertech.com>
  13  * Tom Cubie <tangliang@allwinnertech.com>
  14  */
  15
  16 #include <axp_pmic.h>
  17 #include <common.h>
  18 #include <dm.h>
  19 #include <errno.h>
  20 #include <i2c.h>
  21 #include <time.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/cpu.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/p2wi.h>
  26 #include <asm/arch/prcm.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 static int sun6i_p2wi_await_trans(struct sunxi_p2wi_reg *base)
  30 {
  31         unsigned long tmo = timer_get_us() + 1000000;
  32         int ret;
  33         u8 reg;
  34
  35         while (1) {
  36                 reg = readl(&base->status);
  37                 if (reg & P2WI_STAT_TRANS_ERR) {
  38                         ret = -EIO;
  39                         break;
  40                 }
  41                 if (reg & P2WI_STAT_TRANS_DONE) {
  42                         ret = 0;
  43                         break;
  44                 }
  45                 if (timer_get_us() > tmo) {
  46                         ret = -ETIME;
  47                         break;
  48                 }
  49         }
  50         writel(reg, &base->status); /* Clear status bits */
  51
  52         return ret;
  53 }
  54
  55 static int sun6i_p2wi_read(struct sunxi_p2wi_reg *base, const u8 addr, u8 *data)
  56 {
  57         int ret;
  58
  59         writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0);
  60         writel(P2WI_DATA_NUM_BYTES(1) |
  61                P2WI_DATA_NUM_BYTES_READ, &base->numbytes);
  62         writel(P2WI_STAT_TRANS_DONE, &base->status);
  63         writel(P2WI_CTRL_TRANS_START, &base->ctrl);
  64
  65         ret = sun6i_p2wi_await_trans(base);
  66
  67         *data = readl(&base->data0) & P2WI_DATA_BYTE_1_MASK;
  68
  69         return ret;
  70 }
  71
  72 static int sun6i_p2wi_write(struct sunxi_p2wi_reg *base, const u8 addr, u8 data)
  73 {
  74         writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0);
  75         writel(P2WI_DATA_BYTE_1(data), &base->data0);
  76         writel(P2WI_DATA_NUM_BYTES(1), &base->numbytes);
  77         writel(P2WI_STAT_TRANS_DONE, &base->status);
  78         writel(P2WI_CTRL_TRANS_START, &base->ctrl);
  79
  80         return sun6i_p2wi_await_trans(base);
  81 }
  82
  83 static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base,
  84                                           u8 slave_addr, u8 ctrl_reg,
  85                                           u8 init_data)
  86 {
  87         unsigned long tmo = timer_get_us() + 1000000;
  88
  89         writel(P2WI_PM_DEV_ADDR(slave_addr) |
  90                P2WI_PM_CTRL_ADDR(ctrl_reg) |
  91                P2WI_PM_INIT_DATA(init_data) |
  92                P2WI_PM_INIT_SEND,
  93                &base->pm);
  94
  95         while ((readl(&base->pm) & P2WI_PM_INIT_SEND)) {
  96                 if (timer_get_us() > tmo)
  97                         return -ETIME;
  98         }
  99
 100         return 0;
 101 }
 102
 103 static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base)
 104 {
 105         /* Enable p2wi and PIO clk, and de-assert their resets */
 106         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
 107
 108         sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
 109         sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
 110
 111         /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
 112         writel(P2WI_CTRL_RESET, &base->ctrl);
 113         sdelay(0x100);
 114         writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
 115                &base->cc);
 116 }
 117
 118 #if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
 119 int p2wi_read(const u8 addr, u8 *data)
 120 {
 121         struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 122
 123         return sun6i_p2wi_read(base, addr, data);
 124 }
 125
 126 int p2wi_write(const u8 addr, u8 data)
 127 {
 128         struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 129
 130         return sun6i_p2wi_write(base, addr, data);
 131 }
 132
 133 int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
 134 {
 135         struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 136
 137         return sun6i_p2wi_change_to_p2wi_mode(base, slave_addr, ctrl_reg,
 138                                               init_data);
 139 }
 140
 141 void p2wi_init(void)
 142 {
 143         struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 144
 145         sun6i_p2wi_init(base);
 146 }
 147 #endif
 148
 149 #if CONFIG_IS_ENABLED(DM_I2C)
 150 struct sun6i_p2wi_priv {
 151         struct sunxi_p2wi_reg *base;
 152 };
 153
 154 static int sun6i_p2wi_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 155 {
 156         struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
 157
 158         /* The hardware only supports SMBus-style transfers. */
 159         if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
 160                 return sun6i_p2wi_read(priv->base,
 161                                        msg[0].buf[0], &msg[1].buf[0]);
 162
 163         if (nmsgs == 1 && msg[0].len == 2)
 164                 return sun6i_p2wi_write(priv->base,
 165                                         msg[0].buf[0], msg[0].buf[1]);
 166
 167         return -EINVAL;
 168 }
 169
 170 static int sun6i_p2wi_probe_chip(struct udevice *bus, uint chip_addr,
 171                                  uint chip_flags)
 172 {
 173         struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
 174
 175         return sun6i_p2wi_change_to_p2wi_mode(priv->base, chip_addr,
 176                                               AXP_PMIC_MODE_REG,
 177                                               AXP_PMIC_MODE_P2WI);
 178 }
 179
 180 static int sun6i_p2wi_probe(struct udevice *bus)
 181 {
 182         struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
 183
 184         priv->base = dev_read_addr_ptr(bus);
 185
 186         sun6i_p2wi_init(priv->base);
 187
 188         return 0;
 189 }
 190
 191 static int sun6i_p2wi_child_pre_probe(struct udevice *child)
 192 {
 193         struct dm_i2c_chip *chip = dev_get_parent_plat(child);
 194
 195         /* Ensure each transfer is for a single register. */
 196         chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
 197
 198         return 0;
 199 }
 200
 201 static const struct dm_i2c_ops sun6i_p2wi_ops = {
 202         .xfer           = sun6i_p2wi_xfer,
 203         .probe_chip     = sun6i_p2wi_probe_chip,
 204 };
 205
 206 static const struct udevice_id sun6i_p2wi_ids[] = {
 207         { .compatible = "allwinner,sun6i-a31-p2wi" },
 208         { /* sentinel */ }
 209 };
 210
 211 U_BOOT_DRIVER(sun6i_p2wi) = {
 212         .name                   = "sun6i_p2wi",
 213         .id                     = UCLASS_I2C,
 214         .of_match               = sun6i_p2wi_ids,
 215         .probe                  = sun6i_p2wi_probe,
 216         .child_pre_probe        = sun6i_p2wi_child_pre_probe,
 217         .priv_auto              = sizeof(struct sun6i_p2wi_priv),
 218         .ops                    = &sun6i_p2wi_ops,
 219 };
 220 #endif /* CONFIG_IS_ENABLED(DM_I2C) */