drivers/i2c/stm32f7_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 STMicroelectronics
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <i2c.h>
  10 #include <reset.h>
  11
  12 #include <dm/device.h>
  13 #include <linux/io.h>
  14
  15 /* STM32 I2C registers */
  16 struct stm32_i2c_regs {
  17         u32 cr1;        /* I2C control register 1 */
  18         u32 cr2;        /* I2C control register 2 */
  19         u32 oar1;       /* I2C own address 1 register */
  20         u32 oar2;       /* I2C own address 2 register */
  21         u32 timingr;    /* I2C timing register */
  22         u32 timeoutr;   /* I2C timeout register */
  23         u32 isr;        /* I2C interrupt and status register */
  24         u32 icr;        /* I2C interrupt clear register */
  25         u32 pecr;       /* I2C packet error checking register */
  26         u32 rxdr;       /* I2C receive data register */
  27         u32 txdr;       /* I2C transmit data register */
  28 };
  29
  30 #define STM32_I2C_CR1                           0x00
  31 #define STM32_I2C_CR2                           0x04
  32 #define STM32_I2C_TIMINGR                       0x10
  33 #define STM32_I2C_ISR                           0x18
  34 #define STM32_I2C_ICR                           0x1C
  35 #define STM32_I2C_RXDR                          0x24
  36 #define STM32_I2C_TXDR                          0x28
  37
  38 /* STM32 I2C control 1 */
  39 #define STM32_I2C_CR1_ANFOFF                    BIT(12)
  40 #define STM32_I2C_CR1_ERRIE                     BIT(7)
  41 #define STM32_I2C_CR1_TCIE                      BIT(6)
  42 #define STM32_I2C_CR1_STOPIE                    BIT(5)
  43 #define STM32_I2C_CR1_NACKIE                    BIT(4)
  44 #define STM32_I2C_CR1_ADDRIE                    BIT(3)
  45 #define STM32_I2C_CR1_RXIE                      BIT(2)
  46 #define STM32_I2C_CR1_TXIE                      BIT(1)
  47 #define STM32_I2C_CR1_PE                        BIT(0)
  48
  49 /* STM32 I2C control 2 */
  50 #define STM32_I2C_CR2_AUTOEND                   BIT(25)
  51 #define STM32_I2C_CR2_RELOAD                    BIT(24)
  52 #define STM32_I2C_CR2_NBYTES_MASK               GENMASK(23, 16)
  53 #define STM32_I2C_CR2_NBYTES(n)                 ((n & 0xff) << 16)
  54 #define STM32_I2C_CR2_NACK                      BIT(15)
  55 #define STM32_I2C_CR2_STOP                      BIT(14)
  56 #define STM32_I2C_CR2_START                     BIT(13)
  57 #define STM32_I2C_CR2_HEAD10R                   BIT(12)
  58 #define STM32_I2C_CR2_ADD10                     BIT(11)
  59 #define STM32_I2C_CR2_RD_WRN                    BIT(10)
  60 #define STM32_I2C_CR2_SADD10_MASK               GENMASK(9, 0)
  61 #define STM32_I2C_CR2_SADD10(n)                 (n & STM32_I2C_CR2_SADD10_MASK)
  62 #define STM32_I2C_CR2_SADD7_MASK                GENMASK(7, 1)
  63 #define STM32_I2C_CR2_SADD7(n)                  ((n & 0x7f) << 1)
  64 #define STM32_I2C_CR2_RESET_MASK                (STM32_I2C_CR2_HEAD10R \
  65                                                 | STM32_I2C_CR2_NBYTES_MASK \
  66                                                 | STM32_I2C_CR2_SADD7_MASK \
  67                                                 | STM32_I2C_CR2_RELOAD \
  68                                                 | STM32_I2C_CR2_RD_WRN)
  69
  70 /* STM32 I2C Interrupt Status */
  71 #define STM32_I2C_ISR_BUSY                      BIT(15)
  72 #define STM32_I2C_ISR_ARLO                      BIT(9)
  73 #define STM32_I2C_ISR_BERR                      BIT(8)
  74 #define STM32_I2C_ISR_TCR                       BIT(7)
  75 #define STM32_I2C_ISR_TC                        BIT(6)
  76 #define STM32_I2C_ISR_STOPF                     BIT(5)
  77 #define STM32_I2C_ISR_NACKF                     BIT(4)
  78 #define STM32_I2C_ISR_ADDR                      BIT(3)
  79 #define STM32_I2C_ISR_RXNE                      BIT(2)
  80 #define STM32_I2C_ISR_TXIS                      BIT(1)
  81 #define STM32_I2C_ISR_TXE                       BIT(0)
  82 #define STM32_I2C_ISR_ERRORS                    (STM32_I2C_ISR_BERR \
  83                                                 | STM32_I2C_ISR_ARLO)
  84
  85 /* STM32 I2C Interrupt Clear */
  86 #define STM32_I2C_ICR_ARLOCF                    BIT(9)
  87 #define STM32_I2C_ICR_BERRCF                    BIT(8)
  88 #define STM32_I2C_ICR_STOPCF                    BIT(5)
  89 #define STM32_I2C_ICR_NACKCF                    BIT(4)
  90
  91 /* STM32 I2C Timing */
  92 #define STM32_I2C_TIMINGR_PRESC(n)              ((n & 0xf) << 28)
  93 #define STM32_I2C_TIMINGR_SCLDEL(n)             ((n & 0xf) << 20)
  94 #define STM32_I2C_TIMINGR_SDADEL(n)             ((n & 0xf) << 16)
  95 #define STM32_I2C_TIMINGR_SCLH(n)               ((n & 0xff) << 8)
  96 #define STM32_I2C_TIMINGR_SCLL(n)               (n & 0xff)
  97
  98 #define STM32_I2C_MAX_LEN                       0xff
  99
 100 #define STM32_I2C_DNF_DEFAULT                   0
 101 #define STM32_I2C_DNF_MAX                       16
 102
 103 #define STM32_I2C_ANALOG_FILTER_ENABLE  1
 104 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN       50      /* ns */
 105 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX       260     /* ns */
 106
 107 #define STM32_I2C_RISE_TIME_DEFAULT             25      /* ns */
 108 #define STM32_I2C_FALL_TIME_DEFAULT             10      /* ns */
 109
 110 #define STM32_PRESC_MAX                         BIT(4)
 111 #define STM32_SCLDEL_MAX                        BIT(4)
 112 #define STM32_SDADEL_MAX                        BIT(4)
 113 #define STM32_SCLH_MAX                          BIT(8)
 114 #define STM32_SCLL_MAX                          BIT(8)
 115
 116 #define STM32_NSEC_PER_SEC                      1000000000L
 117
 118 /**
 119  * struct stm32_i2c_spec - private i2c specification timing
 120  * @rate: I2C bus speed (Hz)
 121  * @rate_min: 80% of I2C bus speed (Hz)
 122  * @rate_max: 120% of I2C bus speed (Hz)
 123  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 124  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 125  * @hddat_min: Min data hold time (ns)
 126  * @vddat_max: Max data valid time (ns)
 127  * @sudat_min: Min data setup time (ns)
 128  * @l_min: Min low period of the SCL clock (ns)
 129  * @h_min: Min high period of the SCL clock (ns)
 130  */
 131
 132 struct stm32_i2c_spec {
 133         u32 rate;
 134         u32 rate_min;
 135         u32 rate_max;
 136         u32 fall_max;
 137         u32 rise_max;
 138         u32 hddat_min;
 139         u32 vddat_max;
 140         u32 sudat_min;
 141         u32 l_min;
 142         u32 h_min;
 143 };
 144
 145 /**
 146  * struct stm32_i2c_setup - private I2C timing setup parameters
 147  * @speed: I2C speed mode (standard, Fast Plus)
 148  * @speed_freq: I2C speed frequency  (Hz)
 149  * @clock_src: I2C clock source frequency (Hz)
 150  * @rise_time: Rise time (ns)
 151  * @fall_time: Fall time (ns)
 152  * @dnf: Digital filter coefficient (0-16)
 153  * @analog_filter: Analog filter delay (On/Off)
 154  */
 155 struct stm32_i2c_setup {
 156         enum i2c_speed_mode speed;
 157         u32 speed_freq;
 158         u32 clock_src;
 159         u32 rise_time;
 160         u32 fall_time;
 161         u8 dnf;
 162         bool analog_filter;
 163 };
 164
 165 /**
 166  * struct stm32_i2c_timings - private I2C output parameters
 167  * @prec: Prescaler value
 168  * @scldel: Data setup time
 169  * @sdadel: Data hold time
 170  * @sclh: SCL high period (master mode)
 171  * @sclh: SCL low period (master mode)
 172  */
 173 struct stm32_i2c_timings {
 174         struct list_head node;
 175         u8 presc;
 176         u8 scldel;
 177         u8 sdadel;
 178         u8 sclh;
 179         u8 scll;
 180 };
 181
 182 struct stm32_i2c_priv {
 183         struct stm32_i2c_regs *regs;
 184         struct clk clk;
 185         struct stm32_i2c_setup *setup;
 186         int speed;
 187 };
 188
 189 static const struct stm32_i2c_spec i2c_specs[] = {
 190         [IC_SPEED_MODE_STANDARD] = {
 191                 .rate = I2C_SPEED_STANDARD_RATE,
 192                 .rate_min = 8000,
 193                 .rate_max = 120000,
 194                 .fall_max = 300,
 195                 .rise_max = 1000,
 196                 .hddat_min = 0,
 197                 .vddat_max = 3450,
 198                 .sudat_min = 250,
 199                 .l_min = 4700,
 200                 .h_min = 4000,
 201         },
 202         [IC_SPEED_MODE_FAST] = {
 203                 .rate = I2C_SPEED_FAST_RATE,
 204                 .rate_min = 320000,
 205                 .rate_max = 480000,
 206                 .fall_max = 300,
 207                 .rise_max = 300,
 208                 .hddat_min = 0,
 209                 .vddat_max = 900,
 210                 .sudat_min = 100,
 211                 .l_min = 1300,
 212                 .h_min = 600,
 213         },
 214         [IC_SPEED_MODE_FAST_PLUS] = {
 215                 .rate = I2C_SPEED_FAST_PLUS_RATE,
 216                 .rate_min = 800000,
 217                 .rate_max = 1200000,
 218                 .fall_max = 100,
 219                 .rise_max = 120,
 220                 .hddat_min = 0,
 221                 .vddat_max = 450,
 222                 .sudat_min = 50,
 223                 .l_min = 500,
 224                 .h_min = 260,
 225         },
 226 };
 227
 228 static const struct stm32_i2c_setup stm32f7_setup = {
 229         .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
 230         .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
 231         .dnf = STM32_I2C_DNF_DEFAULT,
 232         .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
 233 };
 234
 235 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
 236 {
 237         struct stm32_i2c_regs *regs = i2c_priv->regs;
 238         u32 status = readl(&regs->isr);
 239
 240         if (status & STM32_I2C_ISR_BUSY)
 241                 return -EBUSY;
 242
 243         return 0;
 244 }
 245
 246 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
 247                                     struct i2c_msg *msg, bool stop)
 248 {
 249         struct stm32_i2c_regs *regs = i2c_priv->regs;
 250         u32 cr2 = readl(&regs->cr2);
 251
 252         /* Set transfer direction */
 253         cr2 &= ~STM32_I2C_CR2_RD_WRN;
 254         if (msg->flags & I2C_M_RD)
 255                 cr2 |= STM32_I2C_CR2_RD_WRN;
 256
 257         /* Set slave address */
 258         cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
 259         if (msg->flags & I2C_M_TEN) {
 260                 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
 261                 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
 262                 cr2 |= STM32_I2C_CR2_ADD10;
 263         } else {
 264                 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
 265                 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
 266         }
 267
 268         /* Set nb bytes to transfer and reload or autoend bits */
 269         cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
 270                  STM32_I2C_CR2_AUTOEND);
 271         if (msg->len > STM32_I2C_MAX_LEN) {
 272                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 273                 cr2 |= STM32_I2C_CR2_RELOAD;
 274         } else {
 275                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 276         }
 277
 278         /* Write configurations register */
 279         writel(cr2, &regs->cr2);
 280
 281         /* START/ReSTART generation */
 282         setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
 283 }
 284
 285 /*
 286  * RELOAD mode must be selected if total number of data bytes to be
 287  * sent is greater than MAX_LEN
 288  */
 289
 290 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
 291                                     struct i2c_msg *msg, bool stop)
 292 {
 293         struct stm32_i2c_regs *regs = i2c_priv->regs;
 294         u32 cr2 = readl(&regs->cr2);
 295
 296         cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
 297
 298         if (msg->len > STM32_I2C_MAX_LEN) {
 299                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 300         } else {
 301                 cr2 &= ~STM32_I2C_CR2_RELOAD;
 302                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 303         }
 304
 305         writel(cr2, &regs->cr2);
 306 }
 307
 308 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
 309                                 u32 flags, u32 *status)
 310 {
 311         struct stm32_i2c_regs *regs = i2c_priv->regs;
 312         u32 time_start = get_timer(0);
 313
 314         *status = readl(&regs->isr);
 315         while (!(*status & flags)) {
 316                 if (get_timer(time_start) > CONFIG_SYS_HZ) {
 317                         debug("%s: i2c timeout\n", __func__);
 318                         return -ETIMEDOUT;
 319                 }
 320
 321                 *status = readl(&regs->isr);
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
 328 {
 329         struct stm32_i2c_regs *regs = i2c_priv->regs;
 330         u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
 331                    STM32_I2C_ISR_STOPF;
 332         u32 status;
 333         int ret;
 334
 335         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 336         if (ret)
 337                 return ret;
 338
 339         if (status & STM32_I2C_ISR_BERR) {
 340                 debug("%s: Bus error\n", __func__);
 341
 342                 /* Clear BERR flag */
 343                 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
 344
 345                 return -EIO;
 346         }
 347
 348         if (status & STM32_I2C_ISR_ARLO) {
 349                 debug("%s: Arbitration lost\n", __func__);
 350
 351                 /* Clear ARLO flag */
 352                 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
 353
 354                 return -EAGAIN;
 355         }
 356
 357         if (status & STM32_I2C_ISR_NACKF) {
 358                 debug("%s: Receive NACK\n", __func__);
 359
 360                 /* Clear NACK flag */
 361                 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
 362
 363                 /* Wait until STOPF flag is set */
 364                 mask = STM32_I2C_ISR_STOPF;
 365                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 366                 if (ret)
 367                         return ret;
 368
 369                 ret = -EIO;
 370         }
 371
 372         if (status & STM32_I2C_ISR_STOPF) {
 373                 /* Clear STOP flag */
 374                 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
 375
 376                 /* Clear control register 2 */
 377                 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
 378         }
 379
 380         return ret;
 381 }
 382
 383 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
 384                                   struct i2c_msg *msg, bool stop)
 385 {
 386         struct stm32_i2c_regs *regs = i2c_priv->regs;
 387         u32 status;
 388         u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 389                    STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 390         int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 391                           STM32_I2C_MAX_LEN : msg->len;
 392         int ret = 0;
 393
 394         /* Add errors */
 395         mask |= STM32_I2C_ISR_ERRORS;
 396
 397         stm32_i2c_message_start(i2c_priv, msg, stop);
 398
 399         while (msg->len) {
 400                 /*
 401                  * Wait until TXIS/NACKF/BERR/ARLO flags or
 402                  * RXNE/BERR/ARLO flags are set
 403                  */
 404                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 405                 if (ret)
 406                         break;
 407
 408                 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
 409                         break;
 410
 411                 if (status & STM32_I2C_ISR_RXNE) {
 412                         *msg->buf++ = readb(&regs->rxdr);
 413                         msg->len--;
 414                         bytes_to_rw--;
 415                 }
 416
 417                 if (status & STM32_I2C_ISR_TXIS) {
 418                         writeb(*msg->buf++, &regs->txdr);
 419                         msg->len--;
 420                         bytes_to_rw--;
 421                 }
 422
 423                 if (!bytes_to_rw && msg->len) {
 424                         /* Wait until TCR flag is set */
 425                         mask = STM32_I2C_ISR_TCR;
 426                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 427                         if (ret)
 428                                 break;
 429
 430                         bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 431                                       STM32_I2C_MAX_LEN : msg->len;
 432                         mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 433                                STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 434
 435                         stm32_i2c_handle_reload(i2c_priv, msg, stop);
 436                 } else if (!bytes_to_rw) {
 437                         /* Wait until TC flag is set */
 438                         mask = STM32_I2C_ISR_TC;
 439                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 440                         if (ret)
 441                                 break;
 442
 443                         if (!stop)
 444                                 /* Message sent, new message has to be sent */
 445                                 return 0;
 446                 }
 447         }
 448
 449         /* End of transfer, send stop condition */
 450         mask = STM32_I2C_CR2_STOP;
 451         setbits_le32(&regs->cr2, mask);
 452
 453         return stm32_i2c_check_end_of_message(i2c_priv);
 454 }
 455
 456 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 457                           int nmsgs)
 458 {
 459         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 460         int ret;
 461
 462         ret = stm32_i2c_check_device_busy(i2c_priv);
 463         if (ret)
 464                 return ret;
 465
 466         for (; nmsgs > 0; nmsgs--, msg++) {
 467                 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
 468                 if (ret)
 469                         return ret;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
 476                                        struct list_head *solutions)
 477 {
 478         struct stm32_i2c_timings *v;
 479         u32 p_prev = STM32_PRESC_MAX;
 480         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 481                                        setup->clock_src);
 482         u32 af_delay_min, af_delay_max;
 483         u16 p, l, a;
 484         int sdadel_min, sdadel_max, scldel_min;
 485         int ret = 0;
 486
 487         af_delay_min = setup->analog_filter ?
 488                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 489         af_delay_max = setup->analog_filter ?
 490                        STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
 491
 492         sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
 493                      af_delay_min - (setup->dnf + 3) * i2cclk;
 494
 495         sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
 496                      af_delay_max - (setup->dnf + 4) * i2cclk;
 497
 498         scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
 499
 500         if (sdadel_min < 0)
 501                 sdadel_min = 0;
 502         if (sdadel_max < 0)
 503                 sdadel_max = 0;
 504
 505         debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
 506               sdadel_min, sdadel_max, scldel_min);
 507
 508         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 509         for (p = 0; p < STM32_PRESC_MAX; p++) {
 510                 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
 511                         int scldel = (l + 1) * (p + 1) * i2cclk;
 512
 513                         if (scldel < scldel_min)
 514                                 continue;
 515
 516                         for (a = 0; a < STM32_SDADEL_MAX; a++) {
 517                                 int sdadel = (a * (p + 1) + 1) * i2cclk;
 518
 519                                 if (((sdadel >= sdadel_min) &&
 520                                      (sdadel <= sdadel_max)) &&
 521                                     (p != p_prev)) {
 522                                         v = calloc(1, sizeof(*v));
 523                                         if (!v)
 524                                                 return -ENOMEM;
 525
 526                                         v->presc = p;
 527                                         v->scldel = l;
 528                                         v->sdadel = a;
 529                                         p_prev = p;
 530
 531                                         list_add_tail(&v->node, solutions);
 532                                         break;
 533                                 }
 534                         }
 535
 536                         if (p_prev == p)
 537                                 break;
 538                 }
 539         }
 540
 541         if (list_empty(solutions)) {
 542                 pr_err("%s: no Prescaler solution\n", __func__);
 543                 ret = -EPERM;
 544         }
 545
 546         return ret;
 547 }
 548
 549 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
 550                                      struct list_head *solutions,
 551                                      struct stm32_i2c_timings *s)
 552 {
 553         struct stm32_i2c_timings *v;
 554         u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 555                                        setup->speed_freq);
 556         u32 clk_error_prev = i2cbus;
 557         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 558                                        setup->clock_src);
 559         u32 clk_min, clk_max;
 560         u32 af_delay_min;
 561         u32 dnf_delay;
 562         u32 tsync;
 563         u16 l, h;
 564         bool sol_found = false;
 565         int ret = 0;
 566
 567         af_delay_min = setup->analog_filter ?
 568                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 569         dnf_delay = setup->dnf * i2cclk;
 570
 571         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 572         clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
 573         clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
 574
 575         /*
 576          * Among Prescaler possibilities discovered above figures out SCL Low
 577          * and High Period. Provided:
 578          * - SCL Low Period has to be higher than Low Period of the SCL Clock
 579          *   defined by I2C Specification. I2C Clock has to be lower than
 580          *   (SCL Low Period - Analog/Digital filters) / 4.
 581          * - SCL High Period has to be lower than High Period of the SCL Clock
 582          *   defined by I2C Specification
 583          * - I2C Clock has to be lower than SCL High Period
 584          */
 585         list_for_each_entry(v, solutions, node) {
 586                 u32 prescaler = (v->presc + 1) * i2cclk;
 587
 588                 for (l = 0; l < STM32_SCLL_MAX; l++) {
 589                         u32 tscl_l = (l + 1) * prescaler + tsync;
 590
 591                         if ((tscl_l < i2c_specs[setup->speed].l_min) ||
 592                             (i2cclk >=
 593                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 594                                 continue;
 595                         }
 596
 597                         for (h = 0; h < STM32_SCLH_MAX; h++) {
 598                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 599                                 u32 tscl = tscl_l + tscl_h +
 600                                            setup->rise_time + setup->fall_time;
 601
 602                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 603                                     (tscl_h >= i2c_specs[setup->speed].h_min) &&
 604                                     (i2cclk < tscl_h)) {
 605                                         u32 clk_error;
 606
 607                                         if (tscl > i2cbus)
 608                                                 clk_error = tscl - i2cbus;
 609                                         else
 610                                                 clk_error = i2cbus - tscl;
 611
 612                                         if (clk_error < clk_error_prev) {
 613                                                 clk_error_prev = clk_error;
 614                                                 v->scll = l;
 615                                                 v->sclh = h;
 616                                                 sol_found = true;
 617                                                 memcpy(s, v, sizeof(*s));
 618                                         }
 619                                 }
 620                         }
 621                 }
 622         }
 623
 624         if (!sol_found) {
 625                 pr_err("%s: no solution at all\n", __func__);
 626                 ret = -EPERM;
 627         }
 628
 629         return ret;
 630 }
 631
 632 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
 633                                     struct stm32_i2c_setup *setup,
 634                                     struct stm32_i2c_timings *output)
 635 {
 636         struct stm32_i2c_timings *v, *_v;
 637         struct list_head solutions;
 638         int ret;
 639
 640         if (setup->speed >= ARRAY_SIZE(i2c_specs)) {
 641                 pr_err("%s: speed out of bound {%d/%d}\n", __func__,
 642                        setup->speed, ARRAY_SIZE(i2c_specs) - 1);
 643                 return -EINVAL;
 644         }
 645
 646         if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
 647             (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
 648                 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 649                        __func__,
 650                        setup->rise_time, i2c_specs[setup->speed].rise_max,
 651                        setup->fall_time, i2c_specs[setup->speed].fall_max);
 652                 return -EINVAL;
 653         }
 654
 655         if (setup->dnf > STM32_I2C_DNF_MAX) {
 656                 pr_err("%s: DNF out of bound %d/%d\n", __func__,
 657                        setup->dnf, STM32_I2C_DNF_MAX);
 658                 return -EINVAL;
 659         }
 660
 661         if (setup->speed_freq > i2c_specs[setup->speed].rate) {
 662                 pr_err("%s: Freq {%d/%d}\n", __func__,
 663                        setup->speed_freq, i2c_specs[setup->speed].rate);
 664                 return -EINVAL;
 665         }
 666
 667         INIT_LIST_HEAD(&solutions);
 668         ret = stm32_i2c_compute_solutions(setup, &solutions);
 669         if (ret)
 670                 goto exit;
 671
 672         ret = stm32_i2c_choose_solution(setup, &solutions, output);
 673         if (ret)
 674                 goto exit;
 675
 676         debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 677               __func__, output->presc,
 678               output->scldel, output->sdadel,
 679               output->scll, output->sclh);
 680
 681 exit:
 682         /* Release list and memory */
 683         list_for_each_entry_safe(v, _v, &solutions, node) {
 684                 list_del(&v->node);
 685                 free(v);
 686         }
 687
 688         return ret;
 689 }
 690
 691 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
 692                                   struct stm32_i2c_timings *timing)
 693 {
 694         struct stm32_i2c_setup *setup = i2c_priv->setup;
 695         int ret = 0;
 696
 697         setup->speed = i2c_priv->speed;
 698         setup->speed_freq = i2c_specs[setup->speed].rate;
 699         setup->clock_src = clk_get_rate(&i2c_priv->clk);
 700
 701         if (!setup->clock_src) {
 702                 pr_err("%s: clock rate is 0\n", __func__);
 703                 return -EINVAL;
 704         }
 705
 706         do {
 707                 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
 708                 if (ret) {
 709                         debug("%s: failed to compute I2C timings.\n",
 710                               __func__);
 711                         if (i2c_priv->speed > IC_SPEED_MODE_STANDARD) {
 712                                 i2c_priv->speed--;
 713                                 setup->speed = i2c_priv->speed;
 714                                 setup->speed_freq =
 715                                         i2c_specs[setup->speed].rate;
 716                                 debug("%s: downgrade I2C Speed Freq to (%i)\n",
 717                                       __func__, i2c_specs[setup->speed].rate);
 718                         } else {
 719                                 break;
 720                         }
 721                 }
 722         } while (ret);
 723
 724         if (ret) {
 725                 pr_err("%s: impossible to compute I2C timings.\n", __func__);
 726                 return ret;
 727         }
 728
 729         debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__,
 730               setup->speed, setup->speed_freq, setup->clock_src);
 731         debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
 732               setup->rise_time, setup->fall_time);
 733         debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
 734               setup->analog_filter ? "On" : "Off", setup->dnf);
 735
 736         return 0;
 737 }
 738
 739 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
 740 {
 741         struct stm32_i2c_regs *regs = i2c_priv->regs;
 742         struct stm32_i2c_timings t;
 743         int ret;
 744         u32 timing = 0;
 745
 746         ret = stm32_i2c_setup_timing(i2c_priv, &t);
 747         if (ret)
 748                 return ret;
 749
 750         /* Disable I2C */
 751         clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 752
 753         /* Timing settings */
 754         timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
 755         timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
 756         timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
 757         timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
 758         timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
 759         writel(timing, &regs->timingr);
 760
 761         /* Enable I2C */
 762         if (i2c_priv->setup->analog_filter)
 763                 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 764         else
 765                 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 766         setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 767
 768         return 0;
 769 }
 770
 771 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 772 {
 773         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 774
 775         switch (speed) {
 776         case I2C_SPEED_STANDARD_RATE:
 777                 i2c_priv->speed = IC_SPEED_MODE_STANDARD;
 778                 break;
 779         case I2C_SPEED_FAST_RATE:
 780                 i2c_priv->speed = IC_SPEED_MODE_FAST;
 781                 break;
 782         case I2C_SPEED_FAST_PLUS_RATE:
 783                 i2c_priv->speed = IC_SPEED_MODE_FAST_PLUS;
 784                 break;
 785         default:
 786                 debug("%s: Speed %d not supported\n", __func__, speed);
 787                 return -EINVAL;
 788         }
 789
 790         return stm32_i2c_hw_config(i2c_priv);
 791 }
 792
 793 static int stm32_i2c_probe(struct udevice *dev)
 794 {
 795         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 796         struct reset_ctl reset_ctl;
 797         fdt_addr_t addr;
 798         int ret;
 799
 800         addr = dev_read_addr(dev);
 801         if (addr == FDT_ADDR_T_NONE)
 802                 return -EINVAL;
 803
 804         i2c_priv->regs = (struct stm32_i2c_regs *)addr;
 805
 806         ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
 807         if (ret)
 808                 return ret;
 809
 810         ret = clk_enable(&i2c_priv->clk);
 811         if (ret)
 812                 goto clk_free;
 813
 814         ret = reset_get_by_index(dev, 0, &reset_ctl);
 815         if (ret)
 816                 goto clk_disable;
 817
 818         reset_assert(&reset_ctl);
 819         udelay(2);
 820         reset_deassert(&reset_ctl);
 821
 822         return 0;
 823
 824 clk_disable:
 825         clk_disable(&i2c_priv->clk);
 826 clk_free:
 827         clk_free(&i2c_priv->clk);
 828
 829         return ret;
 830 }
 831
 832 static int stm32_ofdata_to_platdata(struct udevice *dev)
 833 {
 834         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 835         u32 rise_time, fall_time;
 836
 837         i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
 838         if (!i2c_priv->setup)
 839                 return -EINVAL;
 840
 841         rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
 842         if (rise_time)
 843                 i2c_priv->setup->rise_time = rise_time;
 844
 845         fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
 846         if (fall_time)
 847                 i2c_priv->setup->fall_time = fall_time;
 848
 849         return 0;
 850 }
 851
 852 static const struct dm_i2c_ops stm32_i2c_ops = {
 853         .xfer = stm32_i2c_xfer,
 854         .set_bus_speed = stm32_i2c_set_bus_speed,
 855 };
 856
 857 static const struct udevice_id stm32_i2c_of_match[] = {
 858         { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
 859         {}
 860 };
 861
 862 U_BOOT_DRIVER(stm32f7_i2c) = {
 863         .name = "stm32f7-i2c",
 864         .id = UCLASS_I2C,
 865         .of_match = stm32_i2c_of_match,
 866         .ofdata_to_platdata = stm32_ofdata_to_platdata,
 867         .probe = stm32_i2c_probe,
 868         .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
 869         .ops = &stm32_i2c_ops,
 870 };