drivers/i2c/stm32f7_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 STMicroelectronics
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_I2C
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <i2c.h>
  12 #include <log.h>
  13 #include <regmap.h>
  14 #include <reset.h>
  15 #include <syscon.h>
  16 #include <dm/device.h>
  17 #include <dm/device_compat.h>
  18 #include <linux/bitops.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/io.h>
  22
  23 /* STM32 I2C registers */
  24 struct stm32_i2c_regs {
  25         u32 cr1;        /* I2C control register 1 */
  26         u32 cr2;        /* I2C control register 2 */
  27         u32 oar1;       /* I2C own address 1 register */
  28         u32 oar2;       /* I2C own address 2 register */
  29         u32 timingr;    /* I2C timing register */
  30         u32 timeoutr;   /* I2C timeout register */
  31         u32 isr;        /* I2C interrupt and status register */
  32         u32 icr;        /* I2C interrupt clear register */
  33         u32 pecr;       /* I2C packet error checking register */
  34         u32 rxdr;       /* I2C receive data register */
  35         u32 txdr;       /* I2C transmit data register */
  36 };
  37
  38 #define STM32_I2C_CR1                           0x00
  39 #define STM32_I2C_CR2                           0x04
  40 #define STM32_I2C_TIMINGR                       0x10
  41 #define STM32_I2C_ISR                           0x18
  42 #define STM32_I2C_ICR                           0x1C
  43 #define STM32_I2C_RXDR                          0x24
  44 #define STM32_I2C_TXDR                          0x28
  45
  46 /* STM32 I2C control 1 */
  47 #define STM32_I2C_CR1_ANFOFF                    BIT(12)
  48 #define STM32_I2C_CR1_DNF_MASK                  GENMASK(11, 8)
  49 #define STM32_I2C_CR1_DNF(n)                    (((n) & 0xf) << 8)
  50 #define STM32_I2C_CR1_ERRIE                     BIT(7)
  51 #define STM32_I2C_CR1_TCIE                      BIT(6)
  52 #define STM32_I2C_CR1_STOPIE                    BIT(5)
  53 #define STM32_I2C_CR1_NACKIE                    BIT(4)
  54 #define STM32_I2C_CR1_ADDRIE                    BIT(3)
  55 #define STM32_I2C_CR1_RXIE                      BIT(2)
  56 #define STM32_I2C_CR1_TXIE                      BIT(1)
  57 #define STM32_I2C_CR1_PE                        BIT(0)
  58
  59 /* STM32 I2C control 2 */
  60 #define STM32_I2C_CR2_AUTOEND                   BIT(25)
  61 #define STM32_I2C_CR2_RELOAD                    BIT(24)
  62 #define STM32_I2C_CR2_NBYTES_MASK               GENMASK(23, 16)
  63 #define STM32_I2C_CR2_NBYTES(n)                 ((n & 0xff) << 16)
  64 #define STM32_I2C_CR2_NACK                      BIT(15)
  65 #define STM32_I2C_CR2_STOP                      BIT(14)
  66 #define STM32_I2C_CR2_START                     BIT(13)
  67 #define STM32_I2C_CR2_HEAD10R                   BIT(12)
  68 #define STM32_I2C_CR2_ADD10                     BIT(11)
  69 #define STM32_I2C_CR2_RD_WRN                    BIT(10)
  70 #define STM32_I2C_CR2_SADD10_MASK               GENMASK(9, 0)
  71 #define STM32_I2C_CR2_SADD10(n)                 (n & STM32_I2C_CR2_SADD10_MASK)
  72 #define STM32_I2C_CR2_SADD7_MASK                GENMASK(7, 1)
  73 #define STM32_I2C_CR2_SADD7(n)                  ((n & 0x7f) << 1)
  74 #define STM32_I2C_CR2_RESET_MASK                (STM32_I2C_CR2_HEAD10R \
  75                                                 | STM32_I2C_CR2_NBYTES_MASK \
  76                                                 | STM32_I2C_CR2_SADD7_MASK \
  77                                                 | STM32_I2C_CR2_RELOAD \
  78                                                 | STM32_I2C_CR2_RD_WRN)
  79
  80 /* STM32 I2C Interrupt Status */
  81 #define STM32_I2C_ISR_BUSY                      BIT(15)
  82 #define STM32_I2C_ISR_ARLO                      BIT(9)
  83 #define STM32_I2C_ISR_BERR                      BIT(8)
  84 #define STM32_I2C_ISR_TCR                       BIT(7)
  85 #define STM32_I2C_ISR_TC                        BIT(6)
  86 #define STM32_I2C_ISR_STOPF                     BIT(5)
  87 #define STM32_I2C_ISR_NACKF                     BIT(4)
  88 #define STM32_I2C_ISR_ADDR                      BIT(3)
  89 #define STM32_I2C_ISR_RXNE                      BIT(2)
  90 #define STM32_I2C_ISR_TXIS                      BIT(1)
  91 #define STM32_I2C_ISR_TXE                       BIT(0)
  92 #define STM32_I2C_ISR_ERRORS                    (STM32_I2C_ISR_BERR \
  93                                                 | STM32_I2C_ISR_ARLO)
  94
  95 /* STM32 I2C Interrupt Clear */
  96 #define STM32_I2C_ICR_ARLOCF                    BIT(9)
  97 #define STM32_I2C_ICR_BERRCF                    BIT(8)
  98 #define STM32_I2C_ICR_STOPCF                    BIT(5)
  99 #define STM32_I2C_ICR_NACKCF                    BIT(4)
 100
 101 /* STM32 I2C Timing */
 102 #define STM32_I2C_TIMINGR_PRESC(n)              ((n & 0xf) << 28)
 103 #define STM32_I2C_TIMINGR_SCLDEL(n)             ((n & 0xf) << 20)
 104 #define STM32_I2C_TIMINGR_SDADEL(n)             ((n & 0xf) << 16)
 105 #define STM32_I2C_TIMINGR_SCLH(n)               ((n & 0xff) << 8)
 106 #define STM32_I2C_TIMINGR_SCLL(n)               (n & 0xff)
 107
 108 #define STM32_I2C_MAX_LEN                       0xff
 109
 110 #define STM32_I2C_DNF_MAX                       15
 111
 112 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN       50      /* ns */
 113 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX       260     /* ns */
 114
 115 #define STM32_I2C_RISE_TIME_DEFAULT             25      /* ns */
 116 #define STM32_I2C_FALL_TIME_DEFAULT             10      /* ns */
 117
 118 #define STM32_PRESC_MAX                         BIT(4)
 119 #define STM32_SCLDEL_MAX                        BIT(4)
 120 #define STM32_SDADEL_MAX                        BIT(4)
 121 #define STM32_SCLH_MAX                          BIT(8)
 122 #define STM32_SCLL_MAX                          BIT(8)
 123
 124 #define STM32_NSEC_PER_SEC                      1000000000L
 125
 126 /**
 127  * struct stm32_i2c_spec - private i2c specification timing
 128  * @rate: I2C bus speed (Hz)
 129  * @rate_min: 80% of I2C bus speed (Hz)
 130  * @rate_max: 120% of I2C bus speed (Hz)
 131  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 132  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 133  * @hddat_min: Min data hold time (ns)
 134  * @vddat_max: Max data valid time (ns)
 135  * @sudat_min: Min data setup time (ns)
 136  * @l_min: Min low period of the SCL clock (ns)
 137  * @h_min: Min high period of the SCL clock (ns)
 138  */
 139
 140 struct stm32_i2c_spec {
 141         u32 rate;
 142         u32 rate_min;
 143         u32 rate_max;
 144         u32 fall_max;
 145         u32 rise_max;
 146         u32 hddat_min;
 147         u32 vddat_max;
 148         u32 sudat_min;
 149         u32 l_min;
 150         u32 h_min;
 151 };
 152
 153 /**
 154  * struct stm32_i2c_setup - private I2C timing setup parameters
 155  * @speed_freq: I2C speed frequency  (Hz)
 156  * @clock_src: I2C clock source frequency (Hz)
 157  * @rise_time: Rise time (ns)
 158  * @fall_time: Fall time (ns)
 159  * @dnf: value of digital filter to apply
 160  * @analog_filter: Analog filter delay (On/Off)
 161  */
 162 struct stm32_i2c_setup {
 163         u32 speed_freq;
 164         u32 clock_src;
 165         u32 rise_time;
 166         u32 fall_time;
 167         u8 dnf;
 168         bool analog_filter;
 169 };
 170
 171 /**
 172  * struct stm32_i2c_data - driver data for I2C configuration by compatible
 173  * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
 174  */
 175 struct stm32_i2c_data {
 176         u32 fmp_clr_offset;
 177 };
 178
 179 /**
 180  * struct stm32_i2c_timings - private I2C output parameters
 181  * @prec: Prescaler value
 182  * @scldel: Data setup time
 183  * @sdadel: Data hold time
 184  * @sclh: SCL high period (master mode)
 185  * @sclh: SCL low period (master mode)
 186  */
 187 struct stm32_i2c_timings {
 188         struct list_head node;
 189         u8 presc;
 190         u8 scldel;
 191         u8 sdadel;
 192         u8 sclh;
 193         u8 scll;
 194 };
 195
 196 /**
 197  * struct stm32_i2c_priv - private data of the controller
 198  * @regs: I2C registers address
 199  * @clk: hw i2c clock
 200  * @setup: I2C timing setup parameters
 201  * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
 202  * @regmap: holds SYSCFG phandle for Fast Mode Plus bit
 203  * @regmap_sreg: register address for setting Fast Mode Plus bits
 204  * @regmap_creg: register address for clearing Fast Mode Plus bits
 205  * @regmap_mask: mask for Fast Mode Plus bits
 206  * @dnf_dt: value of digital filter requested via dt
 207  */
 208 struct stm32_i2c_priv {
 209         struct stm32_i2c_regs *regs;
 210         struct clk clk;
 211         struct stm32_i2c_setup setup;
 212         u32 speed;
 213         struct regmap *regmap;
 214         u32 regmap_sreg;
 215         u32 regmap_creg;
 216         u32 regmap_mask;
 217         u32 dnf_dt;
 218 };
 219
 220 static const struct stm32_i2c_spec i2c_specs[] = {
 221         /* Standard speed - 100 KHz */
 222         [IC_SPEED_MODE_STANDARD] = {
 223                 .rate = I2C_SPEED_STANDARD_RATE,
 224                 .rate_min = 8000,
 225                 .rate_max = 120000,
 226                 .fall_max = 300,
 227                 .rise_max = 1000,
 228                 .hddat_min = 0,
 229                 .vddat_max = 3450,
 230                 .sudat_min = 250,
 231                 .l_min = 4700,
 232                 .h_min = 4000,
 233         },
 234         /* Fast speed - 400 KHz */
 235         [IC_SPEED_MODE_FAST] = {
 236                 .rate = I2C_SPEED_FAST_RATE,
 237                 .rate_min = 320000,
 238                 .rate_max = 480000,
 239                 .fall_max = 300,
 240                 .rise_max = 300,
 241                 .hddat_min = 0,
 242                 .vddat_max = 900,
 243                 .sudat_min = 100,
 244                 .l_min = 1300,
 245                 .h_min = 600,
 246         },
 247         /* Fast Plus Speed - 1 MHz */
 248         [IC_SPEED_MODE_FAST_PLUS] = {
 249                 .rate = I2C_SPEED_FAST_PLUS_RATE,
 250                 .rate_min = 800000,
 251                 .rate_max = 1200000,
 252                 .fall_max = 100,
 253                 .rise_max = 120,
 254                 .hddat_min = 0,
 255                 .vddat_max = 450,
 256                 .sudat_min = 50,
 257                 .l_min = 500,
 258                 .h_min = 260,
 259         },
 260 };
 261
 262 static const struct stm32_i2c_data stm32f7_data = {
 263         .fmp_clr_offset = 0x00,
 264 };
 265
 266 static const struct stm32_i2c_data stm32mp15_data = {
 267         .fmp_clr_offset = 0x40,
 268 };
 269
 270 static const struct stm32_i2c_data stm32mp13_data = {
 271         .fmp_clr_offset = 0x4,
 272 };
 273
 274 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
 275 {
 276         struct stm32_i2c_regs *regs = i2c_priv->regs;
 277         u32 status = readl(&regs->isr);
 278
 279         if (status & STM32_I2C_ISR_BUSY)
 280                 return -EBUSY;
 281
 282         return 0;
 283 }
 284
 285 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
 286                                     struct i2c_msg *msg, bool stop)
 287 {
 288         struct stm32_i2c_regs *regs = i2c_priv->regs;
 289         u32 cr2 = readl(&regs->cr2);
 290
 291         /* Set transfer direction */
 292         cr2 &= ~STM32_I2C_CR2_RD_WRN;
 293         if (msg->flags & I2C_M_RD)
 294                 cr2 |= STM32_I2C_CR2_RD_WRN;
 295
 296         /* Set slave address */
 297         cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
 298         if (msg->flags & I2C_M_TEN) {
 299                 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
 300                 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
 301                 cr2 |= STM32_I2C_CR2_ADD10;
 302         } else {
 303                 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
 304                 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
 305         }
 306
 307         /* Set nb bytes to transfer and reload or autoend bits */
 308         cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
 309                  STM32_I2C_CR2_AUTOEND);
 310         if (msg->len > STM32_I2C_MAX_LEN) {
 311                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 312                 cr2 |= STM32_I2C_CR2_RELOAD;
 313         } else {
 314                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 315         }
 316
 317         /* Write configurations register */
 318         writel(cr2, &regs->cr2);
 319
 320         /* START/ReSTART generation */
 321         setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
 322 }
 323
 324 /*
 325  * RELOAD mode must be selected if total number of data bytes to be
 326  * sent is greater than MAX_LEN
 327  */
 328
 329 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
 330                                     struct i2c_msg *msg, bool stop)
 331 {
 332         struct stm32_i2c_regs *regs = i2c_priv->regs;
 333         u32 cr2 = readl(&regs->cr2);
 334
 335         cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
 336
 337         if (msg->len > STM32_I2C_MAX_LEN) {
 338                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 339         } else {
 340                 cr2 &= ~STM32_I2C_CR2_RELOAD;
 341                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 342         }
 343
 344         writel(cr2, &regs->cr2);
 345 }
 346
 347 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
 348                                 u32 flags, u32 *status)
 349 {
 350         struct stm32_i2c_regs *regs = i2c_priv->regs;
 351         u32 time_start = get_timer(0);
 352
 353         *status = readl(&regs->isr);
 354         while (!(*status & flags)) {
 355                 if (get_timer(time_start) > CONFIG_SYS_HZ) {
 356                         log_debug("i2c timeout\n");
 357                         return -ETIMEDOUT;
 358                 }
 359
 360                 *status = readl(&regs->isr);
 361         }
 362
 363         return 0;
 364 }
 365
 366 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
 367 {
 368         struct stm32_i2c_regs *regs = i2c_priv->regs;
 369         u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
 370                    STM32_I2C_ISR_STOPF;
 371         u32 status;
 372         int ret;
 373
 374         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 375         if (ret)
 376                 return ret;
 377
 378         if (status & STM32_I2C_ISR_BERR) {
 379                 log_debug("Bus error\n");
 380
 381                 /* Clear BERR flag */
 382                 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
 383
 384                 return -EIO;
 385         }
 386
 387         if (status & STM32_I2C_ISR_ARLO) {
 388                 log_debug("Arbitration lost\n");
 389
 390                 /* Clear ARLO flag */
 391                 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
 392
 393                 return -EAGAIN;
 394         }
 395
 396         if (status & STM32_I2C_ISR_NACKF) {
 397                 log_debug("Receive NACK\n");
 398
 399                 /* Clear NACK flag */
 400                 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
 401
 402                 /* Wait until STOPF flag is set */
 403                 mask = STM32_I2C_ISR_STOPF;
 404                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 405                 if (ret)
 406                         return ret;
 407
 408                 ret = -EIO;
 409         }
 410
 411         if (status & STM32_I2C_ISR_STOPF) {
 412                 /* Clear STOP flag */
 413                 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
 414
 415                 /* Clear control register 2 */
 416                 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
 417         }
 418
 419         return ret;
 420 }
 421
 422 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
 423                                   struct i2c_msg *msg, bool stop)
 424 {
 425         struct stm32_i2c_regs *regs = i2c_priv->regs;
 426         u32 status;
 427         u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 428                    STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 429         int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 430                           STM32_I2C_MAX_LEN : msg->len;
 431         int ret = 0;
 432
 433         /* Add errors */
 434         mask |= STM32_I2C_ISR_ERRORS;
 435
 436         stm32_i2c_message_start(i2c_priv, msg, stop);
 437
 438         while (msg->len) {
 439                 /*
 440                  * Wait until TXIS/NACKF/BERR/ARLO flags or
 441                  * RXNE/BERR/ARLO flags are set
 442                  */
 443                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 444                 if (ret)
 445                         break;
 446
 447                 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
 448                         break;
 449
 450                 if (status & STM32_I2C_ISR_RXNE) {
 451                         *msg->buf++ = readb(&regs->rxdr);
 452                         msg->len--;
 453                         bytes_to_rw--;
 454                 }
 455
 456                 if (status & STM32_I2C_ISR_TXIS) {
 457                         writeb(*msg->buf++, &regs->txdr);
 458                         msg->len--;
 459                         bytes_to_rw--;
 460                 }
 461
 462                 if (!bytes_to_rw && msg->len) {
 463                         /* Wait until TCR flag is set */
 464                         mask = STM32_I2C_ISR_TCR;
 465                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 466                         if (ret)
 467                                 break;
 468
 469                         bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 470                                       STM32_I2C_MAX_LEN : msg->len;
 471                         mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 472                                STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 473
 474                         stm32_i2c_handle_reload(i2c_priv, msg, stop);
 475                 } else if (!bytes_to_rw) {
 476                         /* Wait until TC flag is set */
 477                         mask = STM32_I2C_ISR_TC;
 478                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 479                         if (ret)
 480                                 break;
 481
 482                         if (!stop)
 483                                 /* Message sent, new message has to be sent */
 484                                 return 0;
 485                 }
 486         }
 487
 488         /* End of transfer, send stop condition */
 489         mask = STM32_I2C_CR2_STOP;
 490         setbits_le32(&regs->cr2, mask);
 491
 492         return stm32_i2c_check_end_of_message(i2c_priv);
 493 }
 494
 495 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 496                           int nmsgs)
 497 {
 498         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 499         int ret;
 500
 501         ret = stm32_i2c_check_device_busy(i2c_priv);
 502         if (ret)
 503                 return ret;
 504
 505         for (; nmsgs > 0; nmsgs--, msg++) {
 506                 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
 507                 if (ret)
 508                         return ret;
 509         }
 510
 511         return 0;
 512 }
 513
 514 static int stm32_i2c_compute_solutions(u32 i2cclk,
 515                                        struct stm32_i2c_setup *setup,
 516                                        const struct stm32_i2c_spec *specs,
 517                                        struct list_head *solutions)
 518 {
 519         struct stm32_i2c_timings *v;
 520         u32 p_prev = STM32_PRESC_MAX;
 521         u32 af_delay_min, af_delay_max;
 522         u16 p, l, a;
 523         int sdadel_min, sdadel_max, scldel_min;
 524         int ret = 0;
 525
 526         af_delay_min = setup->analog_filter ?
 527                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 528         af_delay_max = setup->analog_filter ?
 529                        STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
 530
 531         sdadel_min = specs->hddat_min + setup->fall_time -
 532                      af_delay_min - (setup->dnf + 3) * i2cclk;
 533
 534         sdadel_max = specs->vddat_max - setup->rise_time -
 535                      af_delay_max - (setup->dnf + 4) * i2cclk;
 536
 537         scldel_min = setup->rise_time + specs->sudat_min;
 538
 539         if (sdadel_min < 0)
 540                 sdadel_min = 0;
 541         if (sdadel_max < 0)
 542                 sdadel_max = 0;
 543
 544         log_debug("SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 545                   sdadel_min, sdadel_max, scldel_min);
 546
 547         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 548         for (p = 0; p < STM32_PRESC_MAX; p++) {
 549                 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
 550                         int scldel = (l + 1) * (p + 1) * i2cclk;
 551
 552                         if (scldel < scldel_min)
 553                                 continue;
 554
 555                         for (a = 0; a < STM32_SDADEL_MAX; a++) {
 556                                 int sdadel = (a * (p + 1) + 1) * i2cclk;
 557
 558                                 if (((sdadel >= sdadel_min) &&
 559                                      (sdadel <= sdadel_max)) &&
 560                                     (p != p_prev)) {
 561                                         v = calloc(1, sizeof(*v));
 562                                         if (!v)
 563                                                 return -ENOMEM;
 564
 565                                         v->presc = p;
 566                                         v->scldel = l;
 567                                         v->sdadel = a;
 568                                         p_prev = p;
 569
 570                                         list_add_tail(&v->node, solutions);
 571                                         break;
 572                                 }
 573                         }
 574
 575                         if (p_prev == p)
 576                                 break;
 577                 }
 578         }
 579
 580         if (list_empty(solutions)) {
 581                 log_err("no Prescaler solution\n");
 582                 ret = -EPERM;
 583         }
 584
 585         return ret;
 586 }
 587
 588 static int stm32_i2c_choose_solution(u32 i2cclk,
 589                                      struct stm32_i2c_setup *setup,
 590                                      const struct stm32_i2c_spec *specs,
 591                                      struct list_head *solutions,
 592                                      struct stm32_i2c_timings *s)
 593 {
 594         struct stm32_i2c_timings *v;
 595         u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 596                                        setup->speed_freq);
 597         u32 clk_error_prev = i2cbus;
 598         u32 clk_min, clk_max;
 599         u32 af_delay_min;
 600         u32 dnf_delay;
 601         u32 tsync;
 602         u16 l, h;
 603         bool sol_found = false;
 604         int ret = 0;
 605
 606         af_delay_min = setup->analog_filter ?
 607                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 608         dnf_delay = setup->dnf * i2cclk;
 609
 610         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 611         clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
 612         clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
 613
 614         /*
 615          * Among Prescaler possibilities discovered above figures out SCL Low
 616          * and High Period. Provided:
 617          * - SCL Low Period has to be higher than Low Period of the SCL Clock
 618          *   defined by I2C Specification. I2C Clock has to be lower than
 619          *   (SCL Low Period - Analog/Digital filters) / 4.
 620          * - SCL High Period has to be lower than High Period of the SCL Clock
 621          *   defined by I2C Specification
 622          * - I2C Clock has to be lower than SCL High Period
 623          */
 624         list_for_each_entry(v, solutions, node) {
 625                 u32 prescaler = (v->presc + 1) * i2cclk;
 626
 627                 for (l = 0; l < STM32_SCLL_MAX; l++) {
 628                         u32 tscl_l = (l + 1) * prescaler + tsync;
 629
 630                         if (tscl_l < specs->l_min ||
 631                             (i2cclk >=
 632                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 633                                 continue;
 634                         }
 635
 636                         for (h = 0; h < STM32_SCLH_MAX; h++) {
 637                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 638                                 u32 tscl = tscl_l + tscl_h +
 639                                            setup->rise_time + setup->fall_time;
 640
 641                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 642                                     (tscl_h >= specs->h_min) &&
 643                                     (i2cclk < tscl_h)) {
 644                                         u32 clk_error;
 645
 646                                         if (tscl > i2cbus)
 647                                                 clk_error = tscl - i2cbus;
 648                                         else
 649                                                 clk_error = i2cbus - tscl;
 650
 651                                         if (clk_error < clk_error_prev) {
 652                                                 clk_error_prev = clk_error;
 653                                                 v->scll = l;
 654                                                 v->sclh = h;
 655                                                 sol_found = true;
 656                                                 memcpy(s, v, sizeof(*s));
 657                                         }
 658                                 }
 659                         }
 660                 }
 661         }
 662
 663         if (!sol_found) {
 664                 log_err("no solution at all\n");
 665                 ret = -EPERM;
 666         }
 667
 668         return ret;
 669 }
 670
 671 static const struct stm32_i2c_spec *get_specs(u32 rate)
 672 {
 673         unsigned int i;
 674
 675         for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
 676                 if (rate <= i2c_specs[i].rate)
 677                         return &i2c_specs[i];
 678
 679         /* NOT REACHED */
 680         return ERR_PTR(-EINVAL);
 681 }
 682
 683 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
 684                                     struct stm32_i2c_timings *output)
 685 {
 686         struct stm32_i2c_setup *setup = &i2c_priv->setup;
 687         const struct stm32_i2c_spec *specs;
 688         struct stm32_i2c_timings *v, *_v;
 689         struct list_head solutions;
 690         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, setup->clock_src);
 691         int ret;
 692
 693         specs = get_specs(setup->speed_freq);
 694         if (specs == ERR_PTR(-EINVAL)) {
 695                 log_err("speed out of bound {%d}\n",
 696                         setup->speed_freq);
 697                 return -EINVAL;
 698         }
 699
 700         if (setup->rise_time > specs->rise_max ||
 701             setup->fall_time > specs->fall_max) {
 702                 log_err("timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 703                         setup->rise_time, specs->rise_max,
 704                         setup->fall_time, specs->fall_max);
 705                 return -EINVAL;
 706         }
 707
 708         /*  Analog and Digital Filters */
 709         setup->dnf = DIV_ROUND_CLOSEST(i2c_priv->dnf_dt, i2cclk);
 710         if (setup->dnf > STM32_I2C_DNF_MAX) {
 711                 log_err("DNF out of bound %d/%d\n",
 712                         setup->dnf, STM32_I2C_DNF_MAX);
 713                 return -EINVAL;
 714         }
 715
 716         INIT_LIST_HEAD(&solutions);
 717         ret = stm32_i2c_compute_solutions(i2cclk, setup, specs, &solutions);
 718         if (ret)
 719                 goto exit;
 720
 721         ret = stm32_i2c_choose_solution(i2cclk, setup, specs, &solutions, output);
 722         if (ret)
 723                 goto exit;
 724
 725         log_debug("Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 726                   output->presc,
 727                   output->scldel, output->sdadel,
 728                   output->scll, output->sclh);
 729
 730 exit:
 731         /* Release list and memory */
 732         list_for_each_entry_safe(v, _v, &solutions, node) {
 733                 list_del(&v->node);
 734                 free(v);
 735         }
 736
 737         return ret;
 738 }
 739
 740 static u32 get_lower_rate(u32 rate)
 741 {
 742         int i;
 743
 744         for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
 745                 if (rate > i2c_specs[i].rate)
 746                         return i2c_specs[i].rate;
 747
 748         return i2c_specs[0].rate;
 749 }
 750
 751 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
 752                                   struct stm32_i2c_timings *timing)
 753 {
 754         struct stm32_i2c_setup *setup = &i2c_priv->setup;
 755         int ret = 0;
 756
 757         setup->speed_freq = i2c_priv->speed;
 758         setup->clock_src = clk_get_rate(&i2c_priv->clk);
 759
 760         if (!setup->clock_src) {
 761                 log_err("clock rate is 0\n");
 762                 return -EINVAL;
 763         }
 764
 765         do {
 766                 ret = stm32_i2c_compute_timing(i2c_priv, timing);
 767                 if (ret) {
 768                         log_debug("failed to compute I2C timings.\n");
 769                         if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
 770                                 setup->speed_freq =
 771                                         get_lower_rate(setup->speed_freq);
 772                                 log_debug("downgrade I2C Speed Freq to (%i)\n",
 773                                           setup->speed_freq);
 774                         } else {
 775                                 break;
 776                         }
 777                 }
 778         } while (ret);
 779
 780         if (ret) {
 781                 log_err("impossible to compute I2C timings.\n");
 782                 return ret;
 783         }
 784
 785         log_debug("I2C Freq(%i), Clk Source(%i)\n",
 786                   setup->speed_freq, setup->clock_src);
 787         log_debug("I2C Rise(%i) and Fall(%i) Time\n",
 788                   setup->rise_time, setup->fall_time);
 789         log_debug("I2C Analog Filter(%s), DNF(%i)\n",
 790                   setup->analog_filter ? "On" : "Off", setup->dnf);
 791
 792         i2c_priv->speed = setup->speed_freq;
 793
 794         return 0;
 795 }
 796
 797 static int stm32_i2c_write_fm_plus_bits(struct stm32_i2c_priv *i2c_priv)
 798 {
 799         int ret;
 800         bool enable = i2c_priv->speed > I2C_SPEED_FAST_RATE;
 801
 802         /* Optional */
 803         if (IS_ERR_OR_NULL(i2c_priv->regmap))
 804                 return 0;
 805
 806         if (i2c_priv->regmap_sreg == i2c_priv->regmap_creg)
 807                 ret = regmap_update_bits(i2c_priv->regmap,
 808                                          i2c_priv->regmap_sreg,
 809                                          i2c_priv->regmap_mask,
 810                                          enable ? i2c_priv->regmap_mask : 0);
 811         else
 812                 ret = regmap_write(i2c_priv->regmap,
 813                                    enable ? i2c_priv->regmap_sreg :
 814                                             i2c_priv->regmap_creg,
 815                                    i2c_priv->regmap_mask);
 816
 817         return ret;
 818 }
 819
 820 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
 821 {
 822         struct stm32_i2c_regs *regs = i2c_priv->regs;
 823         struct stm32_i2c_timings t;
 824         int ret;
 825         u32 timing = 0;
 826
 827         ret = stm32_i2c_setup_timing(i2c_priv, &t);
 828         if (ret)
 829                 return ret;
 830
 831         /* Disable I2C */
 832         clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 833
 834         /* Setup Fast mode plus if necessary */
 835         ret = stm32_i2c_write_fm_plus_bits(i2c_priv);
 836         if (ret)
 837                 return ret;
 838
 839         /* Timing settings */
 840         timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
 841         timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
 842         timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
 843         timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
 844         timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
 845         writel(timing, &regs->timingr);
 846
 847         /* Enable I2C */
 848         if (i2c_priv->setup.analog_filter)
 849                 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 850         else
 851                 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 852
 853         /* Program the Digital Filter */
 854         clrsetbits_le32(&regs->cr1, STM32_I2C_CR1_DNF_MASK,
 855                         STM32_I2C_CR1_DNF(i2c_priv->setup.dnf));
 856
 857         setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 858
 859         return 0;
 860 }
 861
 862 static int stm32_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 863 {
 864         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 865
 866         if (speed > I2C_SPEED_FAST_PLUS_RATE) {
 867                 dev_dbg(dev, "Speed %d not supported\n", speed);
 868                 return -EINVAL;
 869         }
 870
 871         i2c_priv->speed = speed;
 872
 873         return stm32_i2c_hw_config(i2c_priv);
 874 }
 875
 876 static int stm32_i2c_probe(struct udevice *dev)
 877 {
 878         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 879         struct reset_ctl reset_ctl;
 880         fdt_addr_t addr;
 881         int ret;
 882
 883         addr = dev_read_addr(dev);
 884         if (addr == FDT_ADDR_T_NONE)
 885                 return -EINVAL;
 886
 887         i2c_priv->regs = (struct stm32_i2c_regs *)addr;
 888
 889         ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
 890         if (ret)
 891                 return ret;
 892
 893         ret = clk_enable(&i2c_priv->clk);
 894         if (ret)
 895                 goto clk_free;
 896
 897         ret = reset_get_by_index(dev, 0, &reset_ctl);
 898         if (ret)
 899                 goto clk_disable;
 900
 901         reset_assert(&reset_ctl);
 902         udelay(2);
 903         reset_deassert(&reset_ctl);
 904
 905         return 0;
 906
 907 clk_disable:
 908         clk_disable(&i2c_priv->clk);
 909 clk_free:
 910         clk_free(&i2c_priv->clk);
 911
 912         return ret;
 913 }
 914
 915 static int stm32_of_to_plat(struct udevice *dev)
 916 {
 917         const struct stm32_i2c_data *data;
 918         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 919         u32 rise_time, fall_time;
 920         int ret;
 921
 922         data = (const struct stm32_i2c_data *)dev_get_driver_data(dev);
 923         if (!data)
 924                 return -EINVAL;
 925
 926         rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns",
 927                                          STM32_I2C_RISE_TIME_DEFAULT);
 928
 929         fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns",
 930                                          STM32_I2C_FALL_TIME_DEFAULT);
 931
 932         i2c_priv->dnf_dt = dev_read_u32_default(dev, "i2c-digital-filter-width-ns", 0);
 933         if (!dev_read_bool(dev, "i2c-digital-filter"))
 934                 i2c_priv->dnf_dt = 0;
 935
 936         i2c_priv->setup.analog_filter = dev_read_bool(dev, "i2c-analog-filter");
 937
 938         /* Optional */
 939         i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev,
 940                                                            "st,syscfg-fmp");
 941         if (!IS_ERR(i2c_priv->regmap)) {
 942                 u32 fmp[3];
 943
 944                 ret = dev_read_u32_array(dev, "st,syscfg-fmp", fmp, 3);
 945                 if (ret)
 946                         return ret;
 947
 948                 i2c_priv->regmap_sreg = fmp[1];
 949                 i2c_priv->regmap_creg = fmp[1] + data->fmp_clr_offset;
 950                 i2c_priv->regmap_mask = fmp[2];
 951         }
 952
 953         return 0;
 954 }
 955
 956 static const struct dm_i2c_ops stm32_i2c_ops = {
 957         .xfer = stm32_i2c_xfer,
 958         .set_bus_speed = stm32_i2c_set_bus_speed,
 959 };
 960
 961 static const struct udevice_id stm32_i2c_of_match[] = {
 962         { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data },
 963         { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data },
 964         { .compatible = "st,stm32mp13-i2c", .data = (ulong)&stm32mp13_data },
 965         {}
 966 };
 967
 968 U_BOOT_DRIVER(stm32f7_i2c) = {
 969         .name = "stm32f7-i2c",
 970         .id = UCLASS_I2C,
 971         .of_match = stm32_i2c_of_match,
 972         .of_to_plat = stm32_of_to_plat,
 973         .probe = stm32_i2c_probe,
 974         .priv_auto      = sizeof(struct stm32_i2c_priv),
 975         .ops = &stm32_i2c_ops,
 976 };