1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 STMicroelectronics
12 #include <linux/bitops.h>
13 #include <linux/delay.h>
15 #include <dm/device.h>
16 #include <linux/err.h>
19 /* STM32 I2C registers */
20 struct stm32_i2c_regs {
21 u32 cr1; /* I2C control register 1 */
22 u32 cr2; /* I2C control register 2 */
23 u32 oar1; /* I2C own address 1 register */
24 u32 oar2; /* I2C own address 2 register */
25 u32 timingr; /* I2C timing register */
26 u32 timeoutr; /* I2C timeout register */
27 u32 isr; /* I2C interrupt and status register */
28 u32 icr; /* I2C interrupt clear register */
29 u32 pecr; /* I2C packet error checking register */
30 u32 rxdr; /* I2C receive data register */
31 u32 txdr; /* I2C transmit data register */
34 #define STM32_I2C_CR1 0x00
35 #define STM32_I2C_CR2 0x04
36 #define STM32_I2C_TIMINGR 0x10
37 #define STM32_I2C_ISR 0x18
38 #define STM32_I2C_ICR 0x1C
39 #define STM32_I2C_RXDR 0x24
40 #define STM32_I2C_TXDR 0x28
42 /* STM32 I2C control 1 */
43 #define STM32_I2C_CR1_ANFOFF BIT(12)
44 #define STM32_I2C_CR1_ERRIE BIT(7)
45 #define STM32_I2C_CR1_TCIE BIT(6)
46 #define STM32_I2C_CR1_STOPIE BIT(5)
47 #define STM32_I2C_CR1_NACKIE BIT(4)
48 #define STM32_I2C_CR1_ADDRIE BIT(3)
49 #define STM32_I2C_CR1_RXIE BIT(2)
50 #define STM32_I2C_CR1_TXIE BIT(1)
51 #define STM32_I2C_CR1_PE BIT(0)
53 /* STM32 I2C control 2 */
54 #define STM32_I2C_CR2_AUTOEND BIT(25)
55 #define STM32_I2C_CR2_RELOAD BIT(24)
56 #define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
57 #define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16)
58 #define STM32_I2C_CR2_NACK BIT(15)
59 #define STM32_I2C_CR2_STOP BIT(14)
60 #define STM32_I2C_CR2_START BIT(13)
61 #define STM32_I2C_CR2_HEAD10R BIT(12)
62 #define STM32_I2C_CR2_ADD10 BIT(11)
63 #define STM32_I2C_CR2_RD_WRN BIT(10)
64 #define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
65 #define STM32_I2C_CR2_SADD10(n) (n & STM32_I2C_CR2_SADD10_MASK)
66 #define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
67 #define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
68 #define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
69 | STM32_I2C_CR2_NBYTES_MASK \
70 | STM32_I2C_CR2_SADD7_MASK \
71 | STM32_I2C_CR2_RELOAD \
72 | STM32_I2C_CR2_RD_WRN)
74 /* STM32 I2C Interrupt Status */
75 #define STM32_I2C_ISR_BUSY BIT(15)
76 #define STM32_I2C_ISR_ARLO BIT(9)
77 #define STM32_I2C_ISR_BERR BIT(8)
78 #define STM32_I2C_ISR_TCR BIT(7)
79 #define STM32_I2C_ISR_TC BIT(6)
80 #define STM32_I2C_ISR_STOPF BIT(5)
81 #define STM32_I2C_ISR_NACKF BIT(4)
82 #define STM32_I2C_ISR_ADDR BIT(3)
83 #define STM32_I2C_ISR_RXNE BIT(2)
84 #define STM32_I2C_ISR_TXIS BIT(1)
85 #define STM32_I2C_ISR_TXE BIT(0)
86 #define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \
89 /* STM32 I2C Interrupt Clear */
90 #define STM32_I2C_ICR_ARLOCF BIT(9)
91 #define STM32_I2C_ICR_BERRCF BIT(8)
92 #define STM32_I2C_ICR_STOPCF BIT(5)
93 #define STM32_I2C_ICR_NACKCF BIT(4)
95 /* STM32 I2C Timing */
96 #define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28)
97 #define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20)
98 #define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16)
99 #define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8)
100 #define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff)
102 #define STM32_I2C_MAX_LEN 0xff
104 #define STM32_I2C_DNF_DEFAULT 0
105 #define STM32_I2C_DNF_MAX 16
107 #define STM32_I2C_ANALOG_FILTER_ENABLE 1
108 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
109 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
111 #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
112 #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
114 #define STM32_PRESC_MAX BIT(4)
115 #define STM32_SCLDEL_MAX BIT(4)
116 #define STM32_SDADEL_MAX BIT(4)
117 #define STM32_SCLH_MAX BIT(8)
118 #define STM32_SCLL_MAX BIT(8)
120 #define STM32_NSEC_PER_SEC 1000000000L
123 * struct stm32_i2c_spec - private i2c specification timing
124 * @rate: I2C bus speed (Hz)
125 * @rate_min: 80% of I2C bus speed (Hz)
126 * @rate_max: 120% of I2C bus speed (Hz)
127 * @fall_max: Max fall time of both SDA and SCL signals (ns)
128 * @rise_max: Max rise time of both SDA and SCL signals (ns)
129 * @hddat_min: Min data hold time (ns)
130 * @vddat_max: Max data valid time (ns)
131 * @sudat_min: Min data setup time (ns)
132 * @l_min: Min low period of the SCL clock (ns)
133 * @h_min: Min high period of the SCL clock (ns)
136 struct stm32_i2c_spec {
150 * struct stm32_i2c_setup - private I2C timing setup parameters
151 * @speed_freq: I2C speed frequency (Hz)
152 * @clock_src: I2C clock source frequency (Hz)
153 * @rise_time: Rise time (ns)
154 * @fall_time: Fall time (ns)
155 * @dnf: Digital filter coefficient (0-16)
156 * @analog_filter: Analog filter delay (On/Off)
158 struct stm32_i2c_setup {
168 * struct stm32_i2c_timings - private I2C output parameters
169 * @prec: Prescaler value
170 * @scldel: Data setup time
171 * @sdadel: Data hold time
172 * @sclh: SCL high period (master mode)
173 * @sclh: SCL low period (master mode)
175 struct stm32_i2c_timings {
176 struct list_head node;
184 struct stm32_i2c_priv {
185 struct stm32_i2c_regs *regs;
187 struct stm32_i2c_setup *setup;
191 static const struct stm32_i2c_spec i2c_specs[] = {
192 /* Standard speed - 100 KHz */
193 [IC_SPEED_MODE_STANDARD] = {
194 .rate = I2C_SPEED_STANDARD_RATE,
205 /* Fast speed - 400 KHz */
206 [IC_SPEED_MODE_FAST] = {
207 .rate = I2C_SPEED_FAST_RATE,
218 /* Fast Plus Speed - 1 MHz */
219 [IC_SPEED_MODE_FAST_PLUS] = {
220 .rate = I2C_SPEED_FAST_PLUS_RATE,
233 static const struct stm32_i2c_setup stm32f7_setup = {
234 .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
235 .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
236 .dnf = STM32_I2C_DNF_DEFAULT,
237 .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
240 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
242 struct stm32_i2c_regs *regs = i2c_priv->regs;
243 u32 status = readl(®s->isr);
245 if (status & STM32_I2C_ISR_BUSY)
251 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
252 struct i2c_msg *msg, bool stop)
254 struct stm32_i2c_regs *regs = i2c_priv->regs;
255 u32 cr2 = readl(®s->cr2);
257 /* Set transfer direction */
258 cr2 &= ~STM32_I2C_CR2_RD_WRN;
259 if (msg->flags & I2C_M_RD)
260 cr2 |= STM32_I2C_CR2_RD_WRN;
262 /* Set slave address */
263 cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
264 if (msg->flags & I2C_M_TEN) {
265 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
266 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
267 cr2 |= STM32_I2C_CR2_ADD10;
269 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
270 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
273 /* Set nb bytes to transfer and reload or autoend bits */
274 cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
275 STM32_I2C_CR2_AUTOEND);
276 if (msg->len > STM32_I2C_MAX_LEN) {
277 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
278 cr2 |= STM32_I2C_CR2_RELOAD;
280 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
283 /* Write configurations register */
284 writel(cr2, ®s->cr2);
286 /* START/ReSTART generation */
287 setbits_le32(®s->cr2, STM32_I2C_CR2_START);
291 * RELOAD mode must be selected if total number of data bytes to be
292 * sent is greater than MAX_LEN
295 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
296 struct i2c_msg *msg, bool stop)
298 struct stm32_i2c_regs *regs = i2c_priv->regs;
299 u32 cr2 = readl(®s->cr2);
301 cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
303 if (msg->len > STM32_I2C_MAX_LEN) {
304 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
306 cr2 &= ~STM32_I2C_CR2_RELOAD;
307 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
310 writel(cr2, ®s->cr2);
313 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
314 u32 flags, u32 *status)
316 struct stm32_i2c_regs *regs = i2c_priv->regs;
317 u32 time_start = get_timer(0);
319 *status = readl(®s->isr);
320 while (!(*status & flags)) {
321 if (get_timer(time_start) > CONFIG_SYS_HZ) {
322 debug("%s: i2c timeout\n", __func__);
326 *status = readl(®s->isr);
332 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
334 struct stm32_i2c_regs *regs = i2c_priv->regs;
335 u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
340 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
344 if (status & STM32_I2C_ISR_BERR) {
345 debug("%s: Bus error\n", __func__);
347 /* Clear BERR flag */
348 setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF);
353 if (status & STM32_I2C_ISR_ARLO) {
354 debug("%s: Arbitration lost\n", __func__);
356 /* Clear ARLO flag */
357 setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF);
362 if (status & STM32_I2C_ISR_NACKF) {
363 debug("%s: Receive NACK\n", __func__);
365 /* Clear NACK flag */
366 setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF);
368 /* Wait until STOPF flag is set */
369 mask = STM32_I2C_ISR_STOPF;
370 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
377 if (status & STM32_I2C_ISR_STOPF) {
378 /* Clear STOP flag */
379 setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF);
381 /* Clear control register 2 */
382 setbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK);
388 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
389 struct i2c_msg *msg, bool stop)
391 struct stm32_i2c_regs *regs = i2c_priv->regs;
393 u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
394 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
395 int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
396 STM32_I2C_MAX_LEN : msg->len;
400 mask |= STM32_I2C_ISR_ERRORS;
402 stm32_i2c_message_start(i2c_priv, msg, stop);
406 * Wait until TXIS/NACKF/BERR/ARLO flags or
407 * RXNE/BERR/ARLO flags are set
409 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
413 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
416 if (status & STM32_I2C_ISR_RXNE) {
417 *msg->buf++ = readb(®s->rxdr);
422 if (status & STM32_I2C_ISR_TXIS) {
423 writeb(*msg->buf++, ®s->txdr);
428 if (!bytes_to_rw && msg->len) {
429 /* Wait until TCR flag is set */
430 mask = STM32_I2C_ISR_TCR;
431 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
435 bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
436 STM32_I2C_MAX_LEN : msg->len;
437 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
438 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
440 stm32_i2c_handle_reload(i2c_priv, msg, stop);
441 } else if (!bytes_to_rw) {
442 /* Wait until TC flag is set */
443 mask = STM32_I2C_ISR_TC;
444 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
449 /* Message sent, new message has to be sent */
454 /* End of transfer, send stop condition */
455 mask = STM32_I2C_CR2_STOP;
456 setbits_le32(®s->cr2, mask);
458 return stm32_i2c_check_end_of_message(i2c_priv);
461 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
464 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
467 ret = stm32_i2c_check_device_busy(i2c_priv);
471 for (; nmsgs > 0; nmsgs--, msg++) {
472 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
480 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
481 const struct stm32_i2c_spec *specs,
482 struct list_head *solutions)
484 struct stm32_i2c_timings *v;
485 u32 p_prev = STM32_PRESC_MAX;
486 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
488 u32 af_delay_min, af_delay_max;
490 int sdadel_min, sdadel_max, scldel_min;
493 af_delay_min = setup->analog_filter ?
494 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
495 af_delay_max = setup->analog_filter ?
496 STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
498 sdadel_min = specs->hddat_min + setup->fall_time -
499 af_delay_min - (setup->dnf + 3) * i2cclk;
501 sdadel_max = specs->vddat_max - setup->rise_time -
502 af_delay_max - (setup->dnf + 4) * i2cclk;
504 scldel_min = setup->rise_time + specs->sudat_min;
511 debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
512 sdadel_min, sdadel_max, scldel_min);
514 /* Compute possible values for PRESC, SCLDEL and SDADEL */
515 for (p = 0; p < STM32_PRESC_MAX; p++) {
516 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
517 int scldel = (l + 1) * (p + 1) * i2cclk;
519 if (scldel < scldel_min)
522 for (a = 0; a < STM32_SDADEL_MAX; a++) {
523 int sdadel = (a * (p + 1) + 1) * i2cclk;
525 if (((sdadel >= sdadel_min) &&
526 (sdadel <= sdadel_max)) &&
528 v = calloc(1, sizeof(*v));
537 list_add_tail(&v->node, solutions);
547 if (list_empty(solutions)) {
548 pr_err("%s: no Prescaler solution\n", __func__);
555 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
556 const struct stm32_i2c_spec *specs,
557 struct list_head *solutions,
558 struct stm32_i2c_timings *s)
560 struct stm32_i2c_timings *v;
561 u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
563 u32 clk_error_prev = i2cbus;
564 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
566 u32 clk_min, clk_max;
571 bool sol_found = false;
574 af_delay_min = setup->analog_filter ?
575 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
576 dnf_delay = setup->dnf * i2cclk;
578 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
579 clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
580 clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
583 * Among Prescaler possibilities discovered above figures out SCL Low
584 * and High Period. Provided:
585 * - SCL Low Period has to be higher than Low Period of the SCL Clock
586 * defined by I2C Specification. I2C Clock has to be lower than
587 * (SCL Low Period - Analog/Digital filters) / 4.
588 * - SCL High Period has to be lower than High Period of the SCL Clock
589 * defined by I2C Specification
590 * - I2C Clock has to be lower than SCL High Period
592 list_for_each_entry(v, solutions, node) {
593 u32 prescaler = (v->presc + 1) * i2cclk;
595 for (l = 0; l < STM32_SCLL_MAX; l++) {
596 u32 tscl_l = (l + 1) * prescaler + tsync;
598 if (tscl_l < specs->l_min ||
600 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
604 for (h = 0; h < STM32_SCLH_MAX; h++) {
605 u32 tscl_h = (h + 1) * prescaler + tsync;
606 u32 tscl = tscl_l + tscl_h +
607 setup->rise_time + setup->fall_time;
609 if ((tscl >= clk_min) && (tscl <= clk_max) &&
610 (tscl_h >= specs->h_min) &&
615 clk_error = tscl - i2cbus;
617 clk_error = i2cbus - tscl;
619 if (clk_error < clk_error_prev) {
620 clk_error_prev = clk_error;
624 memcpy(s, v, sizeof(*s));
632 pr_err("%s: no solution at all\n", __func__);
639 static const struct stm32_i2c_spec *get_specs(u32 rate)
643 for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
644 if (rate <= i2c_specs[i].rate)
645 return &i2c_specs[i];
648 return ERR_PTR(-EINVAL);
651 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
652 struct stm32_i2c_setup *setup,
653 struct stm32_i2c_timings *output)
655 const struct stm32_i2c_spec *specs;
656 struct stm32_i2c_timings *v, *_v;
657 struct list_head solutions;
660 specs = get_specs(setup->speed_freq);
661 if (specs == ERR_PTR(-EINVAL)) {
662 pr_err("%s: speed out of bound {%d}\n", __func__,
667 if (setup->rise_time > specs->rise_max ||
668 setup->fall_time > specs->fall_max) {
669 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
671 setup->rise_time, specs->rise_max,
672 setup->fall_time, specs->fall_max);
676 if (setup->dnf > STM32_I2C_DNF_MAX) {
677 pr_err("%s: DNF out of bound %d/%d\n", __func__,
678 setup->dnf, STM32_I2C_DNF_MAX);
682 INIT_LIST_HEAD(&solutions);
683 ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
687 ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
691 debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
692 __func__, output->presc,
693 output->scldel, output->sdadel,
694 output->scll, output->sclh);
697 /* Release list and memory */
698 list_for_each_entry_safe(v, _v, &solutions, node) {
706 static u32 get_lower_rate(u32 rate)
710 for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
711 if (rate > i2c_specs[i].rate)
712 return i2c_specs[i].rate;
714 return i2c_specs[0].rate;
717 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
718 struct stm32_i2c_timings *timing)
720 struct stm32_i2c_setup *setup = i2c_priv->setup;
723 setup->speed_freq = i2c_priv->speed;
724 setup->clock_src = clk_get_rate(&i2c_priv->clk);
726 if (!setup->clock_src) {
727 pr_err("%s: clock rate is 0\n", __func__);
732 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
734 debug("%s: failed to compute I2C timings.\n",
736 if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
738 get_lower_rate(setup->speed_freq);
739 debug("%s: downgrade I2C Speed Freq to (%i)\n",
740 __func__, setup->speed_freq);
748 pr_err("%s: impossible to compute I2C timings.\n", __func__);
752 debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
753 setup->speed_freq, setup->clock_src);
754 debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
755 setup->rise_time, setup->fall_time);
756 debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
757 setup->analog_filter ? "On" : "Off", setup->dnf);
759 i2c_priv->speed = setup->speed_freq;
764 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
766 struct stm32_i2c_regs *regs = i2c_priv->regs;
767 struct stm32_i2c_timings t;
771 ret = stm32_i2c_setup_timing(i2c_priv, &t);
776 clrbits_le32(®s->cr1, STM32_I2C_CR1_PE);
778 /* Timing settings */
779 timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
780 timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
781 timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
782 timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
783 timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
784 writel(timing, ®s->timingr);
787 if (i2c_priv->setup->analog_filter)
788 clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
790 setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
791 setbits_le32(®s->cr1, STM32_I2C_CR1_PE);
796 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
798 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
800 if (speed > I2C_SPEED_FAST_PLUS_RATE) {
801 debug("%s: Speed %d not supported\n", __func__, speed);
805 i2c_priv->speed = speed;
807 return stm32_i2c_hw_config(i2c_priv);
810 static int stm32_i2c_probe(struct udevice *dev)
812 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
813 struct reset_ctl reset_ctl;
817 addr = dev_read_addr(dev);
818 if (addr == FDT_ADDR_T_NONE)
821 i2c_priv->regs = (struct stm32_i2c_regs *)addr;
823 ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
827 ret = clk_enable(&i2c_priv->clk);
831 ret = reset_get_by_index(dev, 0, &reset_ctl);
835 reset_assert(&reset_ctl);
837 reset_deassert(&reset_ctl);
842 clk_disable(&i2c_priv->clk);
844 clk_free(&i2c_priv->clk);
849 static int stm32_ofdata_to_platdata(struct udevice *dev)
851 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
852 u32 rise_time, fall_time;
854 i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
855 if (!i2c_priv->setup)
858 rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
860 i2c_priv->setup->rise_time = rise_time;
862 fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
864 i2c_priv->setup->fall_time = fall_time;
869 static const struct dm_i2c_ops stm32_i2c_ops = {
870 .xfer = stm32_i2c_xfer,
871 .set_bus_speed = stm32_i2c_set_bus_speed,
874 static const struct udevice_id stm32_i2c_of_match[] = {
875 { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
879 U_BOOT_DRIVER(stm32f7_i2c) = {
880 .name = "stm32f7-i2c",
882 .of_match = stm32_i2c_of_match,
883 .ofdata_to_platdata = stm32_ofdata_to_platdata,
884 .probe = stm32_i2c_probe,
885 .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
886 .ops = &stm32_i2c_ops,