drivers/i2c/stm32f7_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 STMicroelectronics
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <i2c.h>
  10 #include <log.h>
  11 #include <regmap.h>
  12 #include <reset.h>
  13 #include <syscon.h>
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16
  17 #include <dm/device.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20
  21 /* STM32 I2C registers */
  22 struct stm32_i2c_regs {
  23         u32 cr1;        /* I2C control register 1 */
  24         u32 cr2;        /* I2C control register 2 */
  25         u32 oar1;       /* I2C own address 1 register */
  26         u32 oar2;       /* I2C own address 2 register */
  27         u32 timingr;    /* I2C timing register */
  28         u32 timeoutr;   /* I2C timeout register */
  29         u32 isr;        /* I2C interrupt and status register */
  30         u32 icr;        /* I2C interrupt clear register */
  31         u32 pecr;       /* I2C packet error checking register */
  32         u32 rxdr;       /* I2C receive data register */
  33         u32 txdr;       /* I2C transmit data register */
  34 };
  35
  36 #define STM32_I2C_CR1                           0x00
  37 #define STM32_I2C_CR2                           0x04
  38 #define STM32_I2C_TIMINGR                       0x10
  39 #define STM32_I2C_ISR                           0x18
  40 #define STM32_I2C_ICR                           0x1C
  41 #define STM32_I2C_RXDR                          0x24
  42 #define STM32_I2C_TXDR                          0x28
  43
  44 /* STM32 I2C control 1 */
  45 #define STM32_I2C_CR1_ANFOFF                    BIT(12)
  46 #define STM32_I2C_CR1_ERRIE                     BIT(7)
  47 #define STM32_I2C_CR1_TCIE                      BIT(6)
  48 #define STM32_I2C_CR1_STOPIE                    BIT(5)
  49 #define STM32_I2C_CR1_NACKIE                    BIT(4)
  50 #define STM32_I2C_CR1_ADDRIE                    BIT(3)
  51 #define STM32_I2C_CR1_RXIE                      BIT(2)
  52 #define STM32_I2C_CR1_TXIE                      BIT(1)
  53 #define STM32_I2C_CR1_PE                        BIT(0)
  54
  55 /* STM32 I2C control 2 */
  56 #define STM32_I2C_CR2_AUTOEND                   BIT(25)
  57 #define STM32_I2C_CR2_RELOAD                    BIT(24)
  58 #define STM32_I2C_CR2_NBYTES_MASK               GENMASK(23, 16)
  59 #define STM32_I2C_CR2_NBYTES(n)                 ((n & 0xff) << 16)
  60 #define STM32_I2C_CR2_NACK                      BIT(15)
  61 #define STM32_I2C_CR2_STOP                      BIT(14)
  62 #define STM32_I2C_CR2_START                     BIT(13)
  63 #define STM32_I2C_CR2_HEAD10R                   BIT(12)
  64 #define STM32_I2C_CR2_ADD10                     BIT(11)
  65 #define STM32_I2C_CR2_RD_WRN                    BIT(10)
  66 #define STM32_I2C_CR2_SADD10_MASK               GENMASK(9, 0)
  67 #define STM32_I2C_CR2_SADD10(n)                 (n & STM32_I2C_CR2_SADD10_MASK)
  68 #define STM32_I2C_CR2_SADD7_MASK                GENMASK(7, 1)
  69 #define STM32_I2C_CR2_SADD7(n)                  ((n & 0x7f) << 1)
  70 #define STM32_I2C_CR2_RESET_MASK                (STM32_I2C_CR2_HEAD10R \
  71                                                 | STM32_I2C_CR2_NBYTES_MASK \
  72                                                 | STM32_I2C_CR2_SADD7_MASK \
  73                                                 | STM32_I2C_CR2_RELOAD \
  74                                                 | STM32_I2C_CR2_RD_WRN)
  75
  76 /* STM32 I2C Interrupt Status */
  77 #define STM32_I2C_ISR_BUSY                      BIT(15)
  78 #define STM32_I2C_ISR_ARLO                      BIT(9)
  79 #define STM32_I2C_ISR_BERR                      BIT(8)
  80 #define STM32_I2C_ISR_TCR                       BIT(7)
  81 #define STM32_I2C_ISR_TC                        BIT(6)
  82 #define STM32_I2C_ISR_STOPF                     BIT(5)
  83 #define STM32_I2C_ISR_NACKF                     BIT(4)
  84 #define STM32_I2C_ISR_ADDR                      BIT(3)
  85 #define STM32_I2C_ISR_RXNE                      BIT(2)
  86 #define STM32_I2C_ISR_TXIS                      BIT(1)
  87 #define STM32_I2C_ISR_TXE                       BIT(0)
  88 #define STM32_I2C_ISR_ERRORS                    (STM32_I2C_ISR_BERR \
  89                                                 | STM32_I2C_ISR_ARLO)
  90
  91 /* STM32 I2C Interrupt Clear */
  92 #define STM32_I2C_ICR_ARLOCF                    BIT(9)
  93 #define STM32_I2C_ICR_BERRCF                    BIT(8)
  94 #define STM32_I2C_ICR_STOPCF                    BIT(5)
  95 #define STM32_I2C_ICR_NACKCF                    BIT(4)
  96
  97 /* STM32 I2C Timing */
  98 #define STM32_I2C_TIMINGR_PRESC(n)              ((n & 0xf) << 28)
  99 #define STM32_I2C_TIMINGR_SCLDEL(n)             ((n & 0xf) << 20)
 100 #define STM32_I2C_TIMINGR_SDADEL(n)             ((n & 0xf) << 16)
 101 #define STM32_I2C_TIMINGR_SCLH(n)               ((n & 0xff) << 8)
 102 #define STM32_I2C_TIMINGR_SCLL(n)               (n & 0xff)
 103
 104 #define STM32_I2C_MAX_LEN                       0xff
 105
 106 #define STM32_I2C_DNF_DEFAULT                   0
 107 #define STM32_I2C_DNF_MAX                       16
 108
 109 #define STM32_I2C_ANALOG_FILTER_ENABLE  1
 110 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN       50      /* ns */
 111 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX       260     /* ns */
 112
 113 #define STM32_I2C_RISE_TIME_DEFAULT             25      /* ns */
 114 #define STM32_I2C_FALL_TIME_DEFAULT             10      /* ns */
 115
 116 #define STM32_PRESC_MAX                         BIT(4)
 117 #define STM32_SCLDEL_MAX                        BIT(4)
 118 #define STM32_SDADEL_MAX                        BIT(4)
 119 #define STM32_SCLH_MAX                          BIT(8)
 120 #define STM32_SCLL_MAX                          BIT(8)
 121
 122 #define STM32_NSEC_PER_SEC                      1000000000L
 123
 124 /**
 125  * struct stm32_i2c_spec - private i2c specification timing
 126  * @rate: I2C bus speed (Hz)
 127  * @rate_min: 80% of I2C bus speed (Hz)
 128  * @rate_max: 120% of I2C bus speed (Hz)
 129  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 130  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 131  * @hddat_min: Min data hold time (ns)
 132  * @vddat_max: Max data valid time (ns)
 133  * @sudat_min: Min data setup time (ns)
 134  * @l_min: Min low period of the SCL clock (ns)
 135  * @h_min: Min high period of the SCL clock (ns)
 136  */
 137
 138 struct stm32_i2c_spec {
 139         u32 rate;
 140         u32 rate_min;
 141         u32 rate_max;
 142         u32 fall_max;
 143         u32 rise_max;
 144         u32 hddat_min;
 145         u32 vddat_max;
 146         u32 sudat_min;
 147         u32 l_min;
 148         u32 h_min;
 149 };
 150
 151 /**
 152  * struct stm32_i2c_setup - private I2C timing setup parameters
 153  * @speed_freq: I2C speed frequency  (Hz)
 154  * @clock_src: I2C clock source frequency (Hz)
 155  * @rise_time: Rise time (ns)
 156  * @fall_time: Fall time (ns)
 157  * @dnf: Digital filter coefficient (0-16)
 158  * @analog_filter: Analog filter delay (On/Off)
 159  * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
 160  */
 161 struct stm32_i2c_setup {
 162         u32 speed_freq;
 163         u32 clock_src;
 164         u32 rise_time;
 165         u32 fall_time;
 166         u8 dnf;
 167         bool analog_filter;
 168         u32 fmp_clr_offset;
 169 };
 170
 171 /**
 172  * struct stm32_i2c_timings - private I2C output parameters
 173  * @prec: Prescaler value
 174  * @scldel: Data setup time
 175  * @sdadel: Data hold time
 176  * @sclh: SCL high period (master mode)
 177  * @sclh: SCL low period (master mode)
 178  */
 179 struct stm32_i2c_timings {
 180         struct list_head node;
 181         u8 presc;
 182         u8 scldel;
 183         u8 sdadel;
 184         u8 sclh;
 185         u8 scll;
 186 };
 187
 188 /**
 189  * struct stm32_i2c_priv - private data of the controller
 190  * @regs: I2C registers address
 191  * @clk: hw i2c clock
 192  * @setup: I2C timing setup parameters
 193  * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
 194  * @regmap: holds SYSCFG phandle for Fast Mode Plus bit
 195  * @regmap_sreg: register address for setting Fast Mode Plus bits
 196  * @regmap_creg: register address for clearing Fast Mode Plus bits
 197  * @regmap_mask: mask for Fast Mode Plus bits
 198  */
 199 struct stm32_i2c_priv {
 200         struct stm32_i2c_regs *regs;
 201         struct clk clk;
 202         struct stm32_i2c_setup *setup;
 203         u32 speed;
 204         struct regmap *regmap;
 205         u32 regmap_sreg;
 206         u32 regmap_creg;
 207         u32 regmap_mask;
 208 };
 209
 210 static const struct stm32_i2c_spec i2c_specs[] = {
 211         /* Standard speed - 100 KHz */
 212         [IC_SPEED_MODE_STANDARD] = {
 213                 .rate = I2C_SPEED_STANDARD_RATE,
 214                 .rate_min = 8000,
 215                 .rate_max = 120000,
 216                 .fall_max = 300,
 217                 .rise_max = 1000,
 218                 .hddat_min = 0,
 219                 .vddat_max = 3450,
 220                 .sudat_min = 250,
 221                 .l_min = 4700,
 222                 .h_min = 4000,
 223         },
 224         /* Fast speed - 400 KHz */
 225         [IC_SPEED_MODE_FAST] = {
 226                 .rate = I2C_SPEED_FAST_RATE,
 227                 .rate_min = 320000,
 228                 .rate_max = 480000,
 229                 .fall_max = 300,
 230                 .rise_max = 300,
 231                 .hddat_min = 0,
 232                 .vddat_max = 900,
 233                 .sudat_min = 100,
 234                 .l_min = 1300,
 235                 .h_min = 600,
 236         },
 237         /* Fast Plus Speed - 1 MHz */
 238         [IC_SPEED_MODE_FAST_PLUS] = {
 239                 .rate = I2C_SPEED_FAST_PLUS_RATE,
 240                 .rate_min = 800000,
 241                 .rate_max = 1200000,
 242                 .fall_max = 100,
 243                 .rise_max = 120,
 244                 .hddat_min = 0,
 245                 .vddat_max = 450,
 246                 .sudat_min = 50,
 247                 .l_min = 500,
 248                 .h_min = 260,
 249         },
 250 };
 251
 252 static const struct stm32_i2c_setup stm32f7_setup = {
 253         .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
 254         .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
 255         .dnf = STM32_I2C_DNF_DEFAULT,
 256         .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
 257 };
 258
 259 static const struct stm32_i2c_setup stm32mp15_setup = {
 260         .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
 261         .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
 262         .dnf = STM32_I2C_DNF_DEFAULT,
 263         .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
 264         .fmp_clr_offset = 0x40,
 265 };
 266
 267 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
 268 {
 269         struct stm32_i2c_regs *regs = i2c_priv->regs;
 270         u32 status = readl(&regs->isr);
 271
 272         if (status & STM32_I2C_ISR_BUSY)
 273                 return -EBUSY;
 274
 275         return 0;
 276 }
 277
 278 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
 279                                     struct i2c_msg *msg, bool stop)
 280 {
 281         struct stm32_i2c_regs *regs = i2c_priv->regs;
 282         u32 cr2 = readl(&regs->cr2);
 283
 284         /* Set transfer direction */
 285         cr2 &= ~STM32_I2C_CR2_RD_WRN;
 286         if (msg->flags & I2C_M_RD)
 287                 cr2 |= STM32_I2C_CR2_RD_WRN;
 288
 289         /* Set slave address */
 290         cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
 291         if (msg->flags & I2C_M_TEN) {
 292                 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
 293                 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
 294                 cr2 |= STM32_I2C_CR2_ADD10;
 295         } else {
 296                 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
 297                 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
 298         }
 299
 300         /* Set nb bytes to transfer and reload or autoend bits */
 301         cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
 302                  STM32_I2C_CR2_AUTOEND);
 303         if (msg->len > STM32_I2C_MAX_LEN) {
 304                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 305                 cr2 |= STM32_I2C_CR2_RELOAD;
 306         } else {
 307                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 308         }
 309
 310         /* Write configurations register */
 311         writel(cr2, &regs->cr2);
 312
 313         /* START/ReSTART generation */
 314         setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
 315 }
 316
 317 /*
 318  * RELOAD mode must be selected if total number of data bytes to be
 319  * sent is greater than MAX_LEN
 320  */
 321
 322 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
 323                                     struct i2c_msg *msg, bool stop)
 324 {
 325         struct stm32_i2c_regs *regs = i2c_priv->regs;
 326         u32 cr2 = readl(&regs->cr2);
 327
 328         cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
 329
 330         if (msg->len > STM32_I2C_MAX_LEN) {
 331                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 332         } else {
 333                 cr2 &= ~STM32_I2C_CR2_RELOAD;
 334                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 335         }
 336
 337         writel(cr2, &regs->cr2);
 338 }
 339
 340 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
 341                                 u32 flags, u32 *status)
 342 {
 343         struct stm32_i2c_regs *regs = i2c_priv->regs;
 344         u32 time_start = get_timer(0);
 345
 346         *status = readl(&regs->isr);
 347         while (!(*status & flags)) {
 348                 if (get_timer(time_start) > CONFIG_SYS_HZ) {
 349                         debug("%s: i2c timeout\n", __func__);
 350                         return -ETIMEDOUT;
 351                 }
 352
 353                 *status = readl(&regs->isr);
 354         }
 355
 356         return 0;
 357 }
 358
 359 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
 360 {
 361         struct stm32_i2c_regs *regs = i2c_priv->regs;
 362         u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
 363                    STM32_I2C_ISR_STOPF;
 364         u32 status;
 365         int ret;
 366
 367         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 368         if (ret)
 369                 return ret;
 370
 371         if (status & STM32_I2C_ISR_BERR) {
 372                 debug("%s: Bus error\n", __func__);
 373
 374                 /* Clear BERR flag */
 375                 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
 376
 377                 return -EIO;
 378         }
 379
 380         if (status & STM32_I2C_ISR_ARLO) {
 381                 debug("%s: Arbitration lost\n", __func__);
 382
 383                 /* Clear ARLO flag */
 384                 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
 385
 386                 return -EAGAIN;
 387         }
 388
 389         if (status & STM32_I2C_ISR_NACKF) {
 390                 debug("%s: Receive NACK\n", __func__);
 391
 392                 /* Clear NACK flag */
 393                 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
 394
 395                 /* Wait until STOPF flag is set */
 396                 mask = STM32_I2C_ISR_STOPF;
 397                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 398                 if (ret)
 399                         return ret;
 400
 401                 ret = -EIO;
 402         }
 403
 404         if (status & STM32_I2C_ISR_STOPF) {
 405                 /* Clear STOP flag */
 406                 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
 407
 408                 /* Clear control register 2 */
 409                 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
 410         }
 411
 412         return ret;
 413 }
 414
 415 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
 416                                   struct i2c_msg *msg, bool stop)
 417 {
 418         struct stm32_i2c_regs *regs = i2c_priv->regs;
 419         u32 status;
 420         u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 421                    STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 422         int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 423                           STM32_I2C_MAX_LEN : msg->len;
 424         int ret = 0;
 425
 426         /* Add errors */
 427         mask |= STM32_I2C_ISR_ERRORS;
 428
 429         stm32_i2c_message_start(i2c_priv, msg, stop);
 430
 431         while (msg->len) {
 432                 /*
 433                  * Wait until TXIS/NACKF/BERR/ARLO flags or
 434                  * RXNE/BERR/ARLO flags are set
 435                  */
 436                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 437                 if (ret)
 438                         break;
 439
 440                 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
 441                         break;
 442
 443                 if (status & STM32_I2C_ISR_RXNE) {
 444                         *msg->buf++ = readb(&regs->rxdr);
 445                         msg->len--;
 446                         bytes_to_rw--;
 447                 }
 448
 449                 if (status & STM32_I2C_ISR_TXIS) {
 450                         writeb(*msg->buf++, &regs->txdr);
 451                         msg->len--;
 452                         bytes_to_rw--;
 453                 }
 454
 455                 if (!bytes_to_rw && msg->len) {
 456                         /* Wait until TCR flag is set */
 457                         mask = STM32_I2C_ISR_TCR;
 458                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 459                         if (ret)
 460                                 break;
 461
 462                         bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 463                                       STM32_I2C_MAX_LEN : msg->len;
 464                         mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 465                                STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 466
 467                         stm32_i2c_handle_reload(i2c_priv, msg, stop);
 468                 } else if (!bytes_to_rw) {
 469                         /* Wait until TC flag is set */
 470                         mask = STM32_I2C_ISR_TC;
 471                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 472                         if (ret)
 473                                 break;
 474
 475                         if (!stop)
 476                                 /* Message sent, new message has to be sent */
 477                                 return 0;
 478                 }
 479         }
 480
 481         /* End of transfer, send stop condition */
 482         mask = STM32_I2C_CR2_STOP;
 483         setbits_le32(&regs->cr2, mask);
 484
 485         return stm32_i2c_check_end_of_message(i2c_priv);
 486 }
 487
 488 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 489                           int nmsgs)
 490 {
 491         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 492         int ret;
 493
 494         ret = stm32_i2c_check_device_busy(i2c_priv);
 495         if (ret)
 496                 return ret;
 497
 498         for (; nmsgs > 0; nmsgs--, msg++) {
 499                 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
 500                 if (ret)
 501                         return ret;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
 508                                        const struct stm32_i2c_spec *specs,
 509                                        struct list_head *solutions)
 510 {
 511         struct stm32_i2c_timings *v;
 512         u32 p_prev = STM32_PRESC_MAX;
 513         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 514                                        setup->clock_src);
 515         u32 af_delay_min, af_delay_max;
 516         u16 p, l, a;
 517         int sdadel_min, sdadel_max, scldel_min;
 518         int ret = 0;
 519
 520         af_delay_min = setup->analog_filter ?
 521                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 522         af_delay_max = setup->analog_filter ?
 523                        STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
 524
 525         sdadel_min = specs->hddat_min + setup->fall_time -
 526                      af_delay_min - (setup->dnf + 3) * i2cclk;
 527
 528         sdadel_max = specs->vddat_max - setup->rise_time -
 529                      af_delay_max - (setup->dnf + 4) * i2cclk;
 530
 531         scldel_min = setup->rise_time + specs->sudat_min;
 532
 533         if (sdadel_min < 0)
 534                 sdadel_min = 0;
 535         if (sdadel_max < 0)
 536                 sdadel_max = 0;
 537
 538         debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
 539               sdadel_min, sdadel_max, scldel_min);
 540
 541         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 542         for (p = 0; p < STM32_PRESC_MAX; p++) {
 543                 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
 544                         int scldel = (l + 1) * (p + 1) * i2cclk;
 545
 546                         if (scldel < scldel_min)
 547                                 continue;
 548
 549                         for (a = 0; a < STM32_SDADEL_MAX; a++) {
 550                                 int sdadel = (a * (p + 1) + 1) * i2cclk;
 551
 552                                 if (((sdadel >= sdadel_min) &&
 553                                      (sdadel <= sdadel_max)) &&
 554                                     (p != p_prev)) {
 555                                         v = calloc(1, sizeof(*v));
 556                                         if (!v)
 557                                                 return -ENOMEM;
 558
 559                                         v->presc = p;
 560                                         v->scldel = l;
 561                                         v->sdadel = a;
 562                                         p_prev = p;
 563
 564                                         list_add_tail(&v->node, solutions);
 565                                         break;
 566                                 }
 567                         }
 568
 569                         if (p_prev == p)
 570                                 break;
 571                 }
 572         }
 573
 574         if (list_empty(solutions)) {
 575                 pr_err("%s: no Prescaler solution\n", __func__);
 576                 ret = -EPERM;
 577         }
 578
 579         return ret;
 580 }
 581
 582 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
 583                                      const struct stm32_i2c_spec *specs,
 584                                      struct list_head *solutions,
 585                                      struct stm32_i2c_timings *s)
 586 {
 587         struct stm32_i2c_timings *v;
 588         u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 589                                        setup->speed_freq);
 590         u32 clk_error_prev = i2cbus;
 591         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 592                                        setup->clock_src);
 593         u32 clk_min, clk_max;
 594         u32 af_delay_min;
 595         u32 dnf_delay;
 596         u32 tsync;
 597         u16 l, h;
 598         bool sol_found = false;
 599         int ret = 0;
 600
 601         af_delay_min = setup->analog_filter ?
 602                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 603         dnf_delay = setup->dnf * i2cclk;
 604
 605         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 606         clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
 607         clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
 608
 609         /*
 610          * Among Prescaler possibilities discovered above figures out SCL Low
 611          * and High Period. Provided:
 612          * - SCL Low Period has to be higher than Low Period of the SCL Clock
 613          *   defined by I2C Specification. I2C Clock has to be lower than
 614          *   (SCL Low Period - Analog/Digital filters) / 4.
 615          * - SCL High Period has to be lower than High Period of the SCL Clock
 616          *   defined by I2C Specification
 617          * - I2C Clock has to be lower than SCL High Period
 618          */
 619         list_for_each_entry(v, solutions, node) {
 620                 u32 prescaler = (v->presc + 1) * i2cclk;
 621
 622                 for (l = 0; l < STM32_SCLL_MAX; l++) {
 623                         u32 tscl_l = (l + 1) * prescaler + tsync;
 624
 625                         if (tscl_l < specs->l_min ||
 626                             (i2cclk >=
 627                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 628                                 continue;
 629                         }
 630
 631                         for (h = 0; h < STM32_SCLH_MAX; h++) {
 632                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 633                                 u32 tscl = tscl_l + tscl_h +
 634                                            setup->rise_time + setup->fall_time;
 635
 636                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 637                                     (tscl_h >= specs->h_min) &&
 638                                     (i2cclk < tscl_h)) {
 639                                         u32 clk_error;
 640
 641                                         if (tscl > i2cbus)
 642                                                 clk_error = tscl - i2cbus;
 643                                         else
 644                                                 clk_error = i2cbus - tscl;
 645
 646                                         if (clk_error < clk_error_prev) {
 647                                                 clk_error_prev = clk_error;
 648                                                 v->scll = l;
 649                                                 v->sclh = h;
 650                                                 sol_found = true;
 651                                                 memcpy(s, v, sizeof(*s));
 652                                         }
 653                                 }
 654                         }
 655                 }
 656         }
 657
 658         if (!sol_found) {
 659                 pr_err("%s: no solution at all\n", __func__);
 660                 ret = -EPERM;
 661         }
 662
 663         return ret;
 664 }
 665
 666 static const struct stm32_i2c_spec *get_specs(u32 rate)
 667 {
 668         unsigned int i;
 669
 670         for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
 671                 if (rate <= i2c_specs[i].rate)
 672                         return &i2c_specs[i];
 673
 674         /* NOT REACHED */
 675         return ERR_PTR(-EINVAL);
 676 }
 677
 678 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
 679                                     struct stm32_i2c_setup *setup,
 680                                     struct stm32_i2c_timings *output)
 681 {
 682         const struct stm32_i2c_spec *specs;
 683         struct stm32_i2c_timings *v, *_v;
 684         struct list_head solutions;
 685         int ret;
 686
 687         specs = get_specs(setup->speed_freq);
 688         if (specs == ERR_PTR(-EINVAL)) {
 689                 pr_err("%s: speed out of bound {%d}\n", __func__,
 690                        setup->speed_freq);
 691                 return -EINVAL;
 692         }
 693
 694         if (setup->rise_time > specs->rise_max ||
 695             setup->fall_time > specs->fall_max) {
 696                 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 697                        __func__,
 698                        setup->rise_time, specs->rise_max,
 699                        setup->fall_time, specs->fall_max);
 700                 return -EINVAL;
 701         }
 702
 703         if (setup->dnf > STM32_I2C_DNF_MAX) {
 704                 pr_err("%s: DNF out of bound %d/%d\n", __func__,
 705                        setup->dnf, STM32_I2C_DNF_MAX);
 706                 return -EINVAL;
 707         }
 708
 709         INIT_LIST_HEAD(&solutions);
 710         ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
 711         if (ret)
 712                 goto exit;
 713
 714         ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
 715         if (ret)
 716                 goto exit;
 717
 718         debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 719               __func__, output->presc,
 720               output->scldel, output->sdadel,
 721               output->scll, output->sclh);
 722
 723 exit:
 724         /* Release list and memory */
 725         list_for_each_entry_safe(v, _v, &solutions, node) {
 726                 list_del(&v->node);
 727                 free(v);
 728         }
 729
 730         return ret;
 731 }
 732
 733 static u32 get_lower_rate(u32 rate)
 734 {
 735         int i;
 736
 737         for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
 738                 if (rate > i2c_specs[i].rate)
 739                         return i2c_specs[i].rate;
 740
 741         return i2c_specs[0].rate;
 742 }
 743
 744 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
 745                                   struct stm32_i2c_timings *timing)
 746 {
 747         struct stm32_i2c_setup *setup = i2c_priv->setup;
 748         int ret = 0;
 749
 750         setup->speed_freq = i2c_priv->speed;
 751         setup->clock_src = clk_get_rate(&i2c_priv->clk);
 752
 753         if (!setup->clock_src) {
 754                 pr_err("%s: clock rate is 0\n", __func__);
 755                 return -EINVAL;
 756         }
 757
 758         do {
 759                 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
 760                 if (ret) {
 761                         debug("%s: failed to compute I2C timings.\n",
 762                               __func__);
 763                         if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
 764                                 setup->speed_freq =
 765                                         get_lower_rate(setup->speed_freq);
 766                                 debug("%s: downgrade I2C Speed Freq to (%i)\n",
 767                                       __func__, setup->speed_freq);
 768                         } else {
 769                                 break;
 770                         }
 771                 }
 772         } while (ret);
 773
 774         if (ret) {
 775                 pr_err("%s: impossible to compute I2C timings.\n", __func__);
 776                 return ret;
 777         }
 778
 779         debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
 780               setup->speed_freq, setup->clock_src);
 781         debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
 782               setup->rise_time, setup->fall_time);
 783         debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
 784               setup->analog_filter ? "On" : "Off", setup->dnf);
 785
 786         i2c_priv->speed = setup->speed_freq;
 787
 788         return 0;
 789 }
 790
 791 static int stm32_i2c_write_fm_plus_bits(struct stm32_i2c_priv *i2c_priv)
 792 {
 793         int ret;
 794         bool enable = i2c_priv->speed > I2C_SPEED_FAST_RATE;
 795
 796         /* Optional */
 797         if (IS_ERR_OR_NULL(i2c_priv->regmap))
 798                 return 0;
 799
 800         if (i2c_priv->regmap_sreg == i2c_priv->regmap_creg)
 801                 ret = regmap_update_bits(i2c_priv->regmap,
 802                                          i2c_priv->regmap_sreg,
 803                                          i2c_priv->regmap_mask,
 804                                          enable ? i2c_priv->regmap_mask : 0);
 805         else
 806                 ret = regmap_write(i2c_priv->regmap,
 807                                    enable ? i2c_priv->regmap_sreg :
 808                                             i2c_priv->regmap_creg,
 809                                    i2c_priv->regmap_mask);
 810
 811         return ret;
 812 }
 813
 814 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
 815 {
 816         struct stm32_i2c_regs *regs = i2c_priv->regs;
 817         struct stm32_i2c_timings t;
 818         int ret;
 819         u32 timing = 0;
 820
 821         ret = stm32_i2c_setup_timing(i2c_priv, &t);
 822         if (ret)
 823                 return ret;
 824
 825         /* Disable I2C */
 826         clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 827
 828         /* Setup Fast mode plus if necessary */
 829         ret = stm32_i2c_write_fm_plus_bits(i2c_priv);
 830         if (ret)
 831                 return ret;
 832
 833         /* Timing settings */
 834         timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
 835         timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
 836         timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
 837         timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
 838         timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
 839         writel(timing, &regs->timingr);
 840
 841         /* Enable I2C */
 842         if (i2c_priv->setup->analog_filter)
 843                 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 844         else
 845                 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 846         setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 847
 848         return 0;
 849 }
 850
 851 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 852 {
 853         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 854
 855         if (speed > I2C_SPEED_FAST_PLUS_RATE) {
 856                 debug("%s: Speed %d not supported\n", __func__, speed);
 857                 return -EINVAL;
 858         }
 859
 860         i2c_priv->speed = speed;
 861
 862         return stm32_i2c_hw_config(i2c_priv);
 863 }
 864
 865 static int stm32_i2c_probe(struct udevice *dev)
 866 {
 867         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 868         struct reset_ctl reset_ctl;
 869         fdt_addr_t addr;
 870         int ret;
 871
 872         addr = dev_read_addr(dev);
 873         if (addr == FDT_ADDR_T_NONE)
 874                 return -EINVAL;
 875
 876         i2c_priv->regs = (struct stm32_i2c_regs *)addr;
 877
 878         ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
 879         if (ret)
 880                 return ret;
 881
 882         ret = clk_enable(&i2c_priv->clk);
 883         if (ret)
 884                 goto clk_free;
 885
 886         ret = reset_get_by_index(dev, 0, &reset_ctl);
 887         if (ret)
 888                 goto clk_disable;
 889
 890         reset_assert(&reset_ctl);
 891         udelay(2);
 892         reset_deassert(&reset_ctl);
 893
 894         return 0;
 895
 896 clk_disable:
 897         clk_disable(&i2c_priv->clk);
 898 clk_free:
 899         clk_free(&i2c_priv->clk);
 900
 901         return ret;
 902 }
 903
 904 static int stm32_of_to_plat(struct udevice *dev)
 905 {
 906         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 907         u32 rise_time, fall_time;
 908         int ret;
 909
 910         i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
 911         if (!i2c_priv->setup)
 912                 return -EINVAL;
 913
 914         rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
 915         if (rise_time)
 916                 i2c_priv->setup->rise_time = rise_time;
 917
 918         fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
 919         if (fall_time)
 920                 i2c_priv->setup->fall_time = fall_time;
 921
 922         /* Optional */
 923         i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev,
 924                                                            "st,syscfg-fmp");
 925         if (!IS_ERR(i2c_priv->regmap)) {
 926                 u32 fmp[3];
 927
 928                 ret = dev_read_u32_array(dev, "st,syscfg-fmp", fmp, 3);
 929                 if (ret)
 930                         return ret;
 931
 932                 i2c_priv->regmap_sreg = fmp[1];
 933                 i2c_priv->regmap_creg = fmp[1] +
 934                                         i2c_priv->setup->fmp_clr_offset;
 935                 i2c_priv->regmap_mask = fmp[2];
 936         }
 937
 938         return 0;
 939 }
 940
 941 static const struct dm_i2c_ops stm32_i2c_ops = {
 942         .xfer = stm32_i2c_xfer,
 943         .set_bus_speed = stm32_i2c_set_bus_speed,
 944 };
 945
 946 static const struct udevice_id stm32_i2c_of_match[] = {
 947         { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
 948         { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_setup },
 949         {}
 950 };
 951
 952 U_BOOT_DRIVER(stm32f7_i2c) = {
 953         .name = "stm32f7-i2c",
 954         .id = UCLASS_I2C,
 955         .of_match = stm32_i2c_of_match,
 956         .of_to_plat = stm32_of_to_plat,
 957         .probe = stm32_i2c_probe,
 958         .priv_auto      = sizeof(struct stm32_i2c_priv),
 959         .ops = &stm32_i2c_ops,
 960 };