drivers/i2c/stm32f7_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 STMicroelectronics
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_I2C
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <i2c.h>
  12 #include <log.h>
  13 #include <regmap.h>
  14 #include <reset.h>
  15 #include <syscon.h>
  16 #include <dm/device.h>
  17 #include <dm/device_compat.h>
  18 #include <linux/bitops.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/io.h>
  22
  23 /* STM32 I2C registers */
  24 struct stm32_i2c_regs {
  25         u32 cr1;        /* I2C control register 1 */
  26         u32 cr2;        /* I2C control register 2 */
  27         u32 oar1;       /* I2C own address 1 register */
  28         u32 oar2;       /* I2C own address 2 register */
  29         u32 timingr;    /* I2C timing register */
  30         u32 timeoutr;   /* I2C timeout register */
  31         u32 isr;        /* I2C interrupt and status register */
  32         u32 icr;        /* I2C interrupt clear register */
  33         u32 pecr;       /* I2C packet error checking register */
  34         u32 rxdr;       /* I2C receive data register */
  35         u32 txdr;       /* I2C transmit data register */
  36 };
  37
  38 #define STM32_I2C_CR1                           0x00
  39 #define STM32_I2C_CR2                           0x04
  40 #define STM32_I2C_TIMINGR                       0x10
  41 #define STM32_I2C_ISR                           0x18
  42 #define STM32_I2C_ICR                           0x1C
  43 #define STM32_I2C_RXDR                          0x24
  44 #define STM32_I2C_TXDR                          0x28
  45
  46 /* STM32 I2C control 1 */
  47 #define STM32_I2C_CR1_ANFOFF                    BIT(12)
  48 #define STM32_I2C_CR1_DNF_MASK                  GENMASK(11, 8)
  49 #define STM32_I2C_CR1_DNF(n)                    (((n) & 0xf) << 8)
  50 #define STM32_I2C_CR1_ERRIE                     BIT(7)
  51 #define STM32_I2C_CR1_TCIE                      BIT(6)
  52 #define STM32_I2C_CR1_STOPIE                    BIT(5)
  53 #define STM32_I2C_CR1_NACKIE                    BIT(4)
  54 #define STM32_I2C_CR1_ADDRIE                    BIT(3)
  55 #define STM32_I2C_CR1_RXIE                      BIT(2)
  56 #define STM32_I2C_CR1_TXIE                      BIT(1)
  57 #define STM32_I2C_CR1_PE                        BIT(0)
  58
  59 /* STM32 I2C control 2 */
  60 #define STM32_I2C_CR2_AUTOEND                   BIT(25)
  61 #define STM32_I2C_CR2_RELOAD                    BIT(24)
  62 #define STM32_I2C_CR2_NBYTES_MASK               GENMASK(23, 16)
  63 #define STM32_I2C_CR2_NBYTES(n)                 ((n & 0xff) << 16)
  64 #define STM32_I2C_CR2_NACK                      BIT(15)
  65 #define STM32_I2C_CR2_STOP                      BIT(14)
  66 #define STM32_I2C_CR2_START                     BIT(13)
  67 #define STM32_I2C_CR2_HEAD10R                   BIT(12)
  68 #define STM32_I2C_CR2_ADD10                     BIT(11)
  69 #define STM32_I2C_CR2_RD_WRN                    BIT(10)
  70 #define STM32_I2C_CR2_SADD10_MASK               GENMASK(9, 0)
  71 #define STM32_I2C_CR2_SADD10(n)                 (n & STM32_I2C_CR2_SADD10_MASK)
  72 #define STM32_I2C_CR2_SADD7_MASK                GENMASK(7, 1)
  73 #define STM32_I2C_CR2_SADD7(n)                  ((n & 0x7f) << 1)
  74 #define STM32_I2C_CR2_RESET_MASK                (STM32_I2C_CR2_HEAD10R \
  75                                                 | STM32_I2C_CR2_NBYTES_MASK \
  76                                                 | STM32_I2C_CR2_SADD7_MASK \
  77                                                 | STM32_I2C_CR2_RELOAD \
  78                                                 | STM32_I2C_CR2_RD_WRN)
  79
  80 /* STM32 I2C Interrupt Status */
  81 #define STM32_I2C_ISR_BUSY                      BIT(15)
  82 #define STM32_I2C_ISR_ARLO                      BIT(9)
  83 #define STM32_I2C_ISR_BERR                      BIT(8)
  84 #define STM32_I2C_ISR_TCR                       BIT(7)
  85 #define STM32_I2C_ISR_TC                        BIT(6)
  86 #define STM32_I2C_ISR_STOPF                     BIT(5)
  87 #define STM32_I2C_ISR_NACKF                     BIT(4)
  88 #define STM32_I2C_ISR_ADDR                      BIT(3)
  89 #define STM32_I2C_ISR_RXNE                      BIT(2)
  90 #define STM32_I2C_ISR_TXIS                      BIT(1)
  91 #define STM32_I2C_ISR_TXE                       BIT(0)
  92 #define STM32_I2C_ISR_ERRORS                    (STM32_I2C_ISR_BERR \
  93                                                 | STM32_I2C_ISR_ARLO)
  94
  95 /* STM32 I2C Interrupt Clear */
  96 #define STM32_I2C_ICR_ARLOCF                    BIT(9)
  97 #define STM32_I2C_ICR_BERRCF                    BIT(8)
  98 #define STM32_I2C_ICR_STOPCF                    BIT(5)
  99 #define STM32_I2C_ICR_NACKCF                    BIT(4)
 100
 101 /* STM32 I2C Timing */
 102 #define STM32_I2C_TIMINGR_PRESC(n)              ((n & 0xf) << 28)
 103 #define STM32_I2C_TIMINGR_SCLDEL(n)             ((n & 0xf) << 20)
 104 #define STM32_I2C_TIMINGR_SDADEL(n)             ((n & 0xf) << 16)
 105 #define STM32_I2C_TIMINGR_SCLH(n)               ((n & 0xff) << 8)
 106 #define STM32_I2C_TIMINGR_SCLL(n)               (n & 0xff)
 107
 108 #define STM32_I2C_MAX_LEN                       0xff
 109
 110 #define STM32_I2C_DNF_MAX                       15
 111
 112 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN       50      /* ns */
 113 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX       260     /* ns */
 114
 115 #define STM32_I2C_RISE_TIME_DEFAULT             25      /* ns */
 116 #define STM32_I2C_FALL_TIME_DEFAULT             10      /* ns */
 117
 118 #define STM32_PRESC_MAX                         BIT(4)
 119 #define STM32_SCLDEL_MAX                        BIT(4)
 120 #define STM32_SDADEL_MAX                        BIT(4)
 121 #define STM32_SCLH_MAX                          BIT(8)
 122 #define STM32_SCLL_MAX                          BIT(8)
 123
 124 #define STM32_NSEC_PER_SEC                      1000000000L
 125
 126 /**
 127  * struct stm32_i2c_spec - private i2c specification timing
 128  * @rate: I2C bus speed (Hz)
 129  * @rate_min: 80% of I2C bus speed (Hz)
 130  * @rate_max: 120% of I2C bus speed (Hz)
 131  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 132  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 133  * @hddat_min: Min data hold time (ns)
 134  * @vddat_max: Max data valid time (ns)
 135  * @sudat_min: Min data setup time (ns)
 136  * @l_min: Min low period of the SCL clock (ns)
 137  * @h_min: Min high period of the SCL clock (ns)
 138  */
 139
 140 struct stm32_i2c_spec {
 141         u32 rate;
 142         u32 rate_min;
 143         u32 rate_max;
 144         u32 fall_max;
 145         u32 rise_max;
 146         u32 hddat_min;
 147         u32 vddat_max;
 148         u32 sudat_min;
 149         u32 l_min;
 150         u32 h_min;
 151 };
 152
 153 /**
 154  * struct stm32_i2c_setup - private I2C timing setup parameters
 155  * @speed_freq: I2C speed frequency  (Hz)
 156  * @clock_src: I2C clock source frequency (Hz)
 157  * @rise_time: Rise time (ns)
 158  * @fall_time: Fall time (ns)
 159  * @dnf: value of digital filter to apply
 160  * @analog_filter: Analog filter delay (On/Off)
 161  */
 162 struct stm32_i2c_setup {
 163         u32 speed_freq;
 164         u32 clock_src;
 165         u32 rise_time;
 166         u32 fall_time;
 167         u8 dnf;
 168         bool analog_filter;
 169 };
 170
 171 /**
 172  * struct stm32_i2c_data - driver data for I2C configuration by compatible
 173  * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
 174  */
 175 struct stm32_i2c_data {
 176         u32 fmp_clr_offset;
 177 };
 178
 179 /**
 180  * struct stm32_i2c_timings - private I2C output parameters
 181  * @prec: Prescaler value
 182  * @scldel: Data setup time
 183  * @sdadel: Data hold time
 184  * @sclh: SCL high period (master mode)
 185  * @sclh: SCL low period (master mode)
 186  */
 187 struct stm32_i2c_timings {
 188         struct list_head node;
 189         u8 presc;
 190         u8 scldel;
 191         u8 sdadel;
 192         u8 sclh;
 193         u8 scll;
 194 };
 195
 196 /**
 197  * struct stm32_i2c_priv - private data of the controller
 198  * @regs: I2C registers address
 199  * @clk: hw i2c clock
 200  * @setup: I2C timing setup parameters
 201  * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
 202  * @regmap: holds SYSCFG phandle for Fast Mode Plus bit
 203  * @regmap_sreg: register address for setting Fast Mode Plus bits
 204  * @regmap_creg: register address for clearing Fast Mode Plus bits
 205  * @regmap_mask: mask for Fast Mode Plus bits
 206  * @dnf_dt: value of digital filter requested via dt
 207  */
 208 struct stm32_i2c_priv {
 209         struct stm32_i2c_regs *regs;
 210         struct clk clk;
 211         struct stm32_i2c_setup setup;
 212         u32 speed;
 213         struct regmap *regmap;
 214         u32 regmap_sreg;
 215         u32 regmap_creg;
 216         u32 regmap_mask;
 217         u32 dnf_dt;
 218 };
 219
 220 static const struct stm32_i2c_spec i2c_specs[] = {
 221         /* Standard speed - 100 KHz */
 222         [IC_SPEED_MODE_STANDARD] = {
 223                 .rate = I2C_SPEED_STANDARD_RATE,
 224                 .rate_min = 8000,
 225                 .rate_max = 120000,
 226                 .fall_max = 300,
 227                 .rise_max = 1000,
 228                 .hddat_min = 0,
 229                 .vddat_max = 3450,
 230                 .sudat_min = 250,
 231                 .l_min = 4700,
 232                 .h_min = 4000,
 233         },
 234         /* Fast speed - 400 KHz */
 235         [IC_SPEED_MODE_FAST] = {
 236                 .rate = I2C_SPEED_FAST_RATE,
 237                 .rate_min = 320000,
 238                 .rate_max = 480000,
 239                 .fall_max = 300,
 240                 .rise_max = 300,
 241                 .hddat_min = 0,
 242                 .vddat_max = 900,
 243                 .sudat_min = 100,
 244                 .l_min = 1300,
 245                 .h_min = 600,
 246         },
 247         /* Fast Plus Speed - 1 MHz */
 248         [IC_SPEED_MODE_FAST_PLUS] = {
 249                 .rate = I2C_SPEED_FAST_PLUS_RATE,
 250                 .rate_min = 800000,
 251                 .rate_max = 1200000,
 252                 .fall_max = 100,
 253                 .rise_max = 120,
 254                 .hddat_min = 0,
 255                 .vddat_max = 450,
 256                 .sudat_min = 50,
 257                 .l_min = 500,
 258                 .h_min = 260,
 259         },
 260 };
 261
 262 static const struct stm32_i2c_data stm32f7_data = {
 263         .fmp_clr_offset = 0x00,
 264 };
 265
 266 static const struct stm32_i2c_data stm32mp15_data = {
 267         .fmp_clr_offset = 0x40,
 268 };
 269
 270 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
 271 {
 272         struct stm32_i2c_regs *regs = i2c_priv->regs;
 273         u32 status = readl(&regs->isr);
 274
 275         if (status & STM32_I2C_ISR_BUSY)
 276                 return -EBUSY;
 277
 278         return 0;
 279 }
 280
 281 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
 282                                     struct i2c_msg *msg, bool stop)
 283 {
 284         struct stm32_i2c_regs *regs = i2c_priv->regs;
 285         u32 cr2 = readl(&regs->cr2);
 286
 287         /* Set transfer direction */
 288         cr2 &= ~STM32_I2C_CR2_RD_WRN;
 289         if (msg->flags & I2C_M_RD)
 290                 cr2 |= STM32_I2C_CR2_RD_WRN;
 291
 292         /* Set slave address */
 293         cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
 294         if (msg->flags & I2C_M_TEN) {
 295                 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
 296                 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
 297                 cr2 |= STM32_I2C_CR2_ADD10;
 298         } else {
 299                 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
 300                 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
 301         }
 302
 303         /* Set nb bytes to transfer and reload or autoend bits */
 304         cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
 305                  STM32_I2C_CR2_AUTOEND);
 306         if (msg->len > STM32_I2C_MAX_LEN) {
 307                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 308                 cr2 |= STM32_I2C_CR2_RELOAD;
 309         } else {
 310                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 311         }
 312
 313         /* Write configurations register */
 314         writel(cr2, &regs->cr2);
 315
 316         /* START/ReSTART generation */
 317         setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
 318 }
 319
 320 /*
 321  * RELOAD mode must be selected if total number of data bytes to be
 322  * sent is greater than MAX_LEN
 323  */
 324
 325 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
 326                                     struct i2c_msg *msg, bool stop)
 327 {
 328         struct stm32_i2c_regs *regs = i2c_priv->regs;
 329         u32 cr2 = readl(&regs->cr2);
 330
 331         cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
 332
 333         if (msg->len > STM32_I2C_MAX_LEN) {
 334                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 335         } else {
 336                 cr2 &= ~STM32_I2C_CR2_RELOAD;
 337                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 338         }
 339
 340         writel(cr2, &regs->cr2);
 341 }
 342
 343 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
 344                                 u32 flags, u32 *status)
 345 {
 346         struct stm32_i2c_regs *regs = i2c_priv->regs;
 347         u32 time_start = get_timer(0);
 348
 349         *status = readl(&regs->isr);
 350         while (!(*status & flags)) {
 351                 if (get_timer(time_start) > CONFIG_SYS_HZ) {
 352                         log_debug("i2c timeout\n");
 353                         return -ETIMEDOUT;
 354                 }
 355
 356                 *status = readl(&regs->isr);
 357         }
 358
 359         return 0;
 360 }
 361
 362 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
 363 {
 364         struct stm32_i2c_regs *regs = i2c_priv->regs;
 365         u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
 366                    STM32_I2C_ISR_STOPF;
 367         u32 status;
 368         int ret;
 369
 370         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 371         if (ret)
 372                 return ret;
 373
 374         if (status & STM32_I2C_ISR_BERR) {
 375                 log_debug("Bus error\n");
 376
 377                 /* Clear BERR flag */
 378                 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
 379
 380                 return -EIO;
 381         }
 382
 383         if (status & STM32_I2C_ISR_ARLO) {
 384                 log_debug("Arbitration lost\n");
 385
 386                 /* Clear ARLO flag */
 387                 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
 388
 389                 return -EAGAIN;
 390         }
 391
 392         if (status & STM32_I2C_ISR_NACKF) {
 393                 log_debug("Receive NACK\n");
 394
 395                 /* Clear NACK flag */
 396                 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
 397
 398                 /* Wait until STOPF flag is set */
 399                 mask = STM32_I2C_ISR_STOPF;
 400                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 401                 if (ret)
 402                         return ret;
 403
 404                 ret = -EIO;
 405         }
 406
 407         if (status & STM32_I2C_ISR_STOPF) {
 408                 /* Clear STOP flag */
 409                 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
 410
 411                 /* Clear control register 2 */
 412                 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
 413         }
 414
 415         return ret;
 416 }
 417
 418 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
 419                                   struct i2c_msg *msg, bool stop)
 420 {
 421         struct stm32_i2c_regs *regs = i2c_priv->regs;
 422         u32 status;
 423         u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 424                    STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 425         int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 426                           STM32_I2C_MAX_LEN : msg->len;
 427         int ret = 0;
 428
 429         /* Add errors */
 430         mask |= STM32_I2C_ISR_ERRORS;
 431
 432         stm32_i2c_message_start(i2c_priv, msg, stop);
 433
 434         while (msg->len) {
 435                 /*
 436                  * Wait until TXIS/NACKF/BERR/ARLO flags or
 437                  * RXNE/BERR/ARLO flags are set
 438                  */
 439                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 440                 if (ret)
 441                         break;
 442
 443                 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
 444                         break;
 445
 446                 if (status & STM32_I2C_ISR_RXNE) {
 447                         *msg->buf++ = readb(&regs->rxdr);
 448                         msg->len--;
 449                         bytes_to_rw--;
 450                 }
 451
 452                 if (status & STM32_I2C_ISR_TXIS) {
 453                         writeb(*msg->buf++, &regs->txdr);
 454                         msg->len--;
 455                         bytes_to_rw--;
 456                 }
 457
 458                 if (!bytes_to_rw && msg->len) {
 459                         /* Wait until TCR flag is set */
 460                         mask = STM32_I2C_ISR_TCR;
 461                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 462                         if (ret)
 463                                 break;
 464
 465                         bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 466                                       STM32_I2C_MAX_LEN : msg->len;
 467                         mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 468                                STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 469
 470                         stm32_i2c_handle_reload(i2c_priv, msg, stop);
 471                 } else if (!bytes_to_rw) {
 472                         /* Wait until TC flag is set */
 473                         mask = STM32_I2C_ISR_TC;
 474                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 475                         if (ret)
 476                                 break;
 477
 478                         if (!stop)
 479                                 /* Message sent, new message has to be sent */
 480                                 return 0;
 481                 }
 482         }
 483
 484         /* End of transfer, send stop condition */
 485         mask = STM32_I2C_CR2_STOP;
 486         setbits_le32(&regs->cr2, mask);
 487
 488         return stm32_i2c_check_end_of_message(i2c_priv);
 489 }
 490
 491 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 492                           int nmsgs)
 493 {
 494         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 495         int ret;
 496
 497         ret = stm32_i2c_check_device_busy(i2c_priv);
 498         if (ret)
 499                 return ret;
 500
 501         for (; nmsgs > 0; nmsgs--, msg++) {
 502                 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
 503                 if (ret)
 504                         return ret;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
 511                                        const struct stm32_i2c_spec *specs,
 512                                        struct list_head *solutions)
 513 {
 514         struct stm32_i2c_timings *v;
 515         u32 p_prev = STM32_PRESC_MAX;
 516         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 517                                        setup->clock_src);
 518         u32 af_delay_min, af_delay_max;
 519         u16 p, l, a;
 520         int sdadel_min, sdadel_max, scldel_min;
 521         int ret = 0;
 522
 523         af_delay_min = setup->analog_filter ?
 524                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 525         af_delay_max = setup->analog_filter ?
 526                        STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
 527
 528         sdadel_min = specs->hddat_min + setup->fall_time -
 529                      af_delay_min - (setup->dnf + 3) * i2cclk;
 530
 531         sdadel_max = specs->vddat_max - setup->rise_time -
 532                      af_delay_max - (setup->dnf + 4) * i2cclk;
 533
 534         scldel_min = setup->rise_time + specs->sudat_min;
 535
 536         if (sdadel_min < 0)
 537                 sdadel_min = 0;
 538         if (sdadel_max < 0)
 539                 sdadel_max = 0;
 540
 541         log_debug("SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 542                   sdadel_min, sdadel_max, scldel_min);
 543
 544         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 545         for (p = 0; p < STM32_PRESC_MAX; p++) {
 546                 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
 547                         int scldel = (l + 1) * (p + 1) * i2cclk;
 548
 549                         if (scldel < scldel_min)
 550                                 continue;
 551
 552                         for (a = 0; a < STM32_SDADEL_MAX; a++) {
 553                                 int sdadel = (a * (p + 1) + 1) * i2cclk;
 554
 555                                 if (((sdadel >= sdadel_min) &&
 556                                      (sdadel <= sdadel_max)) &&
 557                                     (p != p_prev)) {
 558                                         v = calloc(1, sizeof(*v));
 559                                         if (!v)
 560                                                 return -ENOMEM;
 561
 562                                         v->presc = p;
 563                                         v->scldel = l;
 564                                         v->sdadel = a;
 565                                         p_prev = p;
 566
 567                                         list_add_tail(&v->node, solutions);
 568                                         break;
 569                                 }
 570                         }
 571
 572                         if (p_prev == p)
 573                                 break;
 574                 }
 575         }
 576
 577         if (list_empty(solutions)) {
 578                 log_err("no Prescaler solution\n");
 579                 ret = -EPERM;
 580         }
 581
 582         return ret;
 583 }
 584
 585 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
 586                                      const struct stm32_i2c_spec *specs,
 587                                      struct list_head *solutions,
 588                                      struct stm32_i2c_timings *s)
 589 {
 590         struct stm32_i2c_timings *v;
 591         u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 592                                        setup->speed_freq);
 593         u32 clk_error_prev = i2cbus;
 594         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 595                                        setup->clock_src);
 596         u32 clk_min, clk_max;
 597         u32 af_delay_min;
 598         u32 dnf_delay;
 599         u32 tsync;
 600         u16 l, h;
 601         bool sol_found = false;
 602         int ret = 0;
 603
 604         af_delay_min = setup->analog_filter ?
 605                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 606         dnf_delay = setup->dnf * i2cclk;
 607
 608         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 609         clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
 610         clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
 611
 612         /*
 613          * Among Prescaler possibilities discovered above figures out SCL Low
 614          * and High Period. Provided:
 615          * - SCL Low Period has to be higher than Low Period of the SCL Clock
 616          *   defined by I2C Specification. I2C Clock has to be lower than
 617          *   (SCL Low Period - Analog/Digital filters) / 4.
 618          * - SCL High Period has to be lower than High Period of the SCL Clock
 619          *   defined by I2C Specification
 620          * - I2C Clock has to be lower than SCL High Period
 621          */
 622         list_for_each_entry(v, solutions, node) {
 623                 u32 prescaler = (v->presc + 1) * i2cclk;
 624
 625                 for (l = 0; l < STM32_SCLL_MAX; l++) {
 626                         u32 tscl_l = (l + 1) * prescaler + tsync;
 627
 628                         if (tscl_l < specs->l_min ||
 629                             (i2cclk >=
 630                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 631                                 continue;
 632                         }
 633
 634                         for (h = 0; h < STM32_SCLH_MAX; h++) {
 635                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 636                                 u32 tscl = tscl_l + tscl_h +
 637                                            setup->rise_time + setup->fall_time;
 638
 639                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 640                                     (tscl_h >= specs->h_min) &&
 641                                     (i2cclk < tscl_h)) {
 642                                         u32 clk_error;
 643
 644                                         if (tscl > i2cbus)
 645                                                 clk_error = tscl - i2cbus;
 646                                         else
 647                                                 clk_error = i2cbus - tscl;
 648
 649                                         if (clk_error < clk_error_prev) {
 650                                                 clk_error_prev = clk_error;
 651                                                 v->scll = l;
 652                                                 v->sclh = h;
 653                                                 sol_found = true;
 654                                                 memcpy(s, v, sizeof(*s));
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660
 661         if (!sol_found) {
 662                 log_err("no solution at all\n");
 663                 ret = -EPERM;
 664         }
 665
 666         return ret;
 667 }
 668
 669 static const struct stm32_i2c_spec *get_specs(u32 rate)
 670 {
 671         unsigned int i;
 672
 673         for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
 674                 if (rate <= i2c_specs[i].rate)
 675                         return &i2c_specs[i];
 676
 677         /* NOT REACHED */
 678         return ERR_PTR(-EINVAL);
 679 }
 680
 681 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
 682                                     struct stm32_i2c_setup *setup,
 683                                     struct stm32_i2c_timings *output)
 684 {
 685         const struct stm32_i2c_spec *specs;
 686         struct stm32_i2c_timings *v, *_v;
 687         struct list_head solutions;
 688         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, setup->clock_src);
 689         int ret;
 690
 691         specs = get_specs(setup->speed_freq);
 692         if (specs == ERR_PTR(-EINVAL)) {
 693                 log_err("speed out of bound {%d}\n",
 694                         setup->speed_freq);
 695                 return -EINVAL;
 696         }
 697
 698         if (setup->rise_time > specs->rise_max ||
 699             setup->fall_time > specs->fall_max) {
 700                 log_err("timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 701                         setup->rise_time, specs->rise_max,
 702                         setup->fall_time, specs->fall_max);
 703                 return -EINVAL;
 704         }
 705
 706         /*  Analog and Digital Filters */
 707         setup->dnf = DIV_ROUND_CLOSEST(i2c_priv->dnf_dt, i2cclk);
 708         if (setup->dnf > STM32_I2C_DNF_MAX) {
 709                 log_err("DNF out of bound %d/%d\n",
 710                         setup->dnf, STM32_I2C_DNF_MAX);
 711                 return -EINVAL;
 712         }
 713
 714         INIT_LIST_HEAD(&solutions);
 715         ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
 716         if (ret)
 717                 goto exit;
 718
 719         ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
 720         if (ret)
 721                 goto exit;
 722
 723         log_debug("Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 724                   output->presc,
 725                   output->scldel, output->sdadel,
 726                   output->scll, output->sclh);
 727
 728 exit:
 729         /* Release list and memory */
 730         list_for_each_entry_safe(v, _v, &solutions, node) {
 731                 list_del(&v->node);
 732                 free(v);
 733         }
 734
 735         return ret;
 736 }
 737
 738 static u32 get_lower_rate(u32 rate)
 739 {
 740         int i;
 741
 742         for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
 743                 if (rate > i2c_specs[i].rate)
 744                         return i2c_specs[i].rate;
 745
 746         return i2c_specs[0].rate;
 747 }
 748
 749 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
 750                                   struct stm32_i2c_timings *timing)
 751 {
 752         struct stm32_i2c_setup *setup = &i2c_priv->setup;
 753         int ret = 0;
 754
 755         setup->speed_freq = i2c_priv->speed;
 756         setup->clock_src = clk_get_rate(&i2c_priv->clk);
 757
 758         if (!setup->clock_src) {
 759                 log_err("clock rate is 0\n");
 760                 return -EINVAL;
 761         }
 762
 763         do {
 764                 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
 765                 if (ret) {
 766                         log_debug("failed to compute I2C timings.\n");
 767                         if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
 768                                 setup->speed_freq =
 769                                         get_lower_rate(setup->speed_freq);
 770                                 log_debug("downgrade I2C Speed Freq to (%i)\n",
 771                                           setup->speed_freq);
 772                         } else {
 773                                 break;
 774                         }
 775                 }
 776         } while (ret);
 777
 778         if (ret) {
 779                 log_err("impossible to compute I2C timings.\n");
 780                 return ret;
 781         }
 782
 783         log_debug("I2C Freq(%i), Clk Source(%i)\n",
 784                   setup->speed_freq, setup->clock_src);
 785         log_debug("I2C Rise(%i) and Fall(%i) Time\n",
 786                   setup->rise_time, setup->fall_time);
 787         log_debug("I2C Analog Filter(%s), DNF(%i)\n",
 788                   setup->analog_filter ? "On" : "Off", setup->dnf);
 789
 790         i2c_priv->speed = setup->speed_freq;
 791
 792         return 0;
 793 }
 794
 795 static int stm32_i2c_write_fm_plus_bits(struct stm32_i2c_priv *i2c_priv)
 796 {
 797         int ret;
 798         bool enable = i2c_priv->speed > I2C_SPEED_FAST_RATE;
 799
 800         /* Optional */
 801         if (IS_ERR_OR_NULL(i2c_priv->regmap))
 802                 return 0;
 803
 804         if (i2c_priv->regmap_sreg == i2c_priv->regmap_creg)
 805                 ret = regmap_update_bits(i2c_priv->regmap,
 806                                          i2c_priv->regmap_sreg,
 807                                          i2c_priv->regmap_mask,
 808                                          enable ? i2c_priv->regmap_mask : 0);
 809         else
 810                 ret = regmap_write(i2c_priv->regmap,
 811                                    enable ? i2c_priv->regmap_sreg :
 812                                             i2c_priv->regmap_creg,
 813                                    i2c_priv->regmap_mask);
 814
 815         return ret;
 816 }
 817
 818 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
 819 {
 820         struct stm32_i2c_regs *regs = i2c_priv->regs;
 821         struct stm32_i2c_timings t;
 822         int ret;
 823         u32 timing = 0;
 824
 825         ret = stm32_i2c_setup_timing(i2c_priv, &t);
 826         if (ret)
 827                 return ret;
 828
 829         /* Disable I2C */
 830         clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 831
 832         /* Setup Fast mode plus if necessary */
 833         ret = stm32_i2c_write_fm_plus_bits(i2c_priv);
 834         if (ret)
 835                 return ret;
 836
 837         /* Timing settings */
 838         timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
 839         timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
 840         timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
 841         timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
 842         timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
 843         writel(timing, &regs->timingr);
 844
 845         /* Enable I2C */
 846         if (i2c_priv->setup.analog_filter)
 847                 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 848         else
 849                 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 850
 851         /* Program the Digital Filter */
 852         clrsetbits_le32(&regs->cr1, STM32_I2C_CR1_DNF_MASK,
 853                         STM32_I2C_CR1_DNF(i2c_priv->setup.dnf));
 854
 855         setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 856
 857         return 0;
 858 }
 859
 860 static int stm32_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 861 {
 862         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 863
 864         if (speed > I2C_SPEED_FAST_PLUS_RATE) {
 865                 dev_dbg(dev, "Speed %d not supported\n", speed);
 866                 return -EINVAL;
 867         }
 868
 869         i2c_priv->speed = speed;
 870
 871         return stm32_i2c_hw_config(i2c_priv);
 872 }
 873
 874 static int stm32_i2c_probe(struct udevice *dev)
 875 {
 876         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 877         struct reset_ctl reset_ctl;
 878         fdt_addr_t addr;
 879         int ret;
 880
 881         addr = dev_read_addr(dev);
 882         if (addr == FDT_ADDR_T_NONE)
 883                 return -EINVAL;
 884
 885         i2c_priv->regs = (struct stm32_i2c_regs *)addr;
 886
 887         ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
 888         if (ret)
 889                 return ret;
 890
 891         ret = clk_enable(&i2c_priv->clk);
 892         if (ret)
 893                 goto clk_free;
 894
 895         ret = reset_get_by_index(dev, 0, &reset_ctl);
 896         if (ret)
 897                 goto clk_disable;
 898
 899         reset_assert(&reset_ctl);
 900         udelay(2);
 901         reset_deassert(&reset_ctl);
 902
 903         return 0;
 904
 905 clk_disable:
 906         clk_disable(&i2c_priv->clk);
 907 clk_free:
 908         clk_free(&i2c_priv->clk);
 909
 910         return ret;
 911 }
 912
 913 static int stm32_of_to_plat(struct udevice *dev)
 914 {
 915         const struct stm32_i2c_data *data;
 916         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 917         u32 rise_time, fall_time;
 918         int ret;
 919
 920         data = (const struct stm32_i2c_data *)dev_get_driver_data(dev);
 921         if (!data)
 922                 return -EINVAL;
 923
 924         rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns",
 925                                          STM32_I2C_RISE_TIME_DEFAULT);
 926
 927         fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns",
 928                                          STM32_I2C_FALL_TIME_DEFAULT);
 929
 930         i2c_priv->dnf_dt = dev_read_u32_default(dev, "i2c-digital-filter-width-ns", 0);
 931         if (!dev_read_bool(dev, "i2c-digital-filter"))
 932                 i2c_priv->dnf_dt = 0;
 933
 934         i2c_priv->setup.analog_filter = dev_read_bool(dev, "i2c-analog-filter");
 935
 936         /* Optional */
 937         i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev,
 938                                                            "st,syscfg-fmp");
 939         if (!IS_ERR(i2c_priv->regmap)) {
 940                 u32 fmp[3];
 941
 942                 ret = dev_read_u32_array(dev, "st,syscfg-fmp", fmp, 3);
 943                 if (ret)
 944                         return ret;
 945
 946                 i2c_priv->regmap_sreg = fmp[1];
 947                 i2c_priv->regmap_creg = fmp[1] + data->fmp_clr_offset;
 948                 i2c_priv->regmap_mask = fmp[2];
 949         }
 950
 951         return 0;
 952 }
 953
 954 static const struct dm_i2c_ops stm32_i2c_ops = {
 955         .xfer = stm32_i2c_xfer,
 956         .set_bus_speed = stm32_i2c_set_bus_speed,
 957 };
 958
 959 static const struct udevice_id stm32_i2c_of_match[] = {
 960         { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data },
 961         { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data },
 962         {}
 963 };
 964
 965 U_BOOT_DRIVER(stm32f7_i2c) = {
 966         .name = "stm32f7-i2c",
 967         .id = UCLASS_I2C,
 968         .of_match = stm32_i2c_of_match,
 969         .of_to_plat = stm32_of_to_plat,
 970         .probe = stm32_i2c_probe,
 971         .priv_auto      = sizeof(struct stm32_i2c_priv),
 972         .ops = &stm32_i2c_ops,
 973 };