1 // SPDX-License-Identifier: GPL-2.0+
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * Changes for multibus/multiadapter I2C support.
7 * (C) Copyright 2001, 2002
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
11 * vanbaren@cideas.com. It was heavily influenced by LiMon, written by
14 * NOTE: This driver should be converted to driver model before June 2017.
15 * Please see doc/driver-model/i2c-howto.rst for instructions.
19 #if defined(CONFIG_AT91FAMILY)
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/at91_pio.h>
23 #ifdef CONFIG_ATMEL_LEGACY
24 #include <asm/arch/gpio.h>
28 #include <asm/global_data.h>
29 #include <linux/delay.h>
31 #if defined(CONFIG_SOFT_I2C_GPIO_SCL)
32 # include <asm/gpio.h>
34 # ifndef I2C_GPIO_SYNC
35 # define I2C_GPIO_SYNC
41 gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \
42 gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \
47 # define I2C_ACTIVE do { } while (0)
51 # define I2C_TRISTATE do { } while (0)
55 # define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA)
59 # define I2C_SDA(bit) \
62 gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \
64 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \
70 # define I2C_SCL(bit) \
72 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \
78 # define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
83 /* #define DEBUG_I2C */
85 DECLARE_GLOBAL_DATA_PTR;
87 #ifndef I2C_SOFT_DECLARATIONS
88 # define I2C_SOFT_DECLARATIONS
91 #if !defined(CONFIG_SYS_I2C_SOFT_SPEED)
92 #define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
94 #if !defined(CONFIG_SYS_I2C_SOFT_SLAVE)
95 #define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
98 /*-----------------------------------------------------------------------
103 #define I2C_ACK 0 /* PD_SDA level to ack a byte */
104 #define I2C_NOACK 1 /* PD_SDA level to noack a byte */
108 #define PRINTD(fmt,args...) do { \
109 printf (fmt ,##args); \
112 #define PRINTD(fmt,args...)
115 /*-----------------------------------------------------------------------
118 #if !defined(CONFIG_SYS_I2C_INIT_BOARD)
119 static void send_reset (void);
121 static void send_start (void);
122 static void send_stop (void);
123 static void send_ack (int);
124 static int write_byte (uchar byte);
125 static uchar read_byte (int);
127 #if !defined(CONFIG_SYS_I2C_INIT_BOARD)
128 /*-----------------------------------------------------------------------
129 * Send a reset sequence consisting of 9 clocks with the data signal high
130 * to clock any confused device back into an idle state. Also send a
131 * <stop> at the end of the sequence for belts & suspenders.
133 static void send_reset(void)
135 I2C_SOFT_DECLARATIONS /* intentional without ';' */
144 for(j = 0; j < 9; j++) {
157 /*-----------------------------------------------------------------------
158 * START: High -> Low on SDA while SCL is High
160 static void send_start(void)
162 I2C_SOFT_DECLARATIONS /* intentional without ';' */
174 /*-----------------------------------------------------------------------
175 * STOP: Low -> High on SDA while SCL is High
177 static void send_stop(void)
179 I2C_SOFT_DECLARATIONS /* intentional without ';' */
193 /*-----------------------------------------------------------------------
194 * ack should be I2C_ACK or I2C_NOACK
196 static void send_ack(int ack)
198 I2C_SOFT_DECLARATIONS /* intentional without ';' */
212 /*-----------------------------------------------------------------------
213 * Send 8 bits and look for an acknowledgement.
215 static int write_byte(uchar data)
217 I2C_SOFT_DECLARATIONS /* intentional without ';' */
222 for(j = 0; j < 8; j++) {
225 I2C_SDA(data & 0x80);
235 * Look for an <ACK>(negative logic) and return it.
250 return(nack); /* not a nack is an ack */
253 /*-----------------------------------------------------------------------
254 * if ack == I2C_ACK, ACK the byte so can continue reading, else
255 * send I2C_NOACK to end the read.
257 static uchar read_byte(int ack)
259 I2C_SOFT_DECLARATIONS /* intentional without ';' */
264 * Read 8 bits, MSB first.
269 for(j = 0; j < 8; j++) {
283 /*-----------------------------------------------------------------------
286 static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
288 #if defined(CONFIG_SYS_I2C_INIT_BOARD)
289 /* call board specific i2c bus reset routine before accessing the */
290 /* environment, which might be in a chip on that bus. For details */
291 /* about this problem see doc/I2C_Edge_Conditions. */
295 * WARNING: Do NOT save speed in a static variable: if the
296 * I2C routines are called before RAM is initialized (to read
297 * the DIMM SPD, for instance), RAM won't be usable and your
304 /*-----------------------------------------------------------------------
305 * Probe to see if a chip is present. Also good for checking for the
306 * completion of EEPROM writes since the chip stops responding until
307 * the write completes (typically 10mSec).
309 static int soft_i2c_probe(struct i2c_adapter *adap, uint8_t addr)
314 * perform 1 byte write transaction with just address byte
318 rc = write_byte ((addr << 1) | 0);
324 /*-----------------------------------------------------------------------
327 static int soft_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
328 int alen, uchar *buffer, int len)
331 PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
332 chip, addr, alen, buffer, len);
334 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
336 * EEPROM chips that implement "address overflow" are ones
337 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
338 * address and the extra bits end up in the "chip address"
339 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
340 * four 256 byte chips.
342 * Note that we consider the length of the address field to
343 * still be one byte because the extra address bits are
344 * hidden in the chip address.
346 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
348 PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
353 * Do the addressing portion of a write cycle to set the
354 * chip's address pointer. If the address length is zero,
355 * don't do the normal write cycle to set the address pointer,
356 * there is no address pointer in this chip.
360 if(write_byte(chip << 1)) { /* write cycle */
362 PRINTD("i2c_read, no chip responded %02X\n", chip);
365 shift = (alen-1) * 8;
367 if(write_byte(addr >> shift)) {
368 PRINTD("i2c_read, address not <ACK>ed\n");
374 /* Some I2C chips need a stop/start sequence here,
375 * other chips don't work with a full stop and need
376 * only a start. Default behaviour is to send the
377 * stop/start sequence.
379 #ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
387 * Send the chip address again, this time for a read cycle.
388 * Then read the data. On the last byte, we do a NACK instead
389 * of an ACK(len == 0) to terminate the read.
391 write_byte((chip << 1) | 1); /* read cycle */
393 *buffer++ = read_byte(len == 0);
399 /*-----------------------------------------------------------------------
402 static int soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
403 int alen, uchar *buffer, int len)
405 int shift, failures = 0;
407 PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
408 chip, addr, alen, buffer, len);
411 if(write_byte(chip << 1)) { /* write cycle */
413 PRINTD("i2c_write, no chip responded %02X\n", chip);
416 shift = (alen-1) * 8;
418 if(write_byte(addr >> shift)) {
419 PRINTD("i2c_write, address not <ACK>ed\n");
426 if(write_byte(*buffer++)) {
435 * Register soft i2c adapters
437 U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe,
438 soft_i2c_read, soft_i2c_write, NULL,
439 CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,