1 // SPDX-License-Identifier: GPL-2.0+
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * Changes for multibus/multiadapter I2C support.
7 * (C) Copyright 2001, 2002
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
11 * vanbaren@cideas.com. It was heavily influenced by LiMon, written by
14 * NOTE: This driver should be converted to driver model before June 2017.
15 * Please see doc/driver-model/i2c-howto.txt for instructions.
19 #if defined(CONFIG_AT91FAMILY)
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/at91_pio.h>
23 #ifdef CONFIG_ATMEL_LEGACY
24 #include <asm/arch/gpio.h>
29 #if defined(CONFIG_SOFT_I2C_GPIO_SCL)
30 # include <asm/gpio.h>
32 # ifndef I2C_GPIO_SYNC
33 # define I2C_GPIO_SYNC
39 gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \
40 gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \
45 # define I2C_ACTIVE do { } while (0)
49 # define I2C_TRISTATE do { } while (0)
53 # define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA)
57 # define I2C_SDA(bit) \
60 gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \
62 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \
68 # define I2C_SCL(bit) \
70 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \
76 # define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
81 /* #define DEBUG_I2C */
83 DECLARE_GLOBAL_DATA_PTR;
85 #ifndef I2C_SOFT_DECLARATIONS
86 # define I2C_SOFT_DECLARATIONS
89 #if !defined(CONFIG_SYS_I2C_SOFT_SPEED)
90 #define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
92 #if !defined(CONFIG_SYS_I2C_SOFT_SLAVE)
93 #define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
96 /*-----------------------------------------------------------------------
101 #define I2C_ACK 0 /* PD_SDA level to ack a byte */
102 #define I2C_NOACK 1 /* PD_SDA level to noack a byte */
106 #define PRINTD(fmt,args...) do { \
107 printf (fmt ,##args); \
110 #define PRINTD(fmt,args...)
113 /*-----------------------------------------------------------------------
116 #if !defined(CONFIG_SYS_I2C_INIT_BOARD)
117 static void send_reset (void);
119 static void send_start (void);
120 static void send_stop (void);
121 static void send_ack (int);
122 static int write_byte (uchar byte);
123 static uchar read_byte (int);
125 #if !defined(CONFIG_SYS_I2C_INIT_BOARD)
126 /*-----------------------------------------------------------------------
127 * Send a reset sequence consisting of 9 clocks with the data signal high
128 * to clock any confused device back into an idle state. Also send a
129 * <stop> at the end of the sequence for belts & suspenders.
131 static void send_reset(void)
133 I2C_SOFT_DECLARATIONS /* intentional without ';' */
142 for(j = 0; j < 9; j++) {
155 /*-----------------------------------------------------------------------
156 * START: High -> Low on SDA while SCL is High
158 static void send_start(void)
160 I2C_SOFT_DECLARATIONS /* intentional without ';' */
172 /*-----------------------------------------------------------------------
173 * STOP: Low -> High on SDA while SCL is High
175 static void send_stop(void)
177 I2C_SOFT_DECLARATIONS /* intentional without ';' */
191 /*-----------------------------------------------------------------------
192 * ack should be I2C_ACK or I2C_NOACK
194 static void send_ack(int ack)
196 I2C_SOFT_DECLARATIONS /* intentional without ';' */
210 /*-----------------------------------------------------------------------
211 * Send 8 bits and look for an acknowledgement.
213 static int write_byte(uchar data)
215 I2C_SOFT_DECLARATIONS /* intentional without ';' */
220 for(j = 0; j < 8; j++) {
223 I2C_SDA(data & 0x80);
233 * Look for an <ACK>(negative logic) and return it.
248 return(nack); /* not a nack is an ack */
251 /*-----------------------------------------------------------------------
252 * if ack == I2C_ACK, ACK the byte so can continue reading, else
253 * send I2C_NOACK to end the read.
255 static uchar read_byte(int ack)
257 I2C_SOFT_DECLARATIONS /* intentional without ';' */
262 * Read 8 bits, MSB first.
267 for(j = 0; j < 8; j++) {
281 /*-----------------------------------------------------------------------
284 static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
286 #if defined(CONFIG_SYS_I2C_INIT_BOARD)
287 /* call board specific i2c bus reset routine before accessing the */
288 /* environment, which might be in a chip on that bus. For details */
289 /* about this problem see doc/I2C_Edge_Conditions. */
293 * WARNING: Do NOT save speed in a static variable: if the
294 * I2C routines are called before RAM is initialized (to read
295 * the DIMM SPD, for instance), RAM won't be usable and your
302 /*-----------------------------------------------------------------------
303 * Probe to see if a chip is present. Also good for checking for the
304 * completion of EEPROM writes since the chip stops responding until
305 * the write completes (typically 10mSec).
307 static int soft_i2c_probe(struct i2c_adapter *adap, uint8_t addr)
312 * perform 1 byte write transaction with just address byte
316 rc = write_byte ((addr << 1) | 0);
322 /*-----------------------------------------------------------------------
325 static int soft_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
326 int alen, uchar *buffer, int len)
329 PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
330 chip, addr, alen, buffer, len);
332 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
334 * EEPROM chips that implement "address overflow" are ones
335 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
336 * address and the extra bits end up in the "chip address"
337 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
338 * four 256 byte chips.
340 * Note that we consider the length of the address field to
341 * still be one byte because the extra address bits are
342 * hidden in the chip address.
344 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
346 PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
351 * Do the addressing portion of a write cycle to set the
352 * chip's address pointer. If the address length is zero,
353 * don't do the normal write cycle to set the address pointer,
354 * there is no address pointer in this chip.
358 if(write_byte(chip << 1)) { /* write cycle */
360 PRINTD("i2c_read, no chip responded %02X\n", chip);
363 shift = (alen-1) * 8;
365 if(write_byte(addr >> shift)) {
366 PRINTD("i2c_read, address not <ACK>ed\n");
372 /* Some I2C chips need a stop/start sequence here,
373 * other chips don't work with a full stop and need
374 * only a start. Default behaviour is to send the
375 * stop/start sequence.
377 #ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
385 * Send the chip address again, this time for a read cycle.
386 * Then read the data. On the last byte, we do a NACK instead
387 * of an ACK(len == 0) to terminate the read.
389 write_byte((chip << 1) | 1); /* read cycle */
391 *buffer++ = read_byte(len == 0);
397 /*-----------------------------------------------------------------------
400 static int soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
401 int alen, uchar *buffer, int len)
403 int shift, failures = 0;
405 PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
406 chip, addr, alen, buffer, len);
409 if(write_byte(chip << 1)) { /* write cycle */
411 PRINTD("i2c_write, no chip responded %02X\n", chip);
414 shift = (alen-1) * 8;
416 if(write_byte(addr >> shift)) {
417 PRINTD("i2c_write, address not <ACK>ed\n");
424 if(write_byte(*buffer++)) {
433 * Register soft i2c adapters
435 U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe,
436 soft_i2c_read, soft_i2c_write, NULL,
437 CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
439 #if defined(I2C_SOFT_DECLARATIONS2)
440 U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe,
441 soft_i2c_read, soft_i2c_write, NULL,
442 CONFIG_SYS_I2C_SOFT_SPEED_2,
443 CONFIG_SYS_I2C_SOFT_SLAVE_2,
446 #if defined(I2C_SOFT_DECLARATIONS3)
447 U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe,
448 soft_i2c_read, soft_i2c_write, NULL,
449 CONFIG_SYS_I2C_SOFT_SPEED_3,
450 CONFIG_SYS_I2C_SOFT_SLAVE_3,
453 #if defined(I2C_SOFT_DECLARATIONS4)
454 U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe,
455 soft_i2c_read, soft_i2c_write, NULL,
456 CONFIG_SYS_I2C_SOFT_SPEED_4,
457 CONFIG_SYS_I2C_SOFT_SLAVE_4,
460 #if defined(I2C_SOFT_DECLARATIONS5)
461 U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe,
462 soft_i2c_read, soft_i2c_write, NULL,
463 CONFIG_SYS_I2C_SOFT_SPEED_5,
464 CONFIG_SYS_I2C_SOFT_SLAVE_5,
467 #if defined(I2C_SOFT_DECLARATIONS6)
468 U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe,
469 soft_i2c_read, soft_i2c_write, NULL,
470 CONFIG_SYS_I2C_SOFT_SPEED_6,
471 CONFIG_SYS_I2C_SOFT_SLAVE_6,
474 #if defined(I2C_SOFT_DECLARATIONS7)
475 U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe,
476 soft_i2c_read, soft_i2c_write, NULL,
477 CONFIG_SYS_I2C_SOFT_SPEED_7,
478 CONFIG_SYS_I2C_SOFT_SLAVE_7,
481 #if defined(I2C_SOFT_DECLARATIONS8)
482 U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe,
483 soft_i2c_read, soft_i2c_write, NULL,
484 CONFIG_SYS_I2C_SOFT_SPEED_8,
485 CONFIG_SYS_I2C_SOFT_SLAVE_8,
488 #if defined(I2C_SOFT_DECLARATIONS9)
489 U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe,
490 soft_i2c_read, soft_i2c_write, NULL,
491 CONFIG_SYS_I2C_SOFT_SPEED_9,
492 CONFIG_SYS_I2C_SOFT_SLAVE_9,
495 #if defined(I2C_SOFT_DECLARATIONS10)
496 U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe,
497 soft_i2c_read, soft_i2c_write, NULL,
498 CONFIG_SYS_I2C_SOFT_SPEED_10,
499 CONFIG_SYS_I2C_SOFT_SLAVE_10,
502 #if defined(I2C_SOFT_DECLARATIONS11)
503 U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe,
504 soft_i2c_read, soft_i2c_write, NULL,
505 CONFIG_SYS_I2C_SOFT_SPEED_11,
506 CONFIG_SYS_I2C_SOFT_SLAVE_11,
509 #if defined(I2C_SOFT_DECLARATIONS12)
510 U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe,
511 soft_i2c_read, soft_i2c_write, NULL,
512 CONFIG_SYS_I2C_SOFT_SPEED_12,
513 CONFIG_SYS_I2C_SOFT_SLAVE_12,