drivers/i2c/sh_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2011, 2013 Renesas Solutions Corp.
   4  * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   5  *
   6  * NOTE: This driver should be converted to driver model before June 2017.
   7  * Please see doc/driver-model/i2c-howto.rst for instructions.
   8  */
   9
  10 #include <common.h>
  11 #include <i2c.h>
  12 #include <log.h>
  13 #include <asm/global_data.h>
  14 #include <asm/io.h>
  15 #include <linux/delay.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 /* Every register is 32bit aligned, but only 8bits in size */
  20 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
  21 struct sh_i2c {
  22         ureg(icdr);
  23         ureg(iccr);
  24         ureg(icsr);
  25         ureg(icic);
  26         ureg(iccl);
  27         ureg(icch);
  28 };
  29 #undef ureg
  30
  31 /* ICCR */
  32 #define SH_I2C_ICCR_ICE         (1 << 7)
  33 #define SH_I2C_ICCR_RACK        (1 << 6)
  34 #define SH_I2C_ICCR_RTS         (1 << 4)
  35 #define SH_I2C_ICCR_BUSY        (1 << 2)
  36 #define SH_I2C_ICCR_SCP         (1 << 0)
  37
  38 /* ICSR / ICIC */
  39 #define SH_IC_BUSY      (1 << 4)
  40 #define SH_IC_TACK      (1 << 2)
  41 #define SH_IC_WAIT      (1 << 1)
  42 #define SH_IC_DTE       (1 << 0)
  43
  44 #ifdef CONFIG_SH_I2C_8BIT
  45 /* store 8th bit of iccl and icch in ICIC register */
  46 #define SH_I2C_ICIC_ICCLB8      (1 << 7)
  47 #define SH_I2C_ICIC_ICCHB8      (1 << 6)
  48 #endif
  49
  50 static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
  51         (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
  52 #ifdef CONFIG_SYS_I2C_SH_BASE1
  53         (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
  54 #endif
  55 #ifdef CONFIG_SYS_I2C_SH_BASE2
  56         (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
  57 #endif
  58 #ifdef CONFIG_SYS_I2C_SH_BASE3
  59         (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
  60 #endif
  61 #ifdef CONFIG_SYS_I2C_SH_BASE4
  62         (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
  63 #endif
  64 };
  65
  66 static u16 iccl, icch;
  67
  68 #define IRQ_WAIT 1000
  69
  70 static void sh_irq_dte(struct sh_i2c *dev)
  71 {
  72         int i;
  73
  74         for (i = 0; i < IRQ_WAIT; i++) {
  75                 if (SH_IC_DTE & readb(&dev->icsr))
  76                         break;
  77                 udelay(10);
  78         }
  79 }
  80
  81 static int sh_irq_dte_with_tack(struct sh_i2c *dev)
  82 {
  83         int i;
  84
  85         for (i = 0; i < IRQ_WAIT; i++) {
  86                 if (SH_IC_DTE & readb(&dev->icsr))
  87                         break;
  88                 if (SH_IC_TACK & readb(&dev->icsr))
  89                         return -1;
  90                 udelay(10);
  91         }
  92         return 0;
  93 }
  94
  95 static void sh_irq_busy(struct sh_i2c *dev)
  96 {
  97         int i;
  98
  99         for (i = 0; i < IRQ_WAIT; i++) {
 100                 if (!(SH_IC_BUSY & readb(&dev->icsr)))
 101                         break;
 102                 udelay(10);
 103         }
 104 }
 105
 106 static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
 107 {
 108         u8 icic = SH_IC_TACK;
 109
 110         debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
 111                                 __func__, chip, addr, iccl, icch);
 112         clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 113         setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 114
 115         writeb(iccl & 0xff, &dev->iccl);
 116         writeb(icch & 0xff, &dev->icch);
 117 #ifdef CONFIG_SH_I2C_8BIT
 118         if (iccl > 0xff)
 119                 icic |= SH_I2C_ICIC_ICCLB8;
 120         if (icch > 0xff)
 121                 icic |= SH_I2C_ICIC_ICCHB8;
 122 #endif
 123         writeb(icic, &dev->icic);
 124
 125         writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
 126         sh_irq_dte(dev);
 127
 128         clrbits_8(&dev->icsr, SH_IC_TACK);
 129         writeb(chip << 1, &dev->icdr);
 130         if (sh_irq_dte_with_tack(dev) != 0)
 131                 return -1;
 132
 133         writeb(addr, &dev->icdr);
 134         if (stop)
 135                 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
 136
 137         if (sh_irq_dte_with_tack(dev) != 0)
 138                 return -1;
 139         return 0;
 140 }
 141
 142 static void sh_i2c_finish(struct sh_i2c *dev)
 143 {
 144         writeb(0, &dev->icsr);
 145         clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 146 }
 147
 148 static int
 149 sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
 150 {
 151         int ret = -1;
 152         if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
 153                 goto exit0;
 154         udelay(10);
 155
 156         writeb(val, &dev->icdr);
 157         if (sh_irq_dte_with_tack(dev) != 0)
 158                 goto exit0;
 159
 160         writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
 161         if (sh_irq_dte_with_tack(dev) != 0)
 162                 goto exit0;
 163         sh_irq_busy(dev);
 164         ret = 0;
 165
 166 exit0:
 167         sh_i2c_finish(dev);
 168         return ret;
 169 }
 170
 171 static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
 172 {
 173         int ret = -1;
 174
 175         if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
 176                 goto exit0;
 177         udelay(100);
 178
 179         writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
 180         sh_irq_dte(dev);
 181
 182         writeb(chip << 1 | 0x01, &dev->icdr);
 183         if (sh_irq_dte_with_tack(dev) != 0)
 184                 goto exit0;
 185
 186         writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
 187         if (sh_irq_dte_with_tack(dev) != 0)
 188                 goto exit0;
 189
 190         ret = readb(&dev->icdr) & 0xff;
 191
 192         writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
 193         readb(&dev->icdr); /* Dummy read */
 194         sh_irq_busy(dev);
 195
 196 exit0:
 197         sh_i2c_finish(dev);
 198
 199         return ret;
 200 }
 201
 202 static void
 203 sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 204 {
 205         int num, denom, tmp;
 206
 207         /* No i2c support prior to relocation */
 208         if (!(gd->flags & GD_FLG_RELOC))
 209                 return;
 210
 211         /*
 212          * Calculate the value for iccl. From the data sheet:
 213          * iccl = (p-clock / transfer-rate) * (L / (L + H))
 214          * where L and H are the SCL low and high ratio.
 215          */
 216         num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
 217         denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
 218         tmp = num * 10 / denom;
 219         if (tmp % 10 >= 5)
 220                 iccl = (u16)((num/denom) + 1);
 221         else
 222                 iccl = (u16)(num/denom);
 223
 224         /* Calculate the value for icch. From the data sheet:
 225            icch = (p clock / transfer rate) * (H / (L + H)) */
 226         num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
 227         tmp = num * 10 / denom;
 228         if (tmp % 10 >= 5)
 229                 icch = (u16)((num/denom) + 1);
 230         else
 231                 icch = (u16)(num/denom);
 232
 233         debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
 234                         CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
 235 }
 236
 237 static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
 238                                 uint addr, int alen, u8 *data, int len)
 239 {
 240         int ret, i;
 241         struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
 242
 243         for (i = 0; i < len; i++) {
 244                 ret = sh_i2c_raw_read(dev, chip, addr + i);
 245                 if (ret < 0)
 246                         return -1;
 247
 248                 data[i] = ret & 0xff;
 249                 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
 250         }
 251
 252         return 0;
 253 }
 254
 255 static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
 256                                 int alen, u8 *data, int len)
 257 {
 258         struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
 259         int i;
 260
 261         for (i = 0; i < len; i++) {
 262                 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
 263                 if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
 264                         return -1;
 265         }
 266         return 0;
 267 }
 268
 269 static int
 270 sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
 271 {
 272         u8 dummy[1];
 273
 274         return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
 275 }
 276
 277 static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
 278                         unsigned int speed)
 279 {
 280         struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
 281
 282         sh_i2c_finish(dev);
 283         sh_i2c_init(adap, speed, 0);
 284
 285         return 0;
 286 }
 287
 288 /*
 289  * Register RCAR i2c adapters
 290  */
 291 U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 292         sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 0)
 293 #ifdef CONFIG_SYS_I2C_SH_BASE1
 294 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 295         sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 1)
 296 #endif
 297 #ifdef CONFIG_SYS_I2C_SH_BASE2
 298 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 299         sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 2)
 300 #endif
 301 #ifdef CONFIG_SYS_I2C_SH_BASE3
 302 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 303         sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 3)
 304 #endif
 305 #ifdef CONFIG_SYS_I2C_SH_BASE4
 306 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 307         sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 4)
 308 #endif