3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * SPDX-License-Identifier: GPL-2.0+
8 /* This code should work for both the S3C2400 and the S3C2410
9 * as they seem to have the same I2C controller inside.
10 * The different address mapping is handled by the s3c24xx.h files below.
15 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
16 #include <asm/arch/clk.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/pinmux.h>
20 #include <asm/arch/s3c24x0_cpu.h>
24 #include "s3c24x0_i2c.h"
26 #ifdef CONFIG_HARD_I2C
34 #define I2C_NOK_LA 3 /* Lost arbitration */
35 #define I2C_NOK_TOUT 4 /* time out */
37 #define I2CSTAT_BSY 0x20 /* Busy bit */
38 #define I2CSTAT_NACK 0x01 /* Nack bit */
39 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
40 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
41 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
42 #define I2C_MODE_MR 0x80 /* Master Receive Mode */
43 #define I2C_START_STOP 0x20 /* START / STOP */
44 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
46 #define I2C_TIMEOUT_MS 1000 /* 1 second */
50 * For SPL boot some boards need i2c before SDRAM is initialised so force
51 * variables to live in SRAM
53 static unsigned int g_current_bus __attribute__((section(".data")));
54 #ifdef CONFIG_OF_CONTROL
55 static int i2c_busses __attribute__((section(".data")));
56 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
57 __attribute__((section(".data")));
60 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
61 static int GetI2CSDA(void)
63 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
66 return (readl(&gpio->gpedat) & 0x8000) >> 15;
69 return (readl(&gpio->pgdat) & 0x0020) >> 5;
73 static void SetI2CSCL(int x)
75 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
78 writel((readl(&gpio->gpedat) & ~0x4000) |
79 (x & 1) << 14, &gpio->gpedat);
82 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
88 * Wait til the byte transfer is completed.
90 * @param i2c- pointer to the appropriate i2c register bank.
91 * @return I2C_OK, if transmission was ACKED
92 * I2C_NACK, if transmission was NACKED
93 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
96 static int WaitForXfer(struct s3c24x0_i2c *i2c)
98 ulong start_time = get_timer(0);
101 if (readl(&i2c->iiccon) & I2CCON_IRPND)
102 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
104 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
109 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
111 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
114 static struct s3c24x0_i2c *get_base_i2c(void)
116 #ifdef CONFIG_EXYNOS4
117 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
118 + (EXYNOS4_I2C_SPACING
121 #elif defined CONFIG_EXYNOS5
122 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
123 + (EXYNOS5_I2C_SPACING
127 return s3c24x0_get_base_i2c();
131 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
133 ulong freq, pres = 16, div;
134 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
135 freq = get_i2c_clk();
139 /* calculate prescaler and divisor values */
140 if ((freq / pres / (16 + 1)) > speed)
141 /* set prescaler to 512 */
145 while ((freq / pres / (div + 1)) > speed)
148 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
149 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
151 /* init to SLAVE REVEIVE and set slaveaddr */
152 writel(0, &i2c->iicstat);
153 writel(slaveadd, &i2c->iicadd);
154 /* program Master Transmit (and implicit STOP) */
155 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
159 * MULTI BUS I2C support
162 #ifdef CONFIG_I2C_MULTI_BUS
163 int i2c_set_bus_num(unsigned int bus)
165 struct s3c24x0_i2c *i2c;
167 if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
168 debug("Bad bus: %d\n", bus);
173 i2c = get_base_i2c();
174 i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
179 unsigned int i2c_get_bus_num(void)
181 return g_current_bus;
185 void i2c_init(int speed, int slaveadd)
188 struct s3c24x0_i2c *i2c;
189 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
190 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
192 ulong start_time = get_timer(0);
194 /* By default i2c channel 0 is the current bus */
196 i2c = get_base_i2c();
199 * In case the previous transfer is still going, wait to give it a
202 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
203 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
204 printf("%s: I2C bus busy for %p\n", __func__,
210 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
211 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
212 #ifdef CONFIG_S3C2410
213 ulong old_gpecon = readl(&gpio->gpecon);
215 #ifdef CONFIG_S3C2400
216 ulong old_gpecon = readl(&gpio->pgcon);
218 /* bus still busy probably by (most) previously interrupted
221 #ifdef CONFIG_S3C2410
222 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
223 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
226 #ifdef CONFIG_S3C2400
227 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
228 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
232 /* toggle I2CSCL until bus idle */
236 while ((i > 0) && (GetI2CSDA() != 1)) {
246 /* restore pin functions */
247 #ifdef CONFIG_S3C2410
248 writel(old_gpecon, &gpio->gpecon);
250 #ifdef CONFIG_S3C2400
251 writel(old_gpecon, &gpio->pgcon);
254 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
255 i2c_ch_init(i2c, speed, slaveadd);
259 * cmd_type is 0 for write, 1 for read.
261 * addr_len can take any value from 0-255, it is only limited
262 * by the char, we could make it larger if needed. If it is
263 * 0 we skip the address write cycle.
265 static int i2c_transfer(struct s3c24x0_i2c *i2c,
266 unsigned char cmd_type,
268 unsigned char addr[],
269 unsigned char addr_len,
270 unsigned char data[],
271 unsigned short data_len)
274 ulong start_time = get_timer(0);
276 if (data == 0 || data_len == 0) {
277 /*Don't support data transfer of no length or to address 0 */
278 debug("i2c_transfer: bad call\n");
282 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
283 if (get_timer(start_time) > I2C_TIMEOUT_MS)
287 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
289 /* Get the slave chip address going */
290 writel(chip, &i2c->iicds);
291 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
292 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
295 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
298 /* Wait for chip address to transmit. */
299 result = WaitForXfer(i2c);
300 if (result != I2C_OK)
303 /* If register address needs to be transmitted - do it now. */
304 if (addr && addr_len) {
305 while ((i < addr_len) && (result == I2C_OK)) {
306 writel(addr[i++], &i2c->iicds);
308 result = WaitForXfer(i2c);
311 if (result != I2C_OK)
317 while ((i < data_len) && (result == I2C_OK)) {
318 writel(data[i++], &i2c->iicds);
320 result = WaitForXfer(i2c);
325 if (addr && addr_len) {
327 * Register address has been sent, now send slave chip
328 * address again to start the actual read transaction.
330 writel(chip, &i2c->iicds);
332 /* Generate a re-START. */
333 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
336 result = WaitForXfer(i2c);
338 if (result != I2C_OK)
342 while ((i < data_len) && (result == I2C_OK)) {
343 /* disable ACK for final READ */
344 if (i == data_len - 1)
345 writel(readl(&i2c->iiccon)
349 result = WaitForXfer(i2c);
350 data[i++] = readl(&i2c->iicds);
352 if (result == I2C_NACK)
353 result = I2C_OK; /* Normal terminated read. */
357 debug("i2c_transfer: bad call\n");
364 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
370 int i2c_probe(uchar chip)
372 struct s3c24x0_i2c *i2c;
375 i2c = get_base_i2c();
379 * What is needed is to send the chip address and verify that the
380 * address was <ACK>ed (i.e. there was a chip at that address which
381 * drove the data line low).
383 return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
386 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
388 struct s3c24x0_i2c *i2c;
393 debug("I2C read: addr len %d not supported\n", alen);
398 xaddr[0] = (addr >> 24) & 0xFF;
399 xaddr[1] = (addr >> 16) & 0xFF;
400 xaddr[2] = (addr >> 8) & 0xFF;
401 xaddr[3] = addr & 0xFF;
404 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
406 * EEPROM chips that implement "address overflow" are ones
407 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
408 * address and the extra bits end up in the "chip address"
409 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
410 * four 256 byte chips.
412 * Note that we consider the length of the address field to
413 * still be one byte because the extra address bits are
414 * hidden in the chip address.
417 chip |= ((addr >> (alen * 8)) &
418 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
420 i2c = get_base_i2c();
421 ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
424 debug("I2c read: failed %d\n", ret);
430 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
432 struct s3c24x0_i2c *i2c;
436 debug("I2C write: addr len %d not supported\n", alen);
441 xaddr[0] = (addr >> 24) & 0xFF;
442 xaddr[1] = (addr >> 16) & 0xFF;
443 xaddr[2] = (addr >> 8) & 0xFF;
444 xaddr[3] = addr & 0xFF;
446 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
448 * EEPROM chips that implement "address overflow" are ones
449 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
450 * address and the extra bits end up in the "chip address"
451 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
452 * four 256 byte chips.
454 * Note that we consider the length of the address field to
455 * still be one byte because the extra address bits are
456 * hidden in the chip address.
459 chip |= ((addr >> (alen * 8)) &
460 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
462 i2c = get_base_i2c();
464 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
468 #ifdef CONFIG_OF_CONTROL
469 void board_i2c_init(const void *blob)
472 int node_list[CONFIG_MAX_I2C_NUM];
475 count = fdtdec_find_aliases_for_id(blob, "i2c",
476 COMPAT_SAMSUNG_S3C2440_I2C, node_list,
479 for (i = 0; i < count; i++) {
480 struct s3c24x0_i2c_bus *bus;
481 int node = node_list[i];
486 bus->regs = (struct s3c24x0_i2c *)
487 fdtdec_get_addr(blob, node, "reg");
488 bus->id = pinmux_decode_periph_id(blob, node);
490 bus->bus_num = i2c_busses++;
491 exynos_pinmux_config(bus->id, 0);
495 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
497 if (bus_idx < i2c_busses)
498 return &i2c_bus[bus_idx];
500 debug("Undefined bus: %d\n", bus_idx);
504 int i2c_get_bus_num_fdt(int node)
508 for (i = 0; i < i2c_busses; i++) {
509 if (node == i2c_bus[i].node)
513 debug("%s: Can't find any matched I2C bus\n", __func__);
517 int i2c_reset_port_fdt(const void *blob, int node)
519 struct s3c24x0_i2c_bus *i2c;
522 bus = i2c_get_bus_num_fdt(node);
524 debug("could not get bus for node %d\n", node);
530 debug("get_bus() failed for node node %d\n", node);
534 i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
540 #endif /* CONFIG_HARD_I2C */