3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* This code should work for both the S3C2400 and the S3C2410
25 * as they seem to have the same I2C controller inside.
26 * The different address mapping is handled by the s3c24xx.h files below.
30 #if defined(CONFIG_S3C2400)
32 #elif defined(CONFIG_S3C2410)
37 #ifdef CONFIG_HARD_I2C
45 #define I2C_NOK_LA 3 /* Lost arbitration */
46 #define I2C_NOK_TOUT 4 /* time out */
48 #define I2CSTAT_BSY 0x20 /* Busy bit */
49 #define I2CSTAT_NACK 0x01 /* Nack bit */
50 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
51 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
52 #define I2C_MODE_MR 0x80 /* Master Receive Mode */
53 #define I2C_START_STOP 0x20 /* START / STOP */
54 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
56 #define I2C_TIMEOUT 1 /* 1 second */
59 static int GetI2CSDA(void)
61 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
64 return (gpio->GPEDAT & 0x8000) >> 15;
67 return (gpio->PGDAT & 0x0020) >> 5;
72 static void SetI2CSDA(int x)
74 rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
78 static void SetI2CSCL(int x)
80 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
83 gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
86 gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6;
91 static int WaitForXfer (void)
93 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
96 i = I2C_TIMEOUT * 10000;
98 while ((i > 0) && !(status & I2CCON_IRPND)) {
100 status = i2c->IICCON;
104 return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
107 static int IsACK (void)
109 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
111 return (!(i2c->IICSTAT & I2CSTAT_NACK));
114 static void ReadWriteByte (void)
116 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
118 i2c->IICCON &= ~I2CCON_IRPND;
121 void i2c_init (int speed, int slaveadd)
123 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
124 S3C24X0_GPIO *const gpio = S3C24X0_GetBase_GPIO ();
125 ulong freq, pres = 16, div;
128 /* wait for some time to give previous transfer a chance to finish */
130 i = I2C_TIMEOUT * 1000;
131 status = i2c->IICSTAT;
132 while ((i > 0) && (status & I2CSTAT_BSY)) {
134 status = i2c->IICSTAT;
138 if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
139 #ifdef CONFIG_S3C2410
140 ulong old_gpecon = gpio->GPECON;
142 #ifdef CONFIG_S3C2400
143 ulong old_gpecon = gpio->PGCON;
145 /* bus still busy probably by (most) previously interrupted transfer */
147 #ifdef CONFIG_S3C2410
148 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
149 gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
151 #ifdef CONFIG_S3C2400
152 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
153 gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00001000;
156 /* toggle I2CSCL until bus idle */
160 while ((i > 0) && (GetI2CSDA () != 1)) {
170 /* restore pin functions */
171 #ifdef CONFIG_S3C2410
172 gpio->GPECON = old_gpecon;
174 #ifdef CONFIG_S3C2400
175 gpio->PGCON = old_gpecon;
179 /* calculate prescaler and divisor values */
181 if ((freq / pres / (16 + 1)) > speed)
182 /* set prescaler to 512 */
186 while ((freq / pres / (div + 1)) > speed)
189 /* set prescaler, divisor according to freq, also set
191 i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
193 /* init to SLAVE REVEIVE and set slaveaddr */
195 i2c->IICADD = slaveadd;
196 /* program Master Transmit (and implicit STOP) */
197 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
202 * cmd_type is 0 for write, 1 for read.
204 * addr_len can take any value from 0-255, it is only limited
205 * by the char, we could make it larger if needed. If it is
206 * 0 we skip the address write cycle.
209 int i2c_transfer (unsigned char cmd_type,
211 unsigned char addr[],
212 unsigned char addr_len,
213 unsigned char data[], unsigned short data_len)
215 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
216 int i, status, result;
218 if (data == 0 || data_len == 0) {
219 /*Don't support data transfer of no length or to address 0 */
220 printf ("i2c_transfer: bad call\n");
224 /* Check I2C bus idle */
225 i = I2C_TIMEOUT * 1000;
226 status = i2c->IICSTAT;
227 while ((i > 0) && (status & I2CSTAT_BSY)) {
229 status = i2c->IICSTAT;
233 if (status & I2CSTAT_BSY)
241 if (addr && addr_len) {
244 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
246 while ((i < addr_len) && (result == I2C_OK)) {
247 result = WaitForXfer ();
248 i2c->IICDS = addr[i];
253 while ((i < data_len) && (result == I2C_OK)) {
254 result = WaitForXfer ();
255 i2c->IICDS = data[i];
262 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
264 while ((i < data_len) && (result = I2C_OK)) {
265 result = WaitForXfer ();
266 i2c->IICDS = data[i];
272 if (result == I2C_OK)
273 result = WaitForXfer ();
276 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
281 if (addr && addr_len) {
282 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
285 i2c->IICSTAT |= I2C_START_STOP;
286 result = WaitForXfer ();
289 while ((i < addr_len) && (result == I2C_OK)) {
290 i2c->IICDS = addr[i];
292 result = WaitForXfer ();
298 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA |
301 result = WaitForXfer ();
303 while ((i < data_len) && (result == I2C_OK)) {
304 /* disable ACK for final READ */
305 if (i == data_len - 1)
306 i2c->IICCON &= ~0x80;
308 result = WaitForXfer ();
309 data[i] = i2c->IICDS;
317 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
320 i2c->IICSTAT |= I2C_START_STOP;
321 result = WaitForXfer ();
325 while ((i < data_len) && (result == I2C_OK)) {
326 /* disable ACK for final READ */
327 if (i == data_len - 1)
328 i2c->IICCON &= ~0x80;
330 result = WaitForXfer ();
331 data[i] = i2c->IICDS;
340 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
345 printf ("i2c_transfer: bad call\n");
353 int i2c_probe (uchar chip)
360 * What is needed is to send the chip address and verify that the
361 * address was <ACK>ed (i.e. there was a chip at that address which
362 * drove the data line low).
364 return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK);
367 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
373 printf ("I2C read: addr len %d not supported\n", alen);
378 xaddr[0] = (addr >> 24) & 0xFF;
379 xaddr[1] = (addr >> 16) & 0xFF;
380 xaddr[2] = (addr >> 8) & 0xFF;
381 xaddr[3] = addr & 0xFF;
384 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
386 * EEPROM chips that implement "address overflow" are ones
387 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
388 * address and the extra bits end up in the "chip address"
389 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
390 * four 256 byte chips.
392 * Note that we consider the length of the address field to
393 * still be one byte because the extra address bits are
394 * hidden in the chip address.
397 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
400 i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen,
401 buffer, len)) != 0) {
402 printf ("I2c read: failed %d\n", ret);
408 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
413 printf ("I2C write: addr len %d not supported\n", alen);
418 xaddr[0] = (addr >> 24) & 0xFF;
419 xaddr[1] = (addr >> 16) & 0xFF;
420 xaddr[2] = (addr >> 8) & 0xFF;
421 xaddr[3] = addr & 0xFF;
423 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
425 * EEPROM chips that implement "address overflow" are ones
426 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
427 * address and the extra bits end up in the "chip address"
428 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
429 * four 256 byte chips.
431 * Note that we consider the length of the address field to
432 * still be one byte because the extra address bits are
433 * hidden in the chip address.
436 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
439 (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
442 #endif /* CONFIG_HARD_I2C */