Prepare v2024.10
[platform/kernel/u-boot.git] / drivers / i2c / s3c24x0_i2c.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2002
4  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5  */
6
7 #include <errno.h>
8 #include <dm.h>
9 #include <fdtdec.h>
10 #include <time.h>
11 #include <log.h>
12 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
13 #include <asm/arch/clk.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/pinmux.h>
16 #endif
17 #include <asm/global_data.h>
18 #include <asm/io.h>
19 #include <i2c.h>
20 #include <clk.h>
21 #include "s3c24x0_i2c.h"
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /*
26  * Wait til the byte transfer is completed.
27  *
28  * @param i2c- pointer to the appropriate i2c register bank.
29  * Return: I2C_OK, if transmission was ACKED
30  *         I2C_NACK, if transmission was NACKED
31  *         I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
32  */
33
34 static int WaitForXfer(struct s3c24x0_i2c *i2c)
35 {
36         ulong start_time = get_timer(0);
37
38         do {
39                 if (readl(&i2c->iiccon) & I2CCON_IRPND)
40                         return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
41                                 I2C_NACK : I2C_OK;
42         } while (get_timer(start_time) < I2C_TIMEOUT_MS);
43
44         return I2C_NOK_TOUT;
45 }
46
47 static void read_write_byte(struct s3c24x0_i2c *i2c)
48 {
49         clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
50 }
51
52 static int i2c_ch_init(struct udevice *dev, int speed, int slaveadd)
53 {
54         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
55         struct s3c24x0_i2c *i2c = i2c_bus->regs;
56         ulong freq, pres = 16, div;
57
58 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
59         freq = get_i2c_clk();
60 #else
61         struct clk clk;
62         int ret;
63
64         ret = clk_get_by_name(dev, "i2c", &clk);
65         if (ret < 0)
66                 return ret;
67         freq = clk_get_rate(&clk);
68 #endif
69         /* calculate prescaler and divisor values */
70         if ((freq / pres / (16 + 1)) > speed)
71                 /* set prescaler to 512 */
72                 pres = 512;
73
74         div = 0;
75         while ((freq / pres / (div + 1)) > speed)
76                 div++;
77
78         /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
79         writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
80
81         /* init to SLAVE REVEIVE and set slaveaddr */
82         writel(0, &i2c->iicstat);
83         writel(slaveadd, &i2c->iicadd);
84         /* program Master Transmit (and implicit STOP) */
85         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
86         return 0;
87 }
88
89 #define SYS_I2C_S3C24X0_SLAVE_ADDR      0
90
91 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
92 {
93         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
94
95         i2c_bus->clock_frequency = speed;
96
97         if (i2c_ch_init(dev, i2c_bus->clock_frequency,
98                         SYS_I2C_S3C24X0_SLAVE_ADDR))
99                 return -EFAULT;
100
101         return 0;
102 }
103
104 /*
105  * cmd_type is 0 for write, 1 for read.
106  *
107  * addr_len can take any value from 0-255, it is only limited
108  * by the char, we could make it larger if needed. If it is
109  * 0 we skip the address write cycle.
110  */
111 static int i2c_transfer(struct s3c24x0_i2c *i2c,
112                         unsigned char cmd_type,
113                         unsigned char chip,
114                         unsigned char addr[],
115                         unsigned char addr_len,
116                         unsigned char data[],
117                         unsigned short data_len)
118 {
119         int i = 0, result;
120         ulong start_time = get_timer(0);
121
122         if (data == 0 || data_len == 0) {
123                 /*Don't support data transfer of no length or to address 0 */
124                 debug("i2c_transfer: bad call\n");
125                 return I2C_NOK;
126         }
127
128         while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
129                 if (get_timer(start_time) > I2C_TIMEOUT_MS)
130                         return I2C_NOK_TOUT;
131         }
132
133         writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
134
135         /* Get the slave chip address going */
136         writel(chip, &i2c->iicds);
137         if ((cmd_type == I2C_WRITE) || (addr && addr_len))
138                 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
139                        &i2c->iicstat);
140         else
141                 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
142                        &i2c->iicstat);
143
144         /* Wait for chip address to transmit. */
145         result = WaitForXfer(i2c);
146         if (result != I2C_OK)
147                 goto bailout;
148
149         /* If register address needs to be transmitted - do it now. */
150         if (addr && addr_len) {
151                 while ((i < addr_len) && (result == I2C_OK)) {
152                         writel(addr[i++], &i2c->iicds);
153                         read_write_byte(i2c);
154                         result = WaitForXfer(i2c);
155                 }
156                 i = 0;
157                 if (result != I2C_OK)
158                         goto bailout;
159         }
160
161         switch (cmd_type) {
162         case I2C_WRITE:
163                 while ((i < data_len) && (result == I2C_OK)) {
164                         writel(data[i++], &i2c->iicds);
165                         read_write_byte(i2c);
166                         result = WaitForXfer(i2c);
167                 }
168                 break;
169
170         case I2C_READ:
171                 if (addr && addr_len) {
172                         /*
173                          * Register address has been sent, now send slave chip
174                          * address again to start the actual read transaction.
175                          */
176                         writel(chip, &i2c->iicds);
177
178                         /* Generate a re-START. */
179                         writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
180                                 &i2c->iicstat);
181                         read_write_byte(i2c);
182                         result = WaitForXfer(i2c);
183
184                         if (result != I2C_OK)
185                                 goto bailout;
186                 }
187
188                 while ((i < data_len) && (result == I2C_OK)) {
189                         /* disable ACK for final READ */
190                         if (i == data_len - 1)
191                                 writel(readl(&i2c->iiccon)
192                                        & ~I2CCON_ACKGEN,
193                                        &i2c->iiccon);
194                         read_write_byte(i2c);
195                         result = WaitForXfer(i2c);
196                         data[i++] = readl(&i2c->iicds);
197                 }
198                 if (result == I2C_NACK)
199                         result = I2C_OK; /* Normal terminated read. */
200                 break;
201
202         default:
203                 debug("i2c_transfer: bad call\n");
204                 result = I2C_NOK;
205                 break;
206         }
207
208 bailout:
209         /* Send STOP. */
210         writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
211         read_write_byte(i2c);
212
213         return result;
214 }
215
216 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
217 {
218         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
219         uchar buf[1];
220         int ret;
221
222         buf[0] = 0;
223
224         /*
225          * What is needed is to send the chip address and verify that the
226          * address was <ACK>ed (i.e. there was a chip at that address which
227          * drove the data line low).
228          */
229         ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
230
231         return ret != I2C_OK;
232 }
233
234 static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
235                           int seq)
236 {
237         struct s3c24x0_i2c *i2c = i2c_bus->regs;
238         bool is_read = msg->flags & I2C_M_RD;
239         uint status;
240         uint addr;
241         int ret, i;
242
243         if (!seq)
244                 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
245
246         /* Get the slave chip address going */
247         addr = msg->addr << 1;
248         writel(addr, &i2c->iicds);
249         status = I2C_TXRX_ENA | I2C_START_STOP;
250         if (is_read)
251                 status |= I2C_MODE_MR;
252         else
253                 status |= I2C_MODE_MT;
254         writel(status, &i2c->iicstat);
255         if (seq)
256                 read_write_byte(i2c);
257
258         /* Wait for chip address to transmit */
259         ret = WaitForXfer(i2c);
260         if (ret)
261                 goto err;
262
263         if (is_read) {
264                 for (i = 0; !ret && i < msg->len; i++) {
265                         /* disable ACK for final READ */
266                         if (i == msg->len - 1)
267                                 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
268                         read_write_byte(i2c);
269                         ret = WaitForXfer(i2c);
270                         msg->buf[i] = readl(&i2c->iicds);
271                 }
272                 if (ret == I2C_NACK)
273                         ret = I2C_OK; /* Normal terminated read */
274         } else {
275                 for (i = 0; !ret && i < msg->len; i++) {
276                         writel(msg->buf[i], &i2c->iicds);
277                         read_write_byte(i2c);
278                         ret = WaitForXfer(i2c);
279                 }
280         }
281
282 err:
283         return ret;
284 }
285
286 static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
287                             int nmsgs)
288 {
289         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
290         struct s3c24x0_i2c *i2c = i2c_bus->regs;
291         ulong start_time;
292         int ret, i;
293
294         start_time = get_timer(0);
295         while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
296                 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
297                         debug("Timeout\n");
298                         return -ETIMEDOUT;
299                 }
300         }
301
302         for (ret = 0, i = 0; !ret && i < nmsgs; i++)
303                 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
304
305         /* Send STOP */
306         writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
307         read_write_byte(i2c);
308
309         return ret ? -EREMOTEIO : 0;
310 }
311
312 static int s3c_i2c_of_to_plat(struct udevice *dev)
313 {
314 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
315         const void *blob = gd->fdt_blob;
316 #endif
317         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
318         int node;
319
320         node = dev_of_offset(dev);
321
322         i2c_bus->regs = dev_read_addr_ptr(dev);
323
324 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
325         i2c_bus->id = pinmux_decode_periph_id(blob, node);
326 #endif
327
328         i2c_bus->clock_frequency =
329                 dev_read_u32_default(dev, "clock-frequency",
330                                      I2C_SPEED_STANDARD_RATE);
331         i2c_bus->node = node;
332         i2c_bus->bus_num = dev_seq(dev);
333
334 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
335         exynos_pinmux_config(i2c_bus->id, 0);
336 #endif
337
338         i2c_bus->active = true;
339
340         return 0;
341 }
342
343 static const struct dm_i2c_ops s3c_i2c_ops = {
344         .xfer           = s3c24x0_i2c_xfer,
345         .probe_chip     = s3c24x0_i2c_probe,
346         .set_bus_speed  = s3c24x0_i2c_set_bus_speed,
347 };
348
349 static const struct udevice_id s3c_i2c_ids[] = {
350         { .compatible = "samsung,s3c2440-i2c" },
351         { }
352 };
353
354 U_BOOT_DRIVER(i2c_s3c) = {
355         .name   = "i2c_s3c",
356         .id     = UCLASS_I2C,
357         .of_match = s3c_i2c_ids,
358         .of_to_plat = s3c_i2c_of_to_plat,
359         .priv_auto      = sizeof(struct s3c24x0_i2c_bus),
360         .ops    = &s3c_i2c_ops,
361 };