1 // SPDX-License-Identifier: GPL-2.0+
4 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
12 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
13 #include <asm/arch/clk.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/pinmux.h>
17 #include <asm/global_data.h>
21 #include "s3c24x0_i2c.h"
23 DECLARE_GLOBAL_DATA_PTR;
26 * Wait til the byte transfer is completed.
28 * @param i2c- pointer to the appropriate i2c register bank.
29 * Return: I2C_OK, if transmission was ACKED
30 * I2C_NACK, if transmission was NACKED
31 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
34 static int WaitForXfer(struct s3c24x0_i2c *i2c)
36 ulong start_time = get_timer(0);
39 if (readl(&i2c->iiccon) & I2CCON_IRPND)
40 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
42 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
47 static void read_write_byte(struct s3c24x0_i2c *i2c)
49 clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
52 static int i2c_ch_init(struct udevice *dev, int speed, int slaveadd)
54 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
55 struct s3c24x0_i2c *i2c = i2c_bus->regs;
56 ulong freq, pres = 16, div;
58 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
64 ret = clk_get_by_name(dev, "i2c", &clk);
67 freq = clk_get_rate(&clk);
69 /* calculate prescaler and divisor values */
70 if ((freq / pres / (16 + 1)) > speed)
71 /* set prescaler to 512 */
75 while ((freq / pres / (div + 1)) > speed)
78 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
79 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
81 /* init to SLAVE REVEIVE and set slaveaddr */
82 writel(0, &i2c->iicstat);
83 writel(slaveadd, &i2c->iicadd);
84 /* program Master Transmit (and implicit STOP) */
85 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
89 #define SYS_I2C_S3C24X0_SLAVE_ADDR 0
91 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
93 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
95 i2c_bus->clock_frequency = speed;
97 if (i2c_ch_init(dev, i2c_bus->clock_frequency,
98 SYS_I2C_S3C24X0_SLAVE_ADDR))
105 * cmd_type is 0 for write, 1 for read.
107 * addr_len can take any value from 0-255, it is only limited
108 * by the char, we could make it larger if needed. If it is
109 * 0 we skip the address write cycle.
111 static int i2c_transfer(struct s3c24x0_i2c *i2c,
112 unsigned char cmd_type,
114 unsigned char addr[],
115 unsigned char addr_len,
116 unsigned char data[],
117 unsigned short data_len)
120 ulong start_time = get_timer(0);
122 if (data == 0 || data_len == 0) {
123 /*Don't support data transfer of no length or to address 0 */
124 debug("i2c_transfer: bad call\n");
128 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
129 if (get_timer(start_time) > I2C_TIMEOUT_MS)
133 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
135 /* Get the slave chip address going */
136 writel(chip, &i2c->iicds);
137 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
138 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
141 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
144 /* Wait for chip address to transmit. */
145 result = WaitForXfer(i2c);
146 if (result != I2C_OK)
149 /* If register address needs to be transmitted - do it now. */
150 if (addr && addr_len) {
151 while ((i < addr_len) && (result == I2C_OK)) {
152 writel(addr[i++], &i2c->iicds);
153 read_write_byte(i2c);
154 result = WaitForXfer(i2c);
157 if (result != I2C_OK)
163 while ((i < data_len) && (result == I2C_OK)) {
164 writel(data[i++], &i2c->iicds);
165 read_write_byte(i2c);
166 result = WaitForXfer(i2c);
171 if (addr && addr_len) {
173 * Register address has been sent, now send slave chip
174 * address again to start the actual read transaction.
176 writel(chip, &i2c->iicds);
178 /* Generate a re-START. */
179 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
181 read_write_byte(i2c);
182 result = WaitForXfer(i2c);
184 if (result != I2C_OK)
188 while ((i < data_len) && (result == I2C_OK)) {
189 /* disable ACK for final READ */
190 if (i == data_len - 1)
191 writel(readl(&i2c->iiccon)
194 read_write_byte(i2c);
195 result = WaitForXfer(i2c);
196 data[i++] = readl(&i2c->iicds);
198 if (result == I2C_NACK)
199 result = I2C_OK; /* Normal terminated read. */
203 debug("i2c_transfer: bad call\n");
210 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
211 read_write_byte(i2c);
216 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
218 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
225 * What is needed is to send the chip address and verify that the
226 * address was <ACK>ed (i.e. there was a chip at that address which
227 * drove the data line low).
229 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
231 return ret != I2C_OK;
234 static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
237 struct s3c24x0_i2c *i2c = i2c_bus->regs;
238 bool is_read = msg->flags & I2C_M_RD;
244 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
246 /* Get the slave chip address going */
247 addr = msg->addr << 1;
248 writel(addr, &i2c->iicds);
249 status = I2C_TXRX_ENA | I2C_START_STOP;
251 status |= I2C_MODE_MR;
253 status |= I2C_MODE_MT;
254 writel(status, &i2c->iicstat);
256 read_write_byte(i2c);
258 /* Wait for chip address to transmit */
259 ret = WaitForXfer(i2c);
264 for (i = 0; !ret && i < msg->len; i++) {
265 /* disable ACK for final READ */
266 if (i == msg->len - 1)
267 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
268 read_write_byte(i2c);
269 ret = WaitForXfer(i2c);
270 msg->buf[i] = readl(&i2c->iicds);
273 ret = I2C_OK; /* Normal terminated read */
275 for (i = 0; !ret && i < msg->len; i++) {
276 writel(msg->buf[i], &i2c->iicds);
277 read_write_byte(i2c);
278 ret = WaitForXfer(i2c);
286 static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
289 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
290 struct s3c24x0_i2c *i2c = i2c_bus->regs;
294 start_time = get_timer(0);
295 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
296 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
302 for (ret = 0, i = 0; !ret && i < nmsgs; i++)
303 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
306 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
307 read_write_byte(i2c);
309 return ret ? -EREMOTEIO : 0;
312 static int s3c_i2c_of_to_plat(struct udevice *dev)
314 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
315 const void *blob = gd->fdt_blob;
317 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
320 node = dev_of_offset(dev);
322 i2c_bus->regs = dev_read_addr_ptr(dev);
324 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
325 i2c_bus->id = pinmux_decode_periph_id(blob, node);
328 i2c_bus->clock_frequency =
329 dev_read_u32_default(dev, "clock-frequency",
330 I2C_SPEED_STANDARD_RATE);
331 i2c_bus->node = node;
332 i2c_bus->bus_num = dev_seq(dev);
334 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
335 exynos_pinmux_config(i2c_bus->id, 0);
338 i2c_bus->active = true;
343 static const struct dm_i2c_ops s3c_i2c_ops = {
344 .xfer = s3c24x0_i2c_xfer,
345 .probe_chip = s3c24x0_i2c_probe,
346 .set_bus_speed = s3c24x0_i2c_set_bus_speed,
349 static const struct udevice_id s3c_i2c_ids[] = {
350 { .compatible = "samsung,s3c2440-i2c" },
354 U_BOOT_DRIVER(i2c_s3c) = {
357 .of_match = s3c_i2c_ids,
358 .of_to_plat = s3c_i2c_of_to_plat,
359 .priv_auto = sizeof(struct s3c24x0_i2c_bus),