3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * SPDX-License-Identifier: GPL-2.0+
8 /* This code should work for both the S3C2400 and the S3C2410
9 * as they seem to have the same I2C controller inside.
10 * The different address mapping is handled by the s3c24xx.h files below.
16 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
17 #include <asm/arch/clk.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/pinmux.h>
21 #include <asm/arch/s3c24x0_cpu.h>
25 #include "s3c24x0_i2c.h"
33 #define I2C_NOK_LA 3 /* Lost arbitration */
34 #define I2C_NOK_TOUT 4 /* time out */
36 /* HSI2C specific register description */
38 /* I2C_CTL Register bits */
39 #define HSI2C_FUNC_MODE_I2C (1u << 0)
40 #define HSI2C_MASTER (1u << 3)
41 #define HSI2C_RXCHON (1u << 6) /* Write/Send */
42 #define HSI2C_TXCHON (1u << 7) /* Read/Receive */
43 #define HSI2C_SW_RST (1u << 31)
45 /* I2C_FIFO_CTL Register bits */
46 #define HSI2C_RXFIFO_EN (1u << 0)
47 #define HSI2C_TXFIFO_EN (1u << 1)
48 #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
49 #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
51 /* I2C_TRAILING_CTL Register bits */
52 #define HSI2C_TRAILING_COUNT (0xff)
54 /* I2C_INT_EN Register bits */
55 #define HSI2C_TX_UNDERRUN_EN (1u << 2)
56 #define HSI2C_TX_OVERRUN_EN (1u << 3)
57 #define HSI2C_RX_UNDERRUN_EN (1u << 4)
58 #define HSI2C_RX_OVERRUN_EN (1u << 5)
59 #define HSI2C_INT_TRAILING_EN (1u << 6)
60 #define HSI2C_INT_I2C_EN (1u << 9)
62 #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\
63 HSI2C_TX_OVERRUN_EN |\
64 HSI2C_RX_UNDERRUN_EN |\
65 HSI2C_RX_OVERRUN_EN |\
66 HSI2C_INT_TRAILING_EN)
68 /* I2C_CONF Register bits */
69 #define HSI2C_AUTO_MODE (1u << 31)
70 #define HSI2C_10BIT_ADDR_MODE (1u << 30)
71 #define HSI2C_HS_MODE (1u << 29)
73 /* I2C_AUTO_CONF Register bits */
74 #define HSI2C_READ_WRITE (1u << 16)
75 #define HSI2C_STOP_AFTER_TRANS (1u << 17)
76 #define HSI2C_MASTER_RUN (1u << 31)
78 /* I2C_TIMEOUT Register bits */
79 #define HSI2C_TIMEOUT_EN (1u << 31)
81 /* I2C_TRANS_STATUS register bits */
82 #define HSI2C_MASTER_BUSY (1u << 17)
83 #define HSI2C_SLAVE_BUSY (1u << 16)
84 #define HSI2C_TIMEOUT_AUTO (1u << 4)
85 #define HSI2C_NO_DEV (1u << 3)
86 #define HSI2C_NO_DEV_ACK (1u << 2)
87 #define HSI2C_TRANS_ABORT (1u << 1)
88 #define HSI2C_TRANS_SUCCESS (1u << 0)
89 #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\
90 HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
92 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
95 /* I2C_FIFO_STAT Register bits */
96 #define HSI2C_RX_FIFO_EMPTY (1u << 24)
97 #define HSI2C_RX_FIFO_FULL (1u << 23)
98 #define HSI2C_TX_FIFO_EMPTY (1u << 8)
99 #define HSI2C_TX_FIFO_FULL (1u << 7)
100 #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f)
101 #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f)
103 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
105 /* S3C I2C Controller bits */
106 #define I2CSTAT_BSY 0x20 /* Busy bit */
107 #define I2CSTAT_NACK 0x01 /* Nack bit */
108 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
109 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
110 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
111 #define I2C_MODE_MR 0x80 /* Master Receive Mode */
112 #define I2C_START_STOP 0x20 /* START / STOP */
113 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
115 #define I2C_TIMEOUT_MS 10 /* 10 ms */
117 #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
119 DECLARE_GLOBAL_DATA_PTR;
121 enum exynos_i2c_type {
127 * Wait til the byte transfer is completed.
129 * @param i2c- pointer to the appropriate i2c register bank.
130 * @return I2C_OK, if transmission was ACKED
131 * I2C_NACK, if transmission was NACKED
132 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
135 static int WaitForXfer(struct s3c24x0_i2c *i2c)
137 ulong start_time = get_timer(0);
140 if (readl(&i2c->iiccon) & I2CCON_IRPND)
141 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
143 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
149 * Wait for transfer completion.
151 * This function reads the interrupt status register waiting for the INT_I2C
152 * bit to be set, which indicates copletion of a transaction.
154 * @param i2c: pointer to the appropriate register bank
156 * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
157 * the status bits do not get set in time, or an approrpiate error
158 * value in case of transfer errors.
160 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
162 int i = HSI2C_TIMEOUT_US;
165 u32 int_status = readl(&i2c->usi_int_stat);
167 if (int_status & HSI2C_INT_I2C_EN) {
168 u32 trans_status = readl(&i2c->usi_trans_status);
170 /* Deassert pending interrupt. */
171 writel(int_status, &i2c->usi_int_stat);
173 if (trans_status & HSI2C_NO_DEV_ACK) {
174 debug("%s: no ACK from device\n", __func__);
177 if (trans_status & HSI2C_NO_DEV) {
178 debug("%s: no device\n", __func__);
181 if (trans_status & HSI2C_TRANS_ABORT) {
182 debug("%s: arbitration lost\n", __func__);
185 if (trans_status & HSI2C_TIMEOUT_AUTO) {
186 debug("%s: device timed out\n", __func__);
193 debug("%s: transaction timeout!\n", __func__);
197 static void read_write_byte(struct s3c24x0_i2c *i2c)
199 clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
202 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
204 ulong freq, pres = 16, div;
205 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
206 freq = get_i2c_clk();
210 /* calculate prescaler and divisor values */
211 if ((freq / pres / (16 + 1)) > speed)
212 /* set prescaler to 512 */
216 while ((freq / pres / (div + 1)) > speed)
219 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
220 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
222 /* init to SLAVE REVEIVE and set slaveaddr */
223 writel(0, &i2c->iicstat);
224 writel(slaveadd, &i2c->iicadd);
225 /* program Master Transmit (and implicit STOP) */
226 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
229 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
231 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
233 unsigned int op_clk = i2c_bus->clock_frequency;
234 unsigned int i = 0, utemp0 = 0, utemp1 = 0;
235 unsigned int t_ftl_cycle;
237 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
238 clkin = get_i2c_clk();
243 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
244 * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
245 * uTemp1 = (TSCLK_L + TSCLK_H + 2)
246 * uTemp2 = TSCLK_L + TSCLK_H
248 t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
249 utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
251 /* CLK_DIV max is 256 */
252 for (i = 0; i < 256; i++) {
253 utemp1 = utemp0 / (i + 1);
254 if ((utemp1 < 512) && (utemp1 > 4)) {
255 i2c_bus->clk_cycle = utemp1 - 2;
256 i2c_bus->clk_div = i;
263 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
265 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
266 unsigned int t_sr_release;
267 unsigned int n_clkdiv;
268 unsigned int t_start_su, t_start_hd;
269 unsigned int t_stop_su;
270 unsigned int t_data_su, t_data_hd;
271 unsigned int t_scl_l, t_scl_h;
277 n_clkdiv = i2c_bus->clk_div;
278 t_scl_l = i2c_bus->clk_cycle / 2;
279 t_scl_h = i2c_bus->clk_cycle / 2;
280 t_start_su = t_scl_l;
281 t_start_hd = t_scl_l;
283 t_data_su = t_scl_l / 2;
284 t_data_hd = t_scl_l / 2;
285 t_sr_release = i2c_bus->clk_cycle;
287 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
288 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
289 i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
290 i2c_timing_sla = t_data_hd << 0;
292 writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
294 /* Clear to enable Timeout */
295 clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
298 writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
300 /* Enable completion conditions' reporting. */
301 writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
304 writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
306 /* Currently operating in Fast speed mode. */
307 writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
308 writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
309 writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
310 writel(i2c_timing_sla, &hsregs->usi_timing_sla);
313 /* SW reset for the high speed bus */
314 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
316 struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
319 /* Set and clear the bit for reset */
320 i2c_ctl = readl(&i2c->usi_ctl);
321 i2c_ctl |= HSI2C_SW_RST;
322 writel(i2c_ctl, &i2c->usi_ctl);
324 i2c_ctl = readl(&i2c->usi_ctl);
325 i2c_ctl &= ~HSI2C_SW_RST;
326 writel(i2c_ctl, &i2c->usi_ctl);
328 /* Initialize the configure registers */
329 hsi2c_ch_init(i2c_bus);
333 * Poll the appropriate bit of the fifo status register until the interface is
334 * ready to process the next byte or timeout expires.
336 * In addition to the FIFO status register this function also polls the
337 * interrupt status register to be able to detect unexpected transaction
340 * When FIFO is ready to process the next byte, this function returns I2C_OK.
341 * If in course of polling the INT_I2C assertion is detected, the function
342 * returns I2C_NOK. If timeout happens before any of the above conditions is
343 * met - the function returns I2C_NOK_TOUT;
345 * @param i2c: pointer to the appropriate i2c register bank.
346 * @param rx_transfer: set to True if the receive transaction is in progress.
347 * @return: as described above.
349 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
351 u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
352 int i = HSI2C_TIMEOUT_US;
354 while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
355 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
357 * There is a chance that assertion of
358 * HSI2C_INT_I2C_EN and deassertion of
359 * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
360 * give FIFO status priority and check it one more
361 * time before reporting interrupt. The interrupt will
362 * be reported next time this function is called.
365 !(readl(&i2c->usi_fifo_stat) & fifo_bit))
370 debug("%s: FIFO polling timeout!\n", __func__);
379 * Preapre hsi2c transaction, either read or write.
381 * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
384 * @param i2c: pointer to the appropriate i2c register bank.
385 * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
386 * @param len: number of bytes expected to be sent or received
387 * @param rx_transfer: set to true for receive transactions
388 * @param: issue_stop: set to true if i2c stop condition should be generated
389 * after this transaction.
390 * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
393 static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
401 conf = len | HSI2C_MASTER_RUN;
404 conf |= HSI2C_STOP_AFTER_TRANS;
406 /* Clear to enable Timeout */
407 writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
409 /* Set slave address */
410 writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
413 /* i2c master, read transaction */
414 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
417 /* read up to len bytes, stop after transaction is finished */
418 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
420 /* i2c master, write transaction */
421 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
424 /* write up to len bytes, stop after transaction is finished */
425 writel(conf, &i2c->usi_auto_conf);
428 /* Reset all pending interrupt status bits we care about, if any */
429 writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
435 * Wait while i2c bus is settling down (mostly stop gets completed).
437 static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
439 int i = HSI2C_TIMEOUT_US;
441 while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
443 debug("%s: bus busy\n", __func__);
451 static int hsi2c_write(struct exynos5_hsi2c *i2c,
453 unsigned char addr[],
455 unsigned char data[],
462 /* Writes of zero length not supported in auto mode. */
463 debug("%s: zero length writes not supported\n", __func__);
467 rv = hsi2c_prepare_transaction
468 (i2c, chip, len + alen, false, issue_stop);
472 /* Move address, if any, and the data, if any, into the FIFO. */
473 for (i = 0; i < alen; i++) {
474 rv = hsi2c_poll_fifo(i2c, false);
476 debug("%s: address write failed\n", __func__);
479 writel(addr[i], &i2c->usi_txdata);
482 for (i = 0; i < len; i++) {
483 rv = hsi2c_poll_fifo(i2c, false);
485 debug("%s: data write failed\n", __func__);
488 writel(data[i], &i2c->usi_txdata);
491 rv = hsi2c_wait_for_trx(i2c);
495 int tmp_ret = hsi2c_wait_while_busy(i2c);
500 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
504 static int hsi2c_read(struct exynos5_hsi2c *i2c,
506 unsigned char addr[],
508 unsigned char data[],
512 bool drop_data = false;
515 /* Reads of zero length not supported in auto mode. */
516 debug("%s: zero length read adjusted\n", __func__);
522 /* Internal register adress needs to be written first. */
523 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
528 rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
533 for (i = 0; i < len; i++) {
534 rv = hsi2c_poll_fifo(i2c, true);
539 data[i] = readl(&i2c->usi_rxdata);
542 rv = hsi2c_wait_for_trx(i2c);
545 tmp_ret = hsi2c_wait_while_busy(i2c);
549 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
553 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
555 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
557 i2c_bus->clock_frequency = speed;
559 if (i2c_bus->is_highspeed) {
560 if (hsi2c_get_clk_details(i2c_bus))
562 hsi2c_ch_init(i2c_bus);
564 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
565 CONFIG_SYS_I2C_S3C24X0_SLAVE);
572 * cmd_type is 0 for write, 1 for read.
574 * addr_len can take any value from 0-255, it is only limited
575 * by the char, we could make it larger if needed. If it is
576 * 0 we skip the address write cycle.
578 static int i2c_transfer(struct s3c24x0_i2c *i2c,
579 unsigned char cmd_type,
581 unsigned char addr[],
582 unsigned char addr_len,
583 unsigned char data[],
584 unsigned short data_len)
587 ulong start_time = get_timer(0);
589 if (data == 0 || data_len == 0) {
590 /*Don't support data transfer of no length or to address 0 */
591 debug("i2c_transfer: bad call\n");
595 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
596 if (get_timer(start_time) > I2C_TIMEOUT_MS)
600 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
602 /* Get the slave chip address going */
603 writel(chip, &i2c->iicds);
604 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
605 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
608 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
611 /* Wait for chip address to transmit. */
612 result = WaitForXfer(i2c);
613 if (result != I2C_OK)
616 /* If register address needs to be transmitted - do it now. */
617 if (addr && addr_len) {
618 while ((i < addr_len) && (result == I2C_OK)) {
619 writel(addr[i++], &i2c->iicds);
620 read_write_byte(i2c);
621 result = WaitForXfer(i2c);
624 if (result != I2C_OK)
630 while ((i < data_len) && (result == I2C_OK)) {
631 writel(data[i++], &i2c->iicds);
632 read_write_byte(i2c);
633 result = WaitForXfer(i2c);
638 if (addr && addr_len) {
640 * Register address has been sent, now send slave chip
641 * address again to start the actual read transaction.
643 writel(chip, &i2c->iicds);
645 /* Generate a re-START. */
646 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
648 read_write_byte(i2c);
649 result = WaitForXfer(i2c);
651 if (result != I2C_OK)
655 while ((i < data_len) && (result == I2C_OK)) {
656 /* disable ACK for final READ */
657 if (i == data_len - 1)
658 writel(readl(&i2c->iiccon)
661 read_write_byte(i2c);
662 result = WaitForXfer(i2c);
663 data[i++] = readl(&i2c->iicds);
665 if (result == I2C_NACK)
666 result = I2C_OK; /* Normal terminated read. */
670 debug("i2c_transfer: bad call\n");
677 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
678 read_write_byte(i2c);
683 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
685 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
692 * What is needed is to send the chip address and verify that the
693 * address was <ACK>ed (i.e. there was a chip at that address which
694 * drove the data line low).
696 if (i2c_bus->is_highspeed) {
697 ret = hsi2c_read(i2c_bus->hsregs,
700 ret = i2c_transfer(i2c_bus->regs,
701 I2C_READ, chip << 1, 0, 0, buf, 1);
704 return ret != I2C_OK;
707 static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
710 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
711 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
714 for (; nmsgs > 0; nmsgs--, msg++) {
715 if (msg->flags & I2C_M_RD) {
716 ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
719 ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
723 exynos5_i2c_reset(i2c_bus);
731 static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
734 struct s3c24x0_i2c *i2c = i2c_bus->regs;
735 bool is_read = msg->flags & I2C_M_RD;
741 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
743 /* Get the slave chip address going */
744 addr = msg->addr << 1;
745 writel(addr, &i2c->iicds);
746 status = I2C_TXRX_ENA | I2C_START_STOP;
748 status |= I2C_MODE_MR;
750 status |= I2C_MODE_MT;
751 writel(status, &i2c->iicstat);
753 read_write_byte(i2c);
755 /* Wait for chip address to transmit */
756 ret = WaitForXfer(i2c);
761 for (i = 0; !ret && i < msg->len; i++) {
762 /* disable ACK for final READ */
763 if (i == msg->len - 1)
764 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
765 read_write_byte(i2c);
766 ret = WaitForXfer(i2c);
767 msg->buf[i] = readl(&i2c->iicds);
770 ret = I2C_OK; /* Normal terminated read */
772 for (i = 0; !ret && i < msg->len; i++) {
773 writel(msg->buf[i], &i2c->iicds);
774 read_write_byte(i2c);
775 ret = WaitForXfer(i2c);
783 static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
786 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
787 struct s3c24x0_i2c *i2c = i2c_bus->regs;
791 start_time = get_timer(0);
792 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
793 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
799 for (ret = 0, i = 0; !ret && i < nmsgs; i++)
800 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
803 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
804 read_write_byte(i2c);
806 return ret ? -EREMOTEIO : 0;
809 static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
811 const void *blob = gd->fdt_blob;
812 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
815 i2c_bus->is_highspeed = dev_get_driver_data(dev);
816 node = dev->of_offset;
818 if (i2c_bus->is_highspeed) {
819 flags = PINMUX_FLAG_HS_MODE;
820 i2c_bus->hsregs = (struct exynos5_hsi2c *)dev_get_addr(dev);
823 i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
826 i2c_bus->id = pinmux_decode_periph_id(blob, node);
828 i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
829 "clock-frequency", 100000);
830 i2c_bus->node = node;
831 i2c_bus->bus_num = dev->seq;
833 exynos_pinmux_config(i2c_bus->id, flags);
835 i2c_bus->active = true;
840 static const struct dm_i2c_ops s3c_i2c_ops = {
841 .xfer = s3c24x0_i2c_xfer,
842 .probe_chip = s3c24x0_i2c_probe,
843 .set_bus_speed = s3c24x0_i2c_set_bus_speed,
846 static const struct udevice_id s3c_i2c_ids[] = {
847 { .compatible = "samsung,s3c2440-i2c", .data = EXYNOS_I2C_STD },
851 U_BOOT_DRIVER(i2c_s3c) = {
854 .of_match = s3c_i2c_ids,
855 .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
856 .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
861 * TODO(sjg@chromium.org): Move this to a separate file when everything uses
864 static const struct dm_i2c_ops exynos_hs_i2c_ops = {
865 .xfer = exynos_hs_i2c_xfer,
866 .probe_chip = s3c24x0_i2c_probe,
867 .set_bus_speed = s3c24x0_i2c_set_bus_speed,
870 static const struct udevice_id exynos_hs_i2c_ids[] = {
871 { .compatible = "samsung,exynos5-hsi2c", .data = EXYNOS_I2C_HS },
875 U_BOOT_DRIVER(hs_i2c) = {
876 .name = "i2c_s3c_hs",
878 .of_match = exynos_hs_i2c_ids,
879 .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
880 .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
881 .ops = &exynos_hs_i2c_ops,