3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * SPDX-License-Identifier: GPL-2.0+
8 /* This code should work for both the S3C2400 and the S3C2410
9 * as they seem to have the same I2C controller inside.
10 * The different address mapping is handled by the s3c24xx.h files below.
16 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
17 #include <asm/arch/clk.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/pinmux.h>
21 #include <asm/arch/s3c24x0_cpu.h>
25 #include "s3c24x0_i2c.h"
27 DECLARE_GLOBAL_DATA_PTR;
30 * Wait til the byte transfer is completed.
32 * @param i2c- pointer to the appropriate i2c register bank.
33 * @return I2C_OK, if transmission was ACKED
34 * I2C_NACK, if transmission was NACKED
35 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
38 static int WaitForXfer(struct s3c24x0_i2c *i2c)
40 ulong start_time = get_timer(0);
43 if (readl(&i2c->iiccon) & I2CCON_IRPND)
44 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
46 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
51 static void read_write_byte(struct s3c24x0_i2c *i2c)
53 clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
56 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
58 ulong freq, pres = 16, div;
59 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
64 /* calculate prescaler and divisor values */
65 if ((freq / pres / (16 + 1)) > speed)
66 /* set prescaler to 512 */
70 while ((freq / pres / (div + 1)) > speed)
73 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
74 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
76 /* init to SLAVE REVEIVE and set slaveaddr */
77 writel(0, &i2c->iicstat);
78 writel(slaveadd, &i2c->iicadd);
79 /* program Master Transmit (and implicit STOP) */
80 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
83 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
85 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
87 i2c_bus->clock_frequency = speed;
89 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
90 CONFIG_SYS_I2C_S3C24X0_SLAVE);
96 * cmd_type is 0 for write, 1 for read.
98 * addr_len can take any value from 0-255, it is only limited
99 * by the char, we could make it larger if needed. If it is
100 * 0 we skip the address write cycle.
102 static int i2c_transfer(struct s3c24x0_i2c *i2c,
103 unsigned char cmd_type,
105 unsigned char addr[],
106 unsigned char addr_len,
107 unsigned char data[],
108 unsigned short data_len)
111 ulong start_time = get_timer(0);
113 if (data == 0 || data_len == 0) {
114 /*Don't support data transfer of no length or to address 0 */
115 debug("i2c_transfer: bad call\n");
119 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
120 if (get_timer(start_time) > I2C_TIMEOUT_MS)
124 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
126 /* Get the slave chip address going */
127 writel(chip, &i2c->iicds);
128 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
129 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
132 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
135 /* Wait for chip address to transmit. */
136 result = WaitForXfer(i2c);
137 if (result != I2C_OK)
140 /* If register address needs to be transmitted - do it now. */
141 if (addr && addr_len) {
142 while ((i < addr_len) && (result == I2C_OK)) {
143 writel(addr[i++], &i2c->iicds);
144 read_write_byte(i2c);
145 result = WaitForXfer(i2c);
148 if (result != I2C_OK)
154 while ((i < data_len) && (result == I2C_OK)) {
155 writel(data[i++], &i2c->iicds);
156 read_write_byte(i2c);
157 result = WaitForXfer(i2c);
162 if (addr && addr_len) {
164 * Register address has been sent, now send slave chip
165 * address again to start the actual read transaction.
167 writel(chip, &i2c->iicds);
169 /* Generate a re-START. */
170 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
172 read_write_byte(i2c);
173 result = WaitForXfer(i2c);
175 if (result != I2C_OK)
179 while ((i < data_len) && (result == I2C_OK)) {
180 /* disable ACK for final READ */
181 if (i == data_len - 1)
182 writel(readl(&i2c->iiccon)
185 read_write_byte(i2c);
186 result = WaitForXfer(i2c);
187 data[i++] = readl(&i2c->iicds);
189 if (result == I2C_NACK)
190 result = I2C_OK; /* Normal terminated read. */
194 debug("i2c_transfer: bad call\n");
201 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
202 read_write_byte(i2c);
207 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
209 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
216 * What is needed is to send the chip address and verify that the
217 * address was <ACK>ed (i.e. there was a chip at that address which
218 * drove the data line low).
220 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
222 return ret != I2C_OK;
225 static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
228 struct s3c24x0_i2c *i2c = i2c_bus->regs;
229 bool is_read = msg->flags & I2C_M_RD;
235 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
237 /* Get the slave chip address going */
238 addr = msg->addr << 1;
239 writel(addr, &i2c->iicds);
240 status = I2C_TXRX_ENA | I2C_START_STOP;
242 status |= I2C_MODE_MR;
244 status |= I2C_MODE_MT;
245 writel(status, &i2c->iicstat);
247 read_write_byte(i2c);
249 /* Wait for chip address to transmit */
250 ret = WaitForXfer(i2c);
255 for (i = 0; !ret && i < msg->len; i++) {
256 /* disable ACK for final READ */
257 if (i == msg->len - 1)
258 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
259 read_write_byte(i2c);
260 ret = WaitForXfer(i2c);
261 msg->buf[i] = readl(&i2c->iicds);
264 ret = I2C_OK; /* Normal terminated read */
266 for (i = 0; !ret && i < msg->len; i++) {
267 writel(msg->buf[i], &i2c->iicds);
268 read_write_byte(i2c);
269 ret = WaitForXfer(i2c);
277 static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
280 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
281 struct s3c24x0_i2c *i2c = i2c_bus->regs;
285 start_time = get_timer(0);
286 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
287 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
293 for (ret = 0, i = 0; !ret && i < nmsgs; i++)
294 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
297 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
298 read_write_byte(i2c);
300 return ret ? -EREMOTEIO : 0;
303 static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
305 const void *blob = gd->fdt_blob;
306 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
309 node = dev->of_offset;
311 i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
313 i2c_bus->id = pinmux_decode_periph_id(blob, node);
315 i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
316 "clock-frequency", 100000);
317 i2c_bus->node = node;
318 i2c_bus->bus_num = dev->seq;
320 exynos_pinmux_config(i2c_bus->id, 0);
322 i2c_bus->active = true;
327 static const struct dm_i2c_ops s3c_i2c_ops = {
328 .xfer = s3c24x0_i2c_xfer,
329 .probe_chip = s3c24x0_i2c_probe,
330 .set_bus_speed = s3c24x0_i2c_set_bus_speed,
333 static const struct udevice_id s3c_i2c_ids[] = {
334 { .compatible = "samsung,s3c2440-i2c" },
338 U_BOOT_DRIVER(i2c_s3c) = {
341 .of_match = s3c_i2c_ids,
342 .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
343 .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),