3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * SPDX-License-Identifier: GPL-2.0+
8 /* This code should work for both the S3C2400 and the S3C2410
9 * as they seem to have the same I2C controller inside.
10 * The different address mapping is handled by the s3c24xx.h files below.
15 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
16 #include <asm/arch/clk.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/pinmux.h>
20 #include <asm/arch/s3c24x0_cpu.h>
24 #include "s3c24x0_i2c.h"
26 #ifdef CONFIG_HARD_I2C
34 #define I2C_NOK_LA 3 /* Lost arbitration */
35 #define I2C_NOK_TOUT 4 /* time out */
37 /* HSI2C specific register description */
39 /* I2C_CTL Register bits */
40 #define HSI2C_FUNC_MODE_I2C (1u << 0)
41 #define HSI2C_MASTER (1u << 3)
42 #define HSI2C_RXCHON (1u << 6) /* Write/Send */
43 #define HSI2C_TXCHON (1u << 7) /* Read/Receive */
44 #define HSI2C_SW_RST (1u << 31)
46 /* I2C_FIFO_CTL Register bits */
47 #define HSI2C_RXFIFO_EN (1u << 0)
48 #define HSI2C_TXFIFO_EN (1u << 1)
49 #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
50 #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
52 /* I2C_TRAILING_CTL Register bits */
53 #define HSI2C_TRAILING_COUNT (0xff)
55 /* I2C_INT_EN Register bits */
56 #define HSI2C_TX_UNDERRUN_EN (1u << 2)
57 #define HSI2C_TX_OVERRUN_EN (1u << 3)
58 #define HSI2C_RX_UNDERRUN_EN (1u << 4)
59 #define HSI2C_RX_OVERRUN_EN (1u << 5)
60 #define HSI2C_INT_TRAILING_EN (1u << 6)
61 #define HSI2C_INT_I2C_EN (1u << 9)
63 #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\
64 HSI2C_TX_OVERRUN_EN |\
65 HSI2C_RX_UNDERRUN_EN |\
66 HSI2C_RX_OVERRUN_EN |\
67 HSI2C_INT_TRAILING_EN)
69 /* I2C_CONF Register bits */
70 #define HSI2C_AUTO_MODE (1u << 31)
71 #define HSI2C_10BIT_ADDR_MODE (1u << 30)
72 #define HSI2C_HS_MODE (1u << 29)
74 /* I2C_AUTO_CONF Register bits */
75 #define HSI2C_READ_WRITE (1u << 16)
76 #define HSI2C_STOP_AFTER_TRANS (1u << 17)
77 #define HSI2C_MASTER_RUN (1u << 31)
79 /* I2C_TIMEOUT Register bits */
80 #define HSI2C_TIMEOUT_EN (1u << 31)
82 /* I2C_TRANS_STATUS register bits */
83 #define HSI2C_MASTER_BUSY (1u << 17)
84 #define HSI2C_SLAVE_BUSY (1u << 16)
85 #define HSI2C_TIMEOUT_AUTO (1u << 4)
86 #define HSI2C_NO_DEV (1u << 3)
87 #define HSI2C_NO_DEV_ACK (1u << 2)
88 #define HSI2C_TRANS_ABORT (1u << 1)
89 #define HSI2C_TRANS_SUCCESS (1u << 0)
90 #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\
91 HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
93 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
96 /* I2C_FIFO_STAT Register bits */
97 #define HSI2C_RX_FIFO_EMPTY (1u << 24)
98 #define HSI2C_RX_FIFO_FULL (1u << 23)
99 #define HSI2C_TX_FIFO_EMPTY (1u << 8)
100 #define HSI2C_TX_FIFO_FULL (1u << 7)
101 #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f)
102 #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f)
104 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
106 /* S3C I2C Controller bits */
107 #define I2CSTAT_BSY 0x20 /* Busy bit */
108 #define I2CSTAT_NACK 0x01 /* Nack bit */
109 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
110 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
111 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
112 #define I2C_MODE_MR 0x80 /* Master Receive Mode */
113 #define I2C_START_STOP 0x20 /* START / STOP */
114 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
116 #define I2C_TIMEOUT_MS 1000 /* 1 second */
118 #define HSI2C_TIMEOUT_US 100000 /* 100 ms, finer granularity */
121 /* To support VCMA9 boards and other who dont define max_i2c_num */
122 #ifndef CONFIG_MAX_I2C_NUM
123 #define CONFIG_MAX_I2C_NUM 1
127 * For SPL boot some boards need i2c before SDRAM is initialised so force
128 * variables to live in SRAM
130 static unsigned int g_current_bus __attribute__((section(".data")));
131 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
132 __attribute__((section(".data")));
135 * Get a pointer to the given bus index
137 * @bus_idx: Bus index to look up
138 * @return pointer to bus, or NULL if invalid or not available
140 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
142 if (bus_idx < ARRAY_SIZE(i2c_bus)) {
143 struct s3c24x0_i2c_bus *bus;
145 bus = &i2c_bus[bus_idx];
150 debug("Undefined bus: %d\n", bus_idx);
154 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
155 static int GetI2CSDA(void)
157 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
159 #ifdef CONFIG_S3C2410
160 return (readl(&gpio->gpedat) & 0x8000) >> 15;
162 #ifdef CONFIG_S3C2400
163 return (readl(&gpio->pgdat) & 0x0020) >> 5;
167 static void SetI2CSCL(int x)
169 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
171 #ifdef CONFIG_S3C2410
172 writel((readl(&gpio->gpedat) & ~0x4000) |
173 (x & 1) << 14, &gpio->gpedat);
175 #ifdef CONFIG_S3C2400
176 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
182 * Wait til the byte transfer is completed.
184 * @param i2c- pointer to the appropriate i2c register bank.
185 * @return I2C_OK, if transmission was ACKED
186 * I2C_NACK, if transmission was NACKED
187 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
190 static int WaitForXfer(struct s3c24x0_i2c *i2c)
192 ulong start_time = get_timer(0);
195 if (readl(&i2c->iiccon) & I2CCON_IRPND)
196 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
198 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
204 * Wait for transfer completion.
206 * This function reads the interrupt status register waiting for the INT_I2C
207 * bit to be set, which indicates copletion of a transaction.
209 * @param i2c: pointer to the appropriate register bank
211 * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
212 * the status bits do not get set in time, or an approrpiate error
213 * value in case of transfer errors.
215 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
217 int i = HSI2C_TIMEOUT_US;
220 u32 int_status = readl(&i2c->usi_int_stat);
222 if (int_status & HSI2C_INT_I2C_EN) {
223 u32 trans_status = readl(&i2c->usi_trans_status);
225 /* Deassert pending interrupt. */
226 writel(int_status, &i2c->usi_int_stat);
228 if (trans_status & HSI2C_NO_DEV_ACK) {
229 debug("%s: no ACK from device\n", __func__);
232 if (trans_status & HSI2C_NO_DEV) {
233 debug("%s: no device\n", __func__);
236 if (trans_status & HSI2C_TRANS_ABORT) {
237 debug("%s: arbitration lost\n", __func__);
240 if (trans_status & HSI2C_TIMEOUT_AUTO) {
241 debug("%s: device timed out\n", __func__);
248 debug("%s: transaction timeout!\n", __func__);
252 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
254 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
257 static struct s3c24x0_i2c *get_base_i2c(void)
259 #ifdef CONFIG_EXYNOS4
260 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
261 + (EXYNOS4_I2C_SPACING
264 #elif defined CONFIG_EXYNOS5
265 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
266 + (EXYNOS5_I2C_SPACING
270 return s3c24x0_get_base_i2c();
274 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
276 ulong freq, pres = 16, div;
277 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
278 freq = get_i2c_clk();
282 /* calculate prescaler and divisor values */
283 if ((freq / pres / (16 + 1)) > speed)
284 /* set prescaler to 512 */
288 while ((freq / pres / (div + 1)) > speed)
291 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
292 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
294 /* init to SLAVE REVEIVE and set slaveaddr */
295 writel(0, &i2c->iicstat);
296 writel(slaveadd, &i2c->iicadd);
297 /* program Master Transmit (and implicit STOP) */
298 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
301 #ifdef CONFIG_I2C_MULTI_BUS
302 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
304 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
306 unsigned int op_clk = i2c_bus->clock_frequency;
307 unsigned int i = 0, utemp0 = 0, utemp1 = 0;
308 unsigned int t_ftl_cycle;
310 #if defined CONFIG_EXYNOS5
311 clkin = get_i2c_clk();
314 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
315 * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
316 * uTemp1 = (TSCLK_L + TSCLK_H + 2)
317 * uTemp2 = TSCLK_L + TSCLK_H
319 t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
320 utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
322 /* CLK_DIV max is 256 */
323 for (i = 0; i < 256; i++) {
324 utemp1 = utemp0 / (i + 1);
325 if ((utemp1 < 512) && (utemp1 > 4)) {
326 i2c_bus->clk_cycle = utemp1 - 2;
327 i2c_bus->clk_div = i;
335 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
337 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
338 unsigned int t_sr_release;
339 unsigned int n_clkdiv;
340 unsigned int t_start_su, t_start_hd;
341 unsigned int t_stop_su;
342 unsigned int t_data_su, t_data_hd;
343 unsigned int t_scl_l, t_scl_h;
349 n_clkdiv = i2c_bus->clk_div;
350 t_scl_l = i2c_bus->clk_cycle / 2;
351 t_scl_h = i2c_bus->clk_cycle / 2;
352 t_start_su = t_scl_l;
353 t_start_hd = t_scl_l;
355 t_data_su = t_scl_l / 2;
356 t_data_hd = t_scl_l / 2;
357 t_sr_release = i2c_bus->clk_cycle;
359 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
360 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
361 i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
362 i2c_timing_sla = t_data_hd << 0;
364 writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
366 /* Clear to enable Timeout */
367 clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
370 writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
372 /* Enable completion conditions' reporting. */
373 writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
376 writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
378 /* Currently operating in Fast speed mode. */
379 writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
380 writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
381 writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
382 writel(i2c_timing_sla, &hsregs->usi_timing_sla);
385 /* SW reset for the high speed bus */
386 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
388 struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
391 /* Set and clear the bit for reset */
392 i2c_ctl = readl(&i2c->usi_ctl);
393 i2c_ctl |= HSI2C_SW_RST;
394 writel(i2c_ctl, &i2c->usi_ctl);
396 i2c_ctl = readl(&i2c->usi_ctl);
397 i2c_ctl &= ~HSI2C_SW_RST;
398 writel(i2c_ctl, &i2c->usi_ctl);
400 /* Initialize the configure registers */
401 hsi2c_ch_init(i2c_bus);
405 * MULTI BUS I2C support
408 #ifdef CONFIG_I2C_MULTI_BUS
409 int i2c_set_bus_num(unsigned int bus)
411 struct s3c24x0_i2c_bus *i2c_bus;
413 i2c_bus = get_bus(bus);
418 if (i2c_bus->is_highspeed) {
419 if (hsi2c_get_clk_details(i2c_bus))
421 hsi2c_ch_init(i2c_bus);
423 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
424 CONFIG_SYS_I2C_SLAVE);
430 unsigned int i2c_get_bus_num(void)
432 return g_current_bus;
436 void i2c_init(int speed, int slaveadd)
438 struct s3c24x0_i2c *i2c;
439 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
440 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
442 ulong start_time = get_timer(0);
444 /* By default i2c channel 0 is the current bus */
446 i2c = get_base_i2c();
449 * In case the previous transfer is still going, wait to give it a
452 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
453 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
454 printf("%s: I2C bus busy for %p\n", __func__,
460 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
463 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
464 #ifdef CONFIG_S3C2410
465 ulong old_gpecon = readl(&gpio->gpecon);
467 #ifdef CONFIG_S3C2400
468 ulong old_gpecon = readl(&gpio->pgcon);
470 /* bus still busy probably by (most) previously interrupted
473 #ifdef CONFIG_S3C2410
474 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
475 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
478 #ifdef CONFIG_S3C2400
479 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
480 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
484 /* toggle I2CSCL until bus idle */
488 while ((i > 0) && (GetI2CSDA() != 1)) {
498 /* restore pin functions */
499 #ifdef CONFIG_S3C2410
500 writel(old_gpecon, &gpio->gpecon);
502 #ifdef CONFIG_S3C2400
503 writel(old_gpecon, &gpio->pgcon);
506 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
507 i2c_ch_init(i2c, speed, slaveadd);
511 * Poll the appropriate bit of the fifo status register until the interface is
512 * ready to process the next byte or timeout expires.
514 * In addition to the FIFO status register this function also polls the
515 * interrupt status register to be able to detect unexpected transaction
518 * When FIFO is ready to process the next byte, this function returns I2C_OK.
519 * If in course of polling the INT_I2C assertion is detected, the function
520 * returns I2C_NOK. If timeout happens before any of the above conditions is
521 * met - the function returns I2C_NOK_TOUT;
523 * @param i2c: pointer to the appropriate i2c register bank.
524 * @param rx_transfer: set to True if the receive transaction is in progress.
525 * @return: as described above.
527 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
529 u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
530 int i = HSI2C_TIMEOUT_US;
532 while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
533 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
535 * There is a chance that assertion of
536 * HSI2C_INT_I2C_EN and deassertion of
537 * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
538 * give FIFO status priority and check it one more
539 * time before reporting interrupt. The interrupt will
540 * be reported next time this function is called.
543 !(readl(&i2c->usi_fifo_stat) & fifo_bit))
548 debug("%s: FIFO polling timeout!\n", __func__);
557 * Preapre hsi2c transaction, either read or write.
559 * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
562 * @param i2c: pointer to the appropriate i2c register bank.
563 * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
564 * @param len: number of bytes expected to be sent or received
565 * @param rx_transfer: set to true for receive transactions
566 * @param: issue_stop: set to true if i2c stop condition should be generated
567 * after this transaction.
568 * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
571 static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
579 conf = len | HSI2C_MASTER_RUN;
582 conf |= HSI2C_STOP_AFTER_TRANS;
584 /* Clear to enable Timeout */
585 writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
587 /* Set slave address */
588 writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
591 /* i2c master, read transaction */
592 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
595 /* read up to len bytes, stop after transaction is finished */
596 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
598 /* i2c master, write transaction */
599 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
602 /* write up to len bytes, stop after transaction is finished */
603 writel(conf, &i2c->usi_auto_conf);
606 /* Reset all pending interrupt status bits we care about, if any */
607 writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
613 * Wait while i2c bus is settling down (mostly stop gets completed).
615 static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
617 int i = HSI2C_TIMEOUT_US;
619 while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
621 debug("%s: bus busy\n", __func__);
629 static int hsi2c_write(struct exynos5_hsi2c *i2c,
631 unsigned char addr[],
633 unsigned char data[],
640 /* Writes of zero length not supported in auto mode. */
641 debug("%s: zero length writes not supported\n", __func__);
645 rv = hsi2c_prepare_transaction
646 (i2c, chip, len + alen, false, issue_stop);
650 /* Move address, if any, and the data, if any, into the FIFO. */
651 for (i = 0; i < alen; i++) {
652 rv = hsi2c_poll_fifo(i2c, false);
654 debug("%s: address write failed\n", __func__);
657 writel(addr[i], &i2c->usi_txdata);
660 for (i = 0; i < len; i++) {
661 rv = hsi2c_poll_fifo(i2c, false);
663 debug("%s: data write failed\n", __func__);
666 writel(data[i], &i2c->usi_txdata);
669 rv = hsi2c_wait_for_trx(i2c);
673 int tmp_ret = hsi2c_wait_while_busy(i2c);
678 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
682 static int hsi2c_read(struct exynos5_hsi2c *i2c,
684 unsigned char addr[],
686 unsigned char data[],
690 bool drop_data = false;
693 /* Reads of zero length not supported in auto mode. */
694 debug("%s: zero length read adjusted\n", __func__);
700 /* Internal register adress needs to be written first. */
701 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
706 rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
711 for (i = 0; i < len; i++) {
712 rv = hsi2c_poll_fifo(i2c, true);
717 data[i] = readl(&i2c->usi_rxdata);
720 rv = hsi2c_wait_for_trx(i2c);
723 tmp_ret = hsi2c_wait_while_busy(i2c);
727 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
732 * cmd_type is 0 for write, 1 for read.
734 * addr_len can take any value from 0-255, it is only limited
735 * by the char, we could make it larger if needed. If it is
736 * 0 we skip the address write cycle.
738 static int i2c_transfer(struct s3c24x0_i2c *i2c,
739 unsigned char cmd_type,
741 unsigned char addr[],
742 unsigned char addr_len,
743 unsigned char data[],
744 unsigned short data_len)
747 ulong start_time = get_timer(0);
749 if (data == 0 || data_len == 0) {
750 /*Don't support data transfer of no length or to address 0 */
751 debug("i2c_transfer: bad call\n");
755 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
756 if (get_timer(start_time) > I2C_TIMEOUT_MS)
760 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
762 /* Get the slave chip address going */
763 writel(chip, &i2c->iicds);
764 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
765 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
768 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
771 /* Wait for chip address to transmit. */
772 result = WaitForXfer(i2c);
773 if (result != I2C_OK)
776 /* If register address needs to be transmitted - do it now. */
777 if (addr && addr_len) {
778 while ((i < addr_len) && (result == I2C_OK)) {
779 writel(addr[i++], &i2c->iicds);
781 result = WaitForXfer(i2c);
784 if (result != I2C_OK)
790 while ((i < data_len) && (result == I2C_OK)) {
791 writel(data[i++], &i2c->iicds);
793 result = WaitForXfer(i2c);
798 if (addr && addr_len) {
800 * Register address has been sent, now send slave chip
801 * address again to start the actual read transaction.
803 writel(chip, &i2c->iicds);
805 /* Generate a re-START. */
806 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
809 result = WaitForXfer(i2c);
811 if (result != I2C_OK)
815 while ((i < data_len) && (result == I2C_OK)) {
816 /* disable ACK for final READ */
817 if (i == data_len - 1)
818 writel(readl(&i2c->iiccon)
822 result = WaitForXfer(i2c);
823 data[i++] = readl(&i2c->iicds);
825 if (result == I2C_NACK)
826 result = I2C_OK; /* Normal terminated read. */
830 debug("i2c_transfer: bad call\n");
837 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
843 int i2c_probe(uchar chip)
845 struct s3c24x0_i2c_bus *i2c_bus;
849 i2c_bus = get_bus(g_current_bus);
855 * What is needed is to send the chip address and verify that the
856 * address was <ACK>ed (i.e. there was a chip at that address which
857 * drove the data line low).
859 if (i2c_bus->is_highspeed) {
860 ret = hsi2c_read(i2c_bus->hsregs,
863 ret = i2c_transfer(i2c_bus->regs,
864 I2C_READ, chip << 1, 0, 0, buf, 1);
868 return ret != I2C_OK;
871 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
873 struct s3c24x0_i2c_bus *i2c_bus;
878 debug("I2C read: addr len %d not supported\n", alen);
883 xaddr[0] = (addr >> 24) & 0xFF;
884 xaddr[1] = (addr >> 16) & 0xFF;
885 xaddr[2] = (addr >> 8) & 0xFF;
886 xaddr[3] = addr & 0xFF;
889 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
891 * EEPROM chips that implement "address overflow" are ones
892 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
893 * address and the extra bits end up in the "chip address"
894 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
895 * four 256 byte chips.
897 * Note that we consider the length of the address field to
898 * still be one byte because the extra address bits are
899 * hidden in the chip address.
902 chip |= ((addr >> (alen * 8)) &
903 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
905 i2c_bus = get_bus(g_current_bus);
909 if (i2c_bus->is_highspeed)
910 ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen],
913 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1,
914 &xaddr[4 - alen], alen, buffer, len);
917 if (i2c_bus->is_highspeed)
918 exynos5_i2c_reset(i2c_bus);
919 debug("I2c read failed %d\n", ret);
925 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
927 struct s3c24x0_i2c_bus *i2c_bus;
932 debug("I2C write: addr len %d not supported\n", alen);
937 xaddr[0] = (addr >> 24) & 0xFF;
938 xaddr[1] = (addr >> 16) & 0xFF;
939 xaddr[2] = (addr >> 8) & 0xFF;
940 xaddr[3] = addr & 0xFF;
942 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
944 * EEPROM chips that implement "address overflow" are ones
945 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
946 * address and the extra bits end up in the "chip address"
947 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
948 * four 256 byte chips.
950 * Note that we consider the length of the address field to
951 * still be one byte because the extra address bits are
952 * hidden in the chip address.
955 chip |= ((addr >> (alen * 8)) &
956 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
958 i2c_bus = get_bus(g_current_bus);
962 if (i2c_bus->is_highspeed)
963 ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen],
964 alen, buffer, len, true);
966 ret = i2c_transfer(i2c_bus->regs, I2C_WRITE, chip << 1,
967 &xaddr[4 - alen], alen, buffer, len);
970 if (i2c_bus->is_highspeed)
971 exynos5_i2c_reset(i2c_bus);
978 #ifdef CONFIG_OF_CONTROL
979 static void process_nodes(const void *blob, int node_list[], int count,
982 struct s3c24x0_i2c_bus *bus;
985 for (i = 0; i < count; i++) {
986 int node = node_list[i];
993 bus->is_highspeed = is_highspeed;
996 bus->hsregs = (struct exynos5_hsi2c *)
997 fdtdec_get_addr(blob, node, "reg");
999 bus->regs = (struct s3c24x0_i2c *)
1000 fdtdec_get_addr(blob, node, "reg");
1002 bus->id = pinmux_decode_periph_id(blob, node);
1003 bus->clock_frequency = fdtdec_get_int(blob, node,
1005 CONFIG_SYS_I2C_SPEED);
1008 exynos_pinmux_config(bus->id, 0);
1010 /* Mark position as used */
1015 void board_i2c_init(const void *blob)
1017 int node_list[CONFIG_MAX_I2C_NUM];
1020 /* First get the normal i2c ports */
1021 count = fdtdec_find_aliases_for_id(blob, "i2c",
1022 COMPAT_SAMSUNG_S3C2440_I2C, node_list,
1023 CONFIG_MAX_I2C_NUM);
1024 process_nodes(blob, node_list, count, 0);
1026 /* Now look for high speed i2c ports */
1027 count = fdtdec_find_aliases_for_id(blob, "i2c",
1028 COMPAT_SAMSUNG_EXYNOS5_I2C, node_list,
1029 CONFIG_MAX_I2C_NUM);
1030 process_nodes(blob, node_list, count, 1);
1034 int i2c_get_bus_num_fdt(int node)
1038 for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) {
1039 if (node == i2c_bus[i].node)
1043 debug("%s: Can't find any matched I2C bus\n", __func__);
1047 #ifdef CONFIG_I2C_MULTI_BUS
1048 int i2c_reset_port_fdt(const void *blob, int node)
1050 struct s3c24x0_i2c_bus *i2c_bus;
1053 bus = i2c_get_bus_num_fdt(node);
1055 debug("could not get bus for node %d\n", node);
1059 i2c_bus = get_bus(bus);
1061 debug("get_bus() failed for node node %d\n", node);
1065 if (i2c_bus->is_highspeed) {
1066 if (hsi2c_get_clk_details(i2c_bus))
1068 hsi2c_ch_init(i2c_bus);
1070 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
1071 CONFIG_SYS_I2C_SLAVE);
1079 #endif /* CONFIG_HARD_I2C */