1 // SPDX-License-Identifier: GPL-2.0+
4 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
11 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
13 #include <asm/arch/clk.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/pinmux.h>
17 #include <asm/arch/s3c24x0_cpu.h>
19 #include <asm/global_data.h>
22 #include "s3c24x0_i2c.h"
24 DECLARE_GLOBAL_DATA_PTR;
27 * Wait til the byte transfer is completed.
29 * @param i2c- pointer to the appropriate i2c register bank.
30 * @return I2C_OK, if transmission was ACKED
31 * I2C_NACK, if transmission was NACKED
32 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
35 static int WaitForXfer(struct s3c24x0_i2c *i2c)
37 ulong start_time = get_timer(0);
40 if (readl(&i2c->iiccon) & I2CCON_IRPND)
41 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
43 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
48 static void read_write_byte(struct s3c24x0_i2c *i2c)
50 clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
53 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
55 ulong freq, pres = 16, div;
56 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
61 /* calculate prescaler and divisor values */
62 if ((freq / pres / (16 + 1)) > speed)
63 /* set prescaler to 512 */
67 while ((freq / pres / (div + 1)) > speed)
70 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
71 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
73 /* init to SLAVE REVEIVE and set slaveaddr */
74 writel(0, &i2c->iicstat);
75 writel(slaveadd, &i2c->iicadd);
76 /* program Master Transmit (and implicit STOP) */
77 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
80 #define SYS_I2C_S3C24X0_SLAVE_ADDR 0
82 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
84 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
86 i2c_bus->clock_frequency = speed;
88 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
89 SYS_I2C_S3C24X0_SLAVE_ADDR);
95 * cmd_type is 0 for write, 1 for read.
97 * addr_len can take any value from 0-255, it is only limited
98 * by the char, we could make it larger if needed. If it is
99 * 0 we skip the address write cycle.
101 static int i2c_transfer(struct s3c24x0_i2c *i2c,
102 unsigned char cmd_type,
104 unsigned char addr[],
105 unsigned char addr_len,
106 unsigned char data[],
107 unsigned short data_len)
110 ulong start_time = get_timer(0);
112 if (data == 0 || data_len == 0) {
113 /*Don't support data transfer of no length or to address 0 */
114 debug("i2c_transfer: bad call\n");
118 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
119 if (get_timer(start_time) > I2C_TIMEOUT_MS)
123 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
125 /* Get the slave chip address going */
126 writel(chip, &i2c->iicds);
127 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
128 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
131 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
134 /* Wait for chip address to transmit. */
135 result = WaitForXfer(i2c);
136 if (result != I2C_OK)
139 /* If register address needs to be transmitted - do it now. */
140 if (addr && addr_len) {
141 while ((i < addr_len) && (result == I2C_OK)) {
142 writel(addr[i++], &i2c->iicds);
143 read_write_byte(i2c);
144 result = WaitForXfer(i2c);
147 if (result != I2C_OK)
153 while ((i < data_len) && (result == I2C_OK)) {
154 writel(data[i++], &i2c->iicds);
155 read_write_byte(i2c);
156 result = WaitForXfer(i2c);
161 if (addr && addr_len) {
163 * Register address has been sent, now send slave chip
164 * address again to start the actual read transaction.
166 writel(chip, &i2c->iicds);
168 /* Generate a re-START. */
169 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
171 read_write_byte(i2c);
172 result = WaitForXfer(i2c);
174 if (result != I2C_OK)
178 while ((i < data_len) && (result == I2C_OK)) {
179 /* disable ACK for final READ */
180 if (i == data_len - 1)
181 writel(readl(&i2c->iiccon)
184 read_write_byte(i2c);
185 result = WaitForXfer(i2c);
186 data[i++] = readl(&i2c->iicds);
188 if (result == I2C_NACK)
189 result = I2C_OK; /* Normal terminated read. */
193 debug("i2c_transfer: bad call\n");
200 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
201 read_write_byte(i2c);
206 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
208 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
215 * What is needed is to send the chip address and verify that the
216 * address was <ACK>ed (i.e. there was a chip at that address which
217 * drove the data line low).
219 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
221 return ret != I2C_OK;
224 static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
227 struct s3c24x0_i2c *i2c = i2c_bus->regs;
228 bool is_read = msg->flags & I2C_M_RD;
234 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
236 /* Get the slave chip address going */
237 addr = msg->addr << 1;
238 writel(addr, &i2c->iicds);
239 status = I2C_TXRX_ENA | I2C_START_STOP;
241 status |= I2C_MODE_MR;
243 status |= I2C_MODE_MT;
244 writel(status, &i2c->iicstat);
246 read_write_byte(i2c);
248 /* Wait for chip address to transmit */
249 ret = WaitForXfer(i2c);
254 for (i = 0; !ret && i < msg->len; i++) {
255 /* disable ACK for final READ */
256 if (i == msg->len - 1)
257 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
258 read_write_byte(i2c);
259 ret = WaitForXfer(i2c);
260 msg->buf[i] = readl(&i2c->iicds);
263 ret = I2C_OK; /* Normal terminated read */
265 for (i = 0; !ret && i < msg->len; i++) {
266 writel(msg->buf[i], &i2c->iicds);
267 read_write_byte(i2c);
268 ret = WaitForXfer(i2c);
276 static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
279 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
280 struct s3c24x0_i2c *i2c = i2c_bus->regs;
284 start_time = get_timer(0);
285 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
286 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
292 for (ret = 0, i = 0; !ret && i < nmsgs; i++)
293 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
296 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
297 read_write_byte(i2c);
299 return ret ? -EREMOTEIO : 0;
302 static int s3c_i2c_of_to_plat(struct udevice *dev)
304 const void *blob = gd->fdt_blob;
305 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
308 node = dev_of_offset(dev);
310 i2c_bus->regs = dev_read_addr_ptr(dev);
312 i2c_bus->id = pinmux_decode_periph_id(blob, node);
314 i2c_bus->clock_frequency =
315 dev_read_u32_default(dev, "clock-frequency",
316 I2C_SPEED_STANDARD_RATE);
317 i2c_bus->node = node;
318 i2c_bus->bus_num = dev_seq(dev);
320 exynos_pinmux_config(i2c_bus->id, 0);
322 i2c_bus->active = true;
327 static const struct dm_i2c_ops s3c_i2c_ops = {
328 .xfer = s3c24x0_i2c_xfer,
329 .probe_chip = s3c24x0_i2c_probe,
330 .set_bus_speed = s3c24x0_i2c_set_bus_speed,
333 static const struct udevice_id s3c_i2c_ids[] = {
334 { .compatible = "samsung,s3c2440-i2c" },
338 U_BOOT_DRIVER(i2c_s3c) = {
341 .of_match = s3c_i2c_ids,
342 .of_to_plat = s3c_i2c_of_to_plat,
343 .priv_auto = sizeof(struct s3c24x0_i2c_bus),