drivers/i2c/s3c24x0_i2c.c

   1 /*
   2  * (C) Copyright 2002
   3  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* This code should work for both the S3C2400 and the S3C2410
  25  * as they seem to have the same I2C controller inside.
  26  * The different address mapping is handled by the s3c24xx.h files below.
  27  */
  28
  29 #include <common.h>
  30 #ifdef CONFIG_EXYNOS5
  31 #include <asm/arch/clk.h>
  32 #include <asm/arch/cpu.h>
  33 #else
  34 #include <asm/arch/s3c24x0_cpu.h>
  35 #endif
  36 #include <asm/io.h>
  37 #include <i2c.h>
  38 #include "s3c24x0_i2c.h"
  39
  40 #ifdef CONFIG_HARD_I2C
  41
  42 #define I2C_WRITE       0
  43 #define I2C_READ        1
  44
  45 #define I2C_OK          0
  46 #define I2C_NOK         1
  47 #define I2C_NACK        2
  48 #define I2C_NOK_LA      3       /* Lost arbitration */
  49 #define I2C_NOK_TOUT    4       /* time out */
  50
  51 #define I2CSTAT_BSY     0x20    /* Busy bit */
  52 #define I2CSTAT_NACK    0x01    /* Nack bit */
  53 #define I2CCON_ACKGEN   0x80    /* Acknowledge generation */
  54 #define I2CCON_IRPND    0x10    /* Interrupt pending bit */
  55 #define I2C_MODE_MT     0xC0    /* Master Transmit Mode */
  56 #define I2C_MODE_MR     0x80    /* Master Receive Mode */
  57 #define I2C_START_STOP  0x20    /* START / STOP */
  58 #define I2C_TXRX_ENA    0x10    /* I2C Tx/Rx enable */
  59
  60 #define I2C_TIMEOUT 1           /* 1 second */
  61
  62
  63 static unsigned int g_current_bus;      /* Stores Current I2C Bus */
  64
  65 #ifndef CONFIG_EXYNOS5
  66 static int GetI2CSDA(void)
  67 {
  68         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
  69
  70 #ifdef CONFIG_S3C2410
  71         return (readl(&gpio->gpedat) & 0x8000) >> 15;
  72 #endif
  73 #ifdef CONFIG_S3C2400
  74         return (readl(&gpio->pgdat) & 0x0020) >> 5;
  75 #endif
  76 }
  77
  78 #if 0
  79 static void SetI2CSDA(int x)
  80 {
  81         rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
  82 }
  83 #endif
  84
  85 static void SetI2CSCL(int x)
  86 {
  87         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
  88
  89 #ifdef CONFIG_S3C2410
  90         writel((readl(&gpio->gpedat) & ~0x4000) |
  91                                         (x & 1) << 14, &gpio->gpedat);
  92 #endif
  93 #ifdef CONFIG_S3C2400
  94         writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
  95 #endif
  96 }
  97 #endif
  98
  99 static int WaitForXfer(struct s3c24x0_i2c *i2c)
 100 {
 101         int i;
 102
 103         i = I2C_TIMEOUT * 10000;
 104         while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
 105                 udelay(100);
 106                 i--;
 107         }
 108
 109         return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
 110 }
 111
 112 static int IsACK(struct s3c24x0_i2c *i2c)
 113 {
 114         return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
 115 }
 116
 117 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
 118 {
 119         writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 120 }
 121
 122 static struct s3c24x0_i2c *get_base_i2c(void)
 123 {
 124 #ifdef CONFIG_EXYNOS5
 125         struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 126                                                         + (EXYNOS5_I2C_SPACING
 127                                                         * g_current_bus));
 128         return i2c;
 129 #else
 130         return s3c24x0_get_base_i2c();
 131 #endif
 132 }
 133
 134 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
 135 {
 136         ulong freq, pres = 16, div;
 137 #ifdef CONFIG_EXYNOS5
 138         freq = get_i2c_clk();
 139 #else
 140         freq = get_PCLK();
 141 #endif
 142         /* calculate prescaler and divisor values */
 143         if ((freq / pres / (16 + 1)) > speed)
 144                 /* set prescaler to 512 */
 145                 pres = 512;
 146
 147         div = 0;
 148         while ((freq / pres / (div + 1)) > speed)
 149                 div++;
 150
 151         /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
 152         writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
 153
 154         /* init to SLAVE REVEIVE and set slaveaddr */
 155         writel(0, &i2c->iicstat);
 156         writel(slaveadd, &i2c->iicadd);
 157         /* program Master Transmit (and implicit STOP) */
 158         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 159 }
 160
 161 /*
 162  * MULTI BUS I2C support
 163  */
 164
 165 #ifdef CONFIG_I2C_MULTI_BUS
 166 int i2c_set_bus_num(unsigned int bus)
 167 {
 168         struct s3c24x0_i2c *i2c;
 169
 170         if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
 171                 debug("Bad bus: %d\n", bus);
 172                 return -1;
 173         }
 174
 175         g_current_bus = bus;
 176         i2c = get_base_i2c();
 177         i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 178
 179         return 0;
 180 }
 181
 182 unsigned int i2c_get_bus_num(void)
 183 {
 184         return g_current_bus;
 185 }
 186 #endif
 187
 188 void i2c_init(int speed, int slaveadd)
 189 {
 190         struct s3c24x0_i2c *i2c;
 191 #ifndef CONFIG_EXYNOS5
 192         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 193 #endif
 194         int i;
 195
 196         /* By default i2c channel 0 is the current bus */
 197         g_current_bus = 0;
 198         i2c = get_base_i2c();
 199
 200         /* wait for some time to give previous transfer a chance to finish */
 201         i = I2C_TIMEOUT * 1000;
 202         while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
 203                 udelay(1000);
 204                 i--;
 205         }
 206
 207 #ifndef CONFIG_EXYNOS5
 208         if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
 209 #ifdef CONFIG_S3C2410
 210                 ulong old_gpecon = readl(&gpio->gpecon);
 211 #endif
 212 #ifdef CONFIG_S3C2400
 213                 ulong old_gpecon = readl(&gpio->pgcon);
 214 #endif
 215                 /* bus still busy probably by (most) previously interrupted
 216                    transfer */
 217
 218 #ifdef CONFIG_S3C2410
 219                 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
 220                 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
 221                        &gpio->gpecon);
 222 #endif
 223 #ifdef CONFIG_S3C2400
 224                 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
 225                 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
 226                        &gpio->pgcon);
 227 #endif
 228
 229                 /* toggle I2CSCL until bus idle */
 230                 SetI2CSCL(0);
 231                 udelay(1000);
 232                 i = 10;
 233                 while ((i > 0) && (GetI2CSDA() != 1)) {
 234                         SetI2CSCL(1);
 235                         udelay(1000);
 236                         SetI2CSCL(0);
 237                         udelay(1000);
 238                         i--;
 239                 }
 240                 SetI2CSCL(1);
 241                 udelay(1000);
 242
 243                 /* restore pin functions */
 244 #ifdef CONFIG_S3C2410
 245                 writel(old_gpecon, &gpio->gpecon);
 246 #endif
 247 #ifdef CONFIG_S3C2400
 248                 writel(old_gpecon, &gpio->pgcon);
 249 #endif
 250         }
 251 #endif /* #ifndef CONFIG_EXYNOS5 */
 252         i2c_ch_init(i2c, speed, slaveadd);
 253 }
 254
 255 /*
 256  * cmd_type is 0 for write, 1 for read.
 257  *
 258  * addr_len can take any value from 0-255, it is only limited
 259  * by the char, we could make it larger if needed. If it is
 260  * 0 we skip the address write cycle.
 261  */
 262 static int i2c_transfer(struct s3c24x0_i2c *i2c,
 263                         unsigned char cmd_type,
 264                         unsigned char chip,
 265                         unsigned char addr[],
 266                         unsigned char addr_len,
 267                         unsigned char data[],
 268                         unsigned short data_len)
 269 {
 270         int i, result;
 271
 272         if (data == 0 || data_len == 0) {
 273                 /*Don't support data transfer of no length or to address 0 */
 274                 debug("i2c_transfer: bad call\n");
 275                 return I2C_NOK;
 276         }
 277
 278         /* Check I2C bus idle */
 279         i = I2C_TIMEOUT * 1000;
 280         while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
 281                 udelay(1000);
 282                 i--;
 283         }
 284
 285         if (readl(&i2c->iicstat) & I2CSTAT_BSY)
 286                 return I2C_NOK_TOUT;
 287
 288         writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
 289         result = I2C_OK;
 290
 291         switch (cmd_type) {
 292         case I2C_WRITE:
 293                 if (addr && addr_len) {
 294                         writel(chip, &i2c->iicds);
 295                         /* send START */
 296                         writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 297                                &i2c->iicstat);
 298                         i = 0;
 299                         while ((i < addr_len) && (result == I2C_OK)) {
 300                                 result = WaitForXfer(i2c);
 301                                 writel(addr[i], &i2c->iicds);
 302                                 ReadWriteByte(i2c);
 303                                 i++;
 304                         }
 305                         i = 0;
 306                         while ((i < data_len) && (result == I2C_OK)) {
 307                                 result = WaitForXfer(i2c);
 308                                 writel(data[i], &i2c->iicds);
 309                                 ReadWriteByte(i2c);
 310                                 i++;
 311                         }
 312                 } else {
 313                         writel(chip, &i2c->iicds);
 314                         /* send START */
 315                         writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 316                                &i2c->iicstat);
 317                         i = 0;
 318                         while ((i < data_len) && (result = I2C_OK)) {
 319                                 result = WaitForXfer(i2c);
 320                                 writel(data[i], &i2c->iicds);
 321                                 ReadWriteByte(i2c);
 322                                 i++;
 323                         }
 324                 }
 325
 326                 if (result == I2C_OK)
 327                         result = WaitForXfer(i2c);
 328
 329                 /* send STOP */
 330                 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 331                 ReadWriteByte(i2c);
 332                 break;
 333
 334         case I2C_READ:
 335                 if (addr && addr_len) {
 336                         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 337                         writel(chip, &i2c->iicds);
 338                         /* send START */
 339                         writel(readl(&i2c->iicstat) | I2C_START_STOP,
 340                                &i2c->iicstat);
 341                         result = WaitForXfer(i2c);
 342                         if (IsACK(i2c)) {
 343                                 i = 0;
 344                                 while ((i < addr_len) && (result == I2C_OK)) {
 345                                         writel(addr[i], &i2c->iicds);
 346                                         ReadWriteByte(i2c);
 347                                         result = WaitForXfer(i2c);
 348                                         i++;
 349                                 }
 350
 351                                 writel(chip, &i2c->iicds);
 352                                 /* resend START */
 353                                 writel(I2C_MODE_MR | I2C_TXRX_ENA |
 354                                        I2C_START_STOP, &i2c->iicstat);
 355                         ReadWriteByte(i2c);
 356                         result = WaitForXfer(i2c);
 357                                 i = 0;
 358                                 while ((i < data_len) && (result == I2C_OK)) {
 359                                         /* disable ACK for final READ */
 360                                         if (i == data_len - 1)
 361                                                 writel(readl(&i2c->iiccon)
 362                                                         & ~I2CCON_ACKGEN,
 363                                                         &i2c->iiccon);
 364                                 ReadWriteByte(i2c);
 365                                 result = WaitForXfer(i2c);
 366                                         data[i] = readl(&i2c->iicds);
 367                                         i++;
 368                                 }
 369                         } else {
 370                                 result = I2C_NACK;
 371                         }
 372
 373                 } else {
 374                         writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 375                         writel(chip, &i2c->iicds);
 376                         /* send START */
 377                         writel(readl(&i2c->iicstat) | I2C_START_STOP,
 378                                &i2c->iicstat);
 379                         result = WaitForXfer(i2c);
 380
 381                         if (IsACK(i2c)) {
 382                                 i = 0;
 383                                 while ((i < data_len) && (result == I2C_OK)) {
 384                                         /* disable ACK for final READ */
 385                                         if (i == data_len - 1)
 386                                                 writel(readl(&i2c->iiccon) &
 387                                                         ~I2CCON_ACKGEN,
 388                                                         &i2c->iiccon);
 389                                         ReadWriteByte(i2c);
 390                                         result = WaitForXfer(i2c);
 391                                         data[i] = readl(&i2c->iicds);
 392                                         i++;
 393                                 }
 394                         } else {
 395                                 result = I2C_NACK;
 396                         }
 397                 }
 398
 399                 /* send STOP */
 400                 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 401                 ReadWriteByte(i2c);
 402                 break;
 403
 404         default:
 405                 debug("i2c_transfer: bad call\n");
 406                 result = I2C_NOK;
 407                 break;
 408         }
 409
 410         return result;
 411 }
 412
 413 int i2c_probe(uchar chip)
 414 {
 415         struct s3c24x0_i2c *i2c;
 416         uchar buf[1];
 417
 418         i2c = get_base_i2c();
 419         buf[0] = 0;
 420
 421         /*
 422          * What is needed is to send the chip address and verify that the
 423          * address was <ACK>ed (i.e. there was a chip at that address which
 424          * drove the data line low).
 425          */
 426         return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
 427 }
 428
 429 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 430 {
 431         struct s3c24x0_i2c *i2c;
 432         uchar xaddr[4];
 433         int ret;
 434
 435         if (alen > 4) {
 436                 debug("I2C read: addr len %d not supported\n", alen);
 437                 return 1;
 438         }
 439
 440         if (alen > 0) {
 441                 xaddr[0] = (addr >> 24) & 0xFF;
 442                 xaddr[1] = (addr >> 16) & 0xFF;
 443                 xaddr[2] = (addr >> 8) & 0xFF;
 444                 xaddr[3] = addr & 0xFF;
 445         }
 446
 447 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 448         /*
 449          * EEPROM chips that implement "address overflow" are ones
 450          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 451          * address and the extra bits end up in the "chip address"
 452          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 453          * four 256 byte chips.
 454          *
 455          * Note that we consider the length of the address field to
 456          * still be one byte because the extra address bits are
 457          * hidden in the chip address.
 458          */
 459         if (alen > 0)
 460                 chip |= ((addr >> (alen * 8)) &
 461                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 462 #endif
 463         i2c = get_base_i2c();
 464         ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
 465                         buffer, len);
 466         if (ret != 0) {
 467                 debug("I2c read: failed %d\n", ret);
 468                 return 1;
 469         }
 470         return 0;
 471 }
 472
 473 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 474 {
 475         struct s3c24x0_i2c *i2c;
 476         uchar xaddr[4];
 477
 478         if (alen > 4) {
 479                 debug("I2C write: addr len %d not supported\n", alen);
 480                 return 1;
 481         }
 482
 483         if (alen > 0) {
 484                 xaddr[0] = (addr >> 24) & 0xFF;
 485                 xaddr[1] = (addr >> 16) & 0xFF;
 486                 xaddr[2] = (addr >> 8) & 0xFF;
 487                 xaddr[3] = addr & 0xFF;
 488         }
 489 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 490         /*
 491          * EEPROM chips that implement "address overflow" are ones
 492          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 493          * address and the extra bits end up in the "chip address"
 494          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 495          * four 256 byte chips.
 496          *
 497          * Note that we consider the length of the address field to
 498          * still be one byte because the extra address bits are
 499          * hidden in the chip address.
 500          */
 501         if (alen > 0)
 502                 chip |= ((addr >> (alen * 8)) &
 503                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 504 #endif
 505         i2c = get_base_i2c();
 506         return (i2c_transfer
 507                 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
 508                  len) != 0);
 509 }
 510 #endif /* CONFIG_HARD_I2C */