3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* This code should work for both the S3C2400 and the S3C2410
25 * as they seem to have the same I2C controller inside.
26 * The different address mapping is handled by the s3c24xx.h files below.
31 #include <asm/arch/clk.h>
32 #include <asm/arch/cpu.h>
34 #include <asm/arch/s3c24x0_cpu.h>
38 #include "s3c24x0_i2c.h"
40 #ifdef CONFIG_HARD_I2C
48 #define I2C_NOK_LA 3 /* Lost arbitration */
49 #define I2C_NOK_TOUT 4 /* time out */
51 #define I2CSTAT_BSY 0x20 /* Busy bit */
52 #define I2CSTAT_NACK 0x01 /* Nack bit */
53 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
54 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
55 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
56 #define I2C_MODE_MR 0x80 /* Master Receive Mode */
57 #define I2C_START_STOP 0x20 /* START / STOP */
58 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
60 #define I2C_TIMEOUT 1 /* 1 second */
63 static unsigned int g_current_bus; /* Stores Current I2C Bus */
65 #ifndef CONFIG_EXYNOS5
66 static int GetI2CSDA(void)
68 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
71 return (readl(&gpio->gpedat) & 0x8000) >> 15;
74 return (readl(&gpio->pgdat) & 0x0020) >> 5;
79 static void SetI2CSDA(int x)
81 rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
85 static void SetI2CSCL(int x)
87 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
90 writel((readl(&gpio->gpedat) & ~0x4000) |
91 (x & 1) << 14, &gpio->gpedat);
94 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
99 static int WaitForXfer(struct s3c24x0_i2c *i2c)
103 i = I2C_TIMEOUT * 10000;
104 while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
109 return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
112 static int IsACK(struct s3c24x0_i2c *i2c)
114 return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
117 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
119 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
122 static struct s3c24x0_i2c *get_base_i2c(void)
124 #ifdef CONFIG_EXYNOS5
125 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
126 + (EXYNOS5_I2C_SPACING
130 return s3c24x0_get_base_i2c();
134 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
136 ulong freq, pres = 16, div;
137 #ifdef CONFIG_EXYNOS5
138 freq = get_i2c_clk();
142 /* calculate prescaler and divisor values */
143 if ((freq / pres / (16 + 1)) > speed)
144 /* set prescaler to 512 */
148 while ((freq / pres / (div + 1)) > speed)
151 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
152 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
154 /* init to SLAVE REVEIVE and set slaveaddr */
155 writel(0, &i2c->iicstat);
156 writel(slaveadd, &i2c->iicadd);
157 /* program Master Transmit (and implicit STOP) */
158 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
162 * MULTI BUS I2C support
165 #ifdef CONFIG_I2C_MULTI_BUS
166 int i2c_set_bus_num(unsigned int bus)
168 struct s3c24x0_i2c *i2c;
170 if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
171 debug("Bad bus: %d\n", bus);
176 i2c = get_base_i2c();
177 i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
182 unsigned int i2c_get_bus_num(void)
184 return g_current_bus;
188 void i2c_init(int speed, int slaveadd)
190 struct s3c24x0_i2c *i2c;
191 #ifndef CONFIG_EXYNOS5
192 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
196 /* By default i2c channel 0 is the current bus */
198 i2c = get_base_i2c();
200 /* wait for some time to give previous transfer a chance to finish */
201 i = I2C_TIMEOUT * 1000;
202 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
207 #ifndef CONFIG_EXYNOS5
208 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
209 #ifdef CONFIG_S3C2410
210 ulong old_gpecon = readl(&gpio->gpecon);
212 #ifdef CONFIG_S3C2400
213 ulong old_gpecon = readl(&gpio->pgcon);
215 /* bus still busy probably by (most) previously interrupted
218 #ifdef CONFIG_S3C2410
219 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
220 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
223 #ifdef CONFIG_S3C2400
224 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
225 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
229 /* toggle I2CSCL until bus idle */
233 while ((i > 0) && (GetI2CSDA() != 1)) {
243 /* restore pin functions */
244 #ifdef CONFIG_S3C2410
245 writel(old_gpecon, &gpio->gpecon);
247 #ifdef CONFIG_S3C2400
248 writel(old_gpecon, &gpio->pgcon);
251 #endif /* #ifndef CONFIG_EXYNOS5 */
252 i2c_ch_init(i2c, speed, slaveadd);
256 * cmd_type is 0 for write, 1 for read.
258 * addr_len can take any value from 0-255, it is only limited
259 * by the char, we could make it larger if needed. If it is
260 * 0 we skip the address write cycle.
262 static int i2c_transfer(struct s3c24x0_i2c *i2c,
263 unsigned char cmd_type,
265 unsigned char addr[],
266 unsigned char addr_len,
267 unsigned char data[],
268 unsigned short data_len)
272 if (data == 0 || data_len == 0) {
273 /*Don't support data transfer of no length or to address 0 */
274 debug("i2c_transfer: bad call\n");
278 /* Check I2C bus idle */
279 i = I2C_TIMEOUT * 1000;
280 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
285 if (readl(&i2c->iicstat) & I2CSTAT_BSY)
288 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
293 if (addr && addr_len) {
294 writel(chip, &i2c->iicds);
296 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
299 while ((i < addr_len) && (result == I2C_OK)) {
300 result = WaitForXfer(i2c);
301 writel(addr[i], &i2c->iicds);
306 while ((i < data_len) && (result == I2C_OK)) {
307 result = WaitForXfer(i2c);
308 writel(data[i], &i2c->iicds);
313 writel(chip, &i2c->iicds);
315 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
318 while ((i < data_len) && (result = I2C_OK)) {
319 result = WaitForXfer(i2c);
320 writel(data[i], &i2c->iicds);
326 if (result == I2C_OK)
327 result = WaitForXfer(i2c);
330 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
335 if (addr && addr_len) {
336 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
337 writel(chip, &i2c->iicds);
339 writel(readl(&i2c->iicstat) | I2C_START_STOP,
341 result = WaitForXfer(i2c);
344 while ((i < addr_len) && (result == I2C_OK)) {
345 writel(addr[i], &i2c->iicds);
347 result = WaitForXfer(i2c);
351 writel(chip, &i2c->iicds);
353 writel(I2C_MODE_MR | I2C_TXRX_ENA |
354 I2C_START_STOP, &i2c->iicstat);
356 result = WaitForXfer(i2c);
358 while ((i < data_len) && (result == I2C_OK)) {
359 /* disable ACK for final READ */
360 if (i == data_len - 1)
361 writel(readl(&i2c->iiccon)
365 result = WaitForXfer(i2c);
366 data[i] = readl(&i2c->iicds);
374 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
375 writel(chip, &i2c->iicds);
377 writel(readl(&i2c->iicstat) | I2C_START_STOP,
379 result = WaitForXfer(i2c);
383 while ((i < data_len) && (result == I2C_OK)) {
384 /* disable ACK for final READ */
385 if (i == data_len - 1)
386 writel(readl(&i2c->iiccon) &
390 result = WaitForXfer(i2c);
391 data[i] = readl(&i2c->iicds);
400 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
405 debug("i2c_transfer: bad call\n");
413 int i2c_probe(uchar chip)
415 struct s3c24x0_i2c *i2c;
418 i2c = get_base_i2c();
422 * What is needed is to send the chip address and verify that the
423 * address was <ACK>ed (i.e. there was a chip at that address which
424 * drove the data line low).
426 return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
429 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
431 struct s3c24x0_i2c *i2c;
436 debug("I2C read: addr len %d not supported\n", alen);
441 xaddr[0] = (addr >> 24) & 0xFF;
442 xaddr[1] = (addr >> 16) & 0xFF;
443 xaddr[2] = (addr >> 8) & 0xFF;
444 xaddr[3] = addr & 0xFF;
447 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
449 * EEPROM chips that implement "address overflow" are ones
450 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
451 * address and the extra bits end up in the "chip address"
452 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
453 * four 256 byte chips.
455 * Note that we consider the length of the address field to
456 * still be one byte because the extra address bits are
457 * hidden in the chip address.
460 chip |= ((addr >> (alen * 8)) &
461 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
463 i2c = get_base_i2c();
464 ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
467 debug("I2c read: failed %d\n", ret);
473 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
475 struct s3c24x0_i2c *i2c;
479 debug("I2C write: addr len %d not supported\n", alen);
484 xaddr[0] = (addr >> 24) & 0xFF;
485 xaddr[1] = (addr >> 16) & 0xFF;
486 xaddr[2] = (addr >> 8) & 0xFF;
487 xaddr[3] = addr & 0xFF;
489 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
491 * EEPROM chips that implement "address overflow" are ones
492 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
493 * address and the extra bits end up in the "chip address"
494 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
495 * four 256 byte chips.
497 * Note that we consider the length of the address field to
498 * still be one byte because the extra address bits are
499 * hidden in the chip address.
502 chip |= ((addr >> (alen * 8)) &
503 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
505 i2c = get_base_i2c();
507 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
510 #endif /* CONFIG_HARD_I2C */