3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * SPDX-License-Identifier: GPL-2.0+
8 /* This code should work for both the S3C2400 and the S3C2410
9 * as they seem to have the same I2C controller inside.
10 * The different address mapping is handled by the s3c24xx.h files below.
15 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
16 #include <asm/arch/clk.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/pinmux.h>
20 #include <asm/arch/s3c24x0_cpu.h>
24 #include "s3c24x0_i2c.h"
32 #define I2C_NOK_LA 3 /* Lost arbitration */
33 #define I2C_NOK_TOUT 4 /* time out */
35 /* HSI2C specific register description */
37 /* I2C_CTL Register bits */
38 #define HSI2C_FUNC_MODE_I2C (1u << 0)
39 #define HSI2C_MASTER (1u << 3)
40 #define HSI2C_RXCHON (1u << 6) /* Write/Send */
41 #define HSI2C_TXCHON (1u << 7) /* Read/Receive */
42 #define HSI2C_SW_RST (1u << 31)
44 /* I2C_FIFO_CTL Register bits */
45 #define HSI2C_RXFIFO_EN (1u << 0)
46 #define HSI2C_TXFIFO_EN (1u << 1)
47 #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
48 #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
50 /* I2C_TRAILING_CTL Register bits */
51 #define HSI2C_TRAILING_COUNT (0xff)
53 /* I2C_INT_EN Register bits */
54 #define HSI2C_TX_UNDERRUN_EN (1u << 2)
55 #define HSI2C_TX_OVERRUN_EN (1u << 3)
56 #define HSI2C_RX_UNDERRUN_EN (1u << 4)
57 #define HSI2C_RX_OVERRUN_EN (1u << 5)
58 #define HSI2C_INT_TRAILING_EN (1u << 6)
59 #define HSI2C_INT_I2C_EN (1u << 9)
61 #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\
62 HSI2C_TX_OVERRUN_EN |\
63 HSI2C_RX_UNDERRUN_EN |\
64 HSI2C_RX_OVERRUN_EN |\
65 HSI2C_INT_TRAILING_EN)
67 /* I2C_CONF Register bits */
68 #define HSI2C_AUTO_MODE (1u << 31)
69 #define HSI2C_10BIT_ADDR_MODE (1u << 30)
70 #define HSI2C_HS_MODE (1u << 29)
72 /* I2C_AUTO_CONF Register bits */
73 #define HSI2C_READ_WRITE (1u << 16)
74 #define HSI2C_STOP_AFTER_TRANS (1u << 17)
75 #define HSI2C_MASTER_RUN (1u << 31)
77 /* I2C_TIMEOUT Register bits */
78 #define HSI2C_TIMEOUT_EN (1u << 31)
80 /* I2C_TRANS_STATUS register bits */
81 #define HSI2C_MASTER_BUSY (1u << 17)
82 #define HSI2C_SLAVE_BUSY (1u << 16)
83 #define HSI2C_TIMEOUT_AUTO (1u << 4)
84 #define HSI2C_NO_DEV (1u << 3)
85 #define HSI2C_NO_DEV_ACK (1u << 2)
86 #define HSI2C_TRANS_ABORT (1u << 1)
87 #define HSI2C_TRANS_SUCCESS (1u << 0)
88 #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\
89 HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
91 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
94 /* I2C_FIFO_STAT Register bits */
95 #define HSI2C_RX_FIFO_EMPTY (1u << 24)
96 #define HSI2C_RX_FIFO_FULL (1u << 23)
97 #define HSI2C_TX_FIFO_EMPTY (1u << 8)
98 #define HSI2C_TX_FIFO_FULL (1u << 7)
99 #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f)
100 #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f)
102 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
104 /* S3C I2C Controller bits */
105 #define I2CSTAT_BSY 0x20 /* Busy bit */
106 #define I2CSTAT_NACK 0x01 /* Nack bit */
107 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
108 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
109 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
110 #define I2C_MODE_MR 0x80 /* Master Receive Mode */
111 #define I2C_START_STOP 0x20 /* START / STOP */
112 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
114 #define I2C_TIMEOUT_MS 1000 /* 1 second */
116 #define HSI2C_TIMEOUT_US 100000 /* 100 ms, finer granularity */
119 /* To support VCMA9 boards and other who dont define max_i2c_num */
120 #ifndef CONFIG_MAX_I2C_NUM
121 #define CONFIG_MAX_I2C_NUM 1
125 * For SPL boot some boards need i2c before SDRAM is initialised so force
126 * variables to live in SRAM
128 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
129 __attribute__((section(".data")));
132 * Get a pointer to the given bus index
134 * @bus_idx: Bus index to look up
135 * @return pointer to bus, or NULL if invalid or not available
137 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
139 if (bus_idx < ARRAY_SIZE(i2c_bus)) {
140 struct s3c24x0_i2c_bus *bus;
142 bus = &i2c_bus[bus_idx];
147 debug("Undefined bus: %d\n", bus_idx);
151 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
152 static int GetI2CSDA(void)
154 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
156 #ifdef CONFIG_S3C2410
157 return (readl(&gpio->gpedat) & 0x8000) >> 15;
159 #ifdef CONFIG_S3C2400
160 return (readl(&gpio->pgdat) & 0x0020) >> 5;
164 static void SetI2CSCL(int x)
166 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
168 #ifdef CONFIG_S3C2410
169 writel((readl(&gpio->gpedat) & ~0x4000) |
170 (x & 1) << 14, &gpio->gpedat);
172 #ifdef CONFIG_S3C2400
173 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
179 * Wait til the byte transfer is completed.
181 * @param i2c- pointer to the appropriate i2c register bank.
182 * @return I2C_OK, if transmission was ACKED
183 * I2C_NACK, if transmission was NACKED
184 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
187 static int WaitForXfer(struct s3c24x0_i2c *i2c)
189 ulong start_time = get_timer(0);
192 if (readl(&i2c->iiccon) & I2CCON_IRPND)
193 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
195 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
201 * Wait for transfer completion.
203 * This function reads the interrupt status register waiting for the INT_I2C
204 * bit to be set, which indicates copletion of a transaction.
206 * @param i2c: pointer to the appropriate register bank
208 * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
209 * the status bits do not get set in time, or an approrpiate error
210 * value in case of transfer errors.
212 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
214 int i = HSI2C_TIMEOUT_US;
217 u32 int_status = readl(&i2c->usi_int_stat);
219 if (int_status & HSI2C_INT_I2C_EN) {
220 u32 trans_status = readl(&i2c->usi_trans_status);
222 /* Deassert pending interrupt. */
223 writel(int_status, &i2c->usi_int_stat);
225 if (trans_status & HSI2C_NO_DEV_ACK) {
226 debug("%s: no ACK from device\n", __func__);
229 if (trans_status & HSI2C_NO_DEV) {
230 debug("%s: no device\n", __func__);
233 if (trans_status & HSI2C_TRANS_ABORT) {
234 debug("%s: arbitration lost\n", __func__);
237 if (trans_status & HSI2C_TIMEOUT_AUTO) {
238 debug("%s: device timed out\n", __func__);
245 debug("%s: transaction timeout!\n", __func__);
249 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
251 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
254 static struct s3c24x0_i2c *get_base_i2c(int bus)
256 #ifdef CONFIG_EXYNOS4
257 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
258 + (EXYNOS4_I2C_SPACING
261 #elif defined CONFIG_EXYNOS5
262 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
263 + (EXYNOS5_I2C_SPACING
267 return s3c24x0_get_base_i2c();
271 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
273 ulong freq, pres = 16, div;
274 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
275 freq = get_i2c_clk();
279 /* calculate prescaler and divisor values */
280 if ((freq / pres / (16 + 1)) > speed)
281 /* set prescaler to 512 */
285 while ((freq / pres / (div + 1)) > speed)
288 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
289 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
291 /* init to SLAVE REVEIVE and set slaveaddr */
292 writel(0, &i2c->iicstat);
293 writel(slaveadd, &i2c->iicadd);
294 /* program Master Transmit (and implicit STOP) */
295 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
298 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
300 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
302 unsigned int op_clk = i2c_bus->clock_frequency;
303 unsigned int i = 0, utemp0 = 0, utemp1 = 0;
304 unsigned int t_ftl_cycle;
306 #if defined CONFIG_EXYNOS5
307 clkin = get_i2c_clk();
310 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
311 * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
312 * uTemp1 = (TSCLK_L + TSCLK_H + 2)
313 * uTemp2 = TSCLK_L + TSCLK_H
315 t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
316 utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
318 /* CLK_DIV max is 256 */
319 for (i = 0; i < 256; i++) {
320 utemp1 = utemp0 / (i + 1);
321 if ((utemp1 < 512) && (utemp1 > 4)) {
322 i2c_bus->clk_cycle = utemp1 - 2;
323 i2c_bus->clk_div = i;
330 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
332 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
333 unsigned int t_sr_release;
334 unsigned int n_clkdiv;
335 unsigned int t_start_su, t_start_hd;
336 unsigned int t_stop_su;
337 unsigned int t_data_su, t_data_hd;
338 unsigned int t_scl_l, t_scl_h;
344 n_clkdiv = i2c_bus->clk_div;
345 t_scl_l = i2c_bus->clk_cycle / 2;
346 t_scl_h = i2c_bus->clk_cycle / 2;
347 t_start_su = t_scl_l;
348 t_start_hd = t_scl_l;
350 t_data_su = t_scl_l / 2;
351 t_data_hd = t_scl_l / 2;
352 t_sr_release = i2c_bus->clk_cycle;
354 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
355 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
356 i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
357 i2c_timing_sla = t_data_hd << 0;
359 writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
361 /* Clear to enable Timeout */
362 clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
365 writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
367 /* Enable completion conditions' reporting. */
368 writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
371 writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
373 /* Currently operating in Fast speed mode. */
374 writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
375 writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
376 writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
377 writel(i2c_timing_sla, &hsregs->usi_timing_sla);
380 /* SW reset for the high speed bus */
381 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
383 struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
386 /* Set and clear the bit for reset */
387 i2c_ctl = readl(&i2c->usi_ctl);
388 i2c_ctl |= HSI2C_SW_RST;
389 writel(i2c_ctl, &i2c->usi_ctl);
391 i2c_ctl = readl(&i2c->usi_ctl);
392 i2c_ctl &= ~HSI2C_SW_RST;
393 writel(i2c_ctl, &i2c->usi_ctl);
395 /* Initialize the configure registers */
396 hsi2c_ch_init(i2c_bus);
399 static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
401 struct s3c24x0_i2c *i2c;
402 struct s3c24x0_i2c_bus *bus;
404 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
405 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
407 ulong start_time = get_timer(0);
409 /* By default i2c channel 0 is the current bus */
410 i2c = get_base_i2c(adap->hwadapnr);
413 * In case the previous transfer is still going, wait to give it a
416 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
417 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
418 printf("%s: I2C bus busy for %p\n", __func__,
424 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
427 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
428 #ifdef CONFIG_S3C2410
429 ulong old_gpecon = readl(&gpio->gpecon);
431 #ifdef CONFIG_S3C2400
432 ulong old_gpecon = readl(&gpio->pgcon);
434 /* bus still busy probably by (most) previously interrupted
437 #ifdef CONFIG_S3C2410
438 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
439 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
442 #ifdef CONFIG_S3C2400
443 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
444 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
448 /* toggle I2CSCL until bus idle */
452 while ((i > 0) && (GetI2CSDA() != 1)) {
462 /* restore pin functions */
463 #ifdef CONFIG_S3C2410
464 writel(old_gpecon, &gpio->gpecon);
466 #ifdef CONFIG_S3C2400
467 writel(old_gpecon, &gpio->pgcon);
470 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
471 i2c_ch_init(i2c, speed, slaveadd);
473 bus = &i2c_bus[adap->hwadapnr];
479 * Poll the appropriate bit of the fifo status register until the interface is
480 * ready to process the next byte or timeout expires.
482 * In addition to the FIFO status register this function also polls the
483 * interrupt status register to be able to detect unexpected transaction
486 * When FIFO is ready to process the next byte, this function returns I2C_OK.
487 * If in course of polling the INT_I2C assertion is detected, the function
488 * returns I2C_NOK. If timeout happens before any of the above conditions is
489 * met - the function returns I2C_NOK_TOUT;
491 * @param i2c: pointer to the appropriate i2c register bank.
492 * @param rx_transfer: set to True if the receive transaction is in progress.
493 * @return: as described above.
495 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
497 u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
498 int i = HSI2C_TIMEOUT_US;
500 while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
501 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
503 * There is a chance that assertion of
504 * HSI2C_INT_I2C_EN and deassertion of
505 * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
506 * give FIFO status priority and check it one more
507 * time before reporting interrupt. The interrupt will
508 * be reported next time this function is called.
511 !(readl(&i2c->usi_fifo_stat) & fifo_bit))
516 debug("%s: FIFO polling timeout!\n", __func__);
525 * Preapre hsi2c transaction, either read or write.
527 * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
530 * @param i2c: pointer to the appropriate i2c register bank.
531 * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
532 * @param len: number of bytes expected to be sent or received
533 * @param rx_transfer: set to true for receive transactions
534 * @param: issue_stop: set to true if i2c stop condition should be generated
535 * after this transaction.
536 * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
539 static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
547 conf = len | HSI2C_MASTER_RUN;
550 conf |= HSI2C_STOP_AFTER_TRANS;
552 /* Clear to enable Timeout */
553 writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
555 /* Set slave address */
556 writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
559 /* i2c master, read transaction */
560 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
563 /* read up to len bytes, stop after transaction is finished */
564 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
566 /* i2c master, write transaction */
567 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
570 /* write up to len bytes, stop after transaction is finished */
571 writel(conf, &i2c->usi_auto_conf);
574 /* Reset all pending interrupt status bits we care about, if any */
575 writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
581 * Wait while i2c bus is settling down (mostly stop gets completed).
583 static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
585 int i = HSI2C_TIMEOUT_US;
587 while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
589 debug("%s: bus busy\n", __func__);
597 static int hsi2c_write(struct exynos5_hsi2c *i2c,
599 unsigned char addr[],
601 unsigned char data[],
608 /* Writes of zero length not supported in auto mode. */
609 debug("%s: zero length writes not supported\n", __func__);
613 rv = hsi2c_prepare_transaction
614 (i2c, chip, len + alen, false, issue_stop);
618 /* Move address, if any, and the data, if any, into the FIFO. */
619 for (i = 0; i < alen; i++) {
620 rv = hsi2c_poll_fifo(i2c, false);
622 debug("%s: address write failed\n", __func__);
625 writel(addr[i], &i2c->usi_txdata);
628 for (i = 0; i < len; i++) {
629 rv = hsi2c_poll_fifo(i2c, false);
631 debug("%s: data write failed\n", __func__);
634 writel(data[i], &i2c->usi_txdata);
637 rv = hsi2c_wait_for_trx(i2c);
641 int tmp_ret = hsi2c_wait_while_busy(i2c);
646 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
650 static int hsi2c_read(struct exynos5_hsi2c *i2c,
652 unsigned char addr[],
654 unsigned char data[],
658 bool drop_data = false;
661 /* Reads of zero length not supported in auto mode. */
662 debug("%s: zero length read adjusted\n", __func__);
668 /* Internal register adress needs to be written first. */
669 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
674 rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
679 for (i = 0; i < len; i++) {
680 rv = hsi2c_poll_fifo(i2c, true);
685 data[i] = readl(&i2c->usi_rxdata);
688 rv = hsi2c_wait_for_trx(i2c);
691 tmp_ret = hsi2c_wait_while_busy(i2c);
695 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
699 static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
702 struct s3c24x0_i2c_bus *i2c_bus;
704 i2c_bus = get_bus(adap->hwadapnr);
708 i2c_bus->clock_frequency = speed;
710 if (i2c_bus->is_highspeed) {
711 if (hsi2c_get_clk_details(i2c_bus))
713 hsi2c_ch_init(i2c_bus);
715 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
716 CONFIG_SYS_I2C_S3C24X0_SLAVE);
723 * cmd_type is 0 for write, 1 for read.
725 * addr_len can take any value from 0-255, it is only limited
726 * by the char, we could make it larger if needed. If it is
727 * 0 we skip the address write cycle.
729 static int i2c_transfer(struct s3c24x0_i2c *i2c,
730 unsigned char cmd_type,
732 unsigned char addr[],
733 unsigned char addr_len,
734 unsigned char data[],
735 unsigned short data_len)
738 ulong start_time = get_timer(0);
740 if (data == 0 || data_len == 0) {
741 /*Don't support data transfer of no length or to address 0 */
742 debug("i2c_transfer: bad call\n");
746 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
747 if (get_timer(start_time) > I2C_TIMEOUT_MS)
751 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
753 /* Get the slave chip address going */
754 writel(chip, &i2c->iicds);
755 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
756 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
759 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
762 /* Wait for chip address to transmit. */
763 result = WaitForXfer(i2c);
764 if (result != I2C_OK)
767 /* If register address needs to be transmitted - do it now. */
768 if (addr && addr_len) {
769 while ((i < addr_len) && (result == I2C_OK)) {
770 writel(addr[i++], &i2c->iicds);
772 result = WaitForXfer(i2c);
775 if (result != I2C_OK)
781 while ((i < data_len) && (result == I2C_OK)) {
782 writel(data[i++], &i2c->iicds);
784 result = WaitForXfer(i2c);
789 if (addr && addr_len) {
791 * Register address has been sent, now send slave chip
792 * address again to start the actual read transaction.
794 writel(chip, &i2c->iicds);
796 /* Generate a re-START. */
797 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
800 result = WaitForXfer(i2c);
802 if (result != I2C_OK)
806 while ((i < data_len) && (result == I2C_OK)) {
807 /* disable ACK for final READ */
808 if (i == data_len - 1)
809 writel(readl(&i2c->iiccon)
813 result = WaitForXfer(i2c);
814 data[i++] = readl(&i2c->iicds);
816 if (result == I2C_NACK)
817 result = I2C_OK; /* Normal terminated read. */
821 debug("i2c_transfer: bad call\n");
828 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
834 static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
836 struct s3c24x0_i2c_bus *i2c_bus;
840 i2c_bus = get_bus(adap->hwadapnr);
846 * What is needed is to send the chip address and verify that the
847 * address was <ACK>ed (i.e. there was a chip at that address which
848 * drove the data line low).
850 if (i2c_bus->is_highspeed) {
851 ret = hsi2c_read(i2c_bus->hsregs,
854 ret = i2c_transfer(i2c_bus->regs,
855 I2C_READ, chip << 1, 0, 0, buf, 1);
858 return ret != I2C_OK;
861 static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
862 int alen, uchar *buffer, int len)
864 struct s3c24x0_i2c_bus *i2c_bus;
869 debug("I2C read: addr len %d not supported\n", alen);
874 xaddr[0] = (addr >> 24) & 0xFF;
875 xaddr[1] = (addr >> 16) & 0xFF;
876 xaddr[2] = (addr >> 8) & 0xFF;
877 xaddr[3] = addr & 0xFF;
880 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
882 * EEPROM chips that implement "address overflow" are ones
883 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
884 * address and the extra bits end up in the "chip address"
885 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
886 * four 256 byte chips.
888 * Note that we consider the length of the address field to
889 * still be one byte because the extra address bits are
890 * hidden in the chip address.
893 chip |= ((addr >> (alen * 8)) &
894 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
896 i2c_bus = get_bus(adap->hwadapnr);
900 if (i2c_bus->is_highspeed)
901 ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen],
904 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1,
905 &xaddr[4 - alen], alen, buffer, len);
908 if (i2c_bus->is_highspeed)
909 exynos5_i2c_reset(i2c_bus);
910 debug("I2c read failed %d\n", ret);
916 static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
917 int alen, uchar *buffer, int len)
919 struct s3c24x0_i2c_bus *i2c_bus;
924 debug("I2C write: addr len %d not supported\n", alen);
929 xaddr[0] = (addr >> 24) & 0xFF;
930 xaddr[1] = (addr >> 16) & 0xFF;
931 xaddr[2] = (addr >> 8) & 0xFF;
932 xaddr[3] = addr & 0xFF;
934 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
936 * EEPROM chips that implement "address overflow" are ones
937 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
938 * address and the extra bits end up in the "chip address"
939 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
940 * four 256 byte chips.
942 * Note that we consider the length of the address field to
943 * still be one byte because the extra address bits are
944 * hidden in the chip address.
947 chip |= ((addr >> (alen * 8)) &
948 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
950 i2c_bus = get_bus(adap->hwadapnr);
954 if (i2c_bus->is_highspeed)
955 ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen],
956 alen, buffer, len, true);
958 ret = i2c_transfer(i2c_bus->regs, I2C_WRITE, chip << 1,
959 &xaddr[4 - alen], alen, buffer, len);
962 if (i2c_bus->is_highspeed)
963 exynos5_i2c_reset(i2c_bus);
970 #ifdef CONFIG_OF_CONTROL
971 static void process_nodes(const void *blob, int node_list[], int count,
974 struct s3c24x0_i2c_bus *bus;
977 for (i = 0; i < count; i++) {
978 int node = node_list[i];
985 bus->is_highspeed = is_highspeed;
988 bus->hsregs = (struct exynos5_hsi2c *)
989 fdtdec_get_addr(blob, node, "reg");
991 bus->regs = (struct s3c24x0_i2c *)
992 fdtdec_get_addr(blob, node, "reg");
994 bus->id = pinmux_decode_periph_id(blob, node);
995 bus->clock_frequency = fdtdec_get_int(blob, node,
997 CONFIG_SYS_I2C_S3C24X0_SPEED);
1000 exynos_pinmux_config(bus->id, 0);
1002 /* Mark position as used */
1007 void board_i2c_init(const void *blob)
1009 int node_list[CONFIG_MAX_I2C_NUM];
1012 /* First get the normal i2c ports */
1013 count = fdtdec_find_aliases_for_id(blob, "i2c",
1014 COMPAT_SAMSUNG_S3C2440_I2C, node_list,
1015 CONFIG_MAX_I2C_NUM);
1016 process_nodes(blob, node_list, count, 0);
1018 /* Now look for high speed i2c ports */
1019 count = fdtdec_find_aliases_for_id(blob, "i2c",
1020 COMPAT_SAMSUNG_EXYNOS5_I2C, node_list,
1021 CONFIG_MAX_I2C_NUM);
1022 process_nodes(blob, node_list, count, 1);
1026 int i2c_get_bus_num_fdt(int node)
1030 for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) {
1031 if (node == i2c_bus[i].node)
1035 debug("%s: Can't find any matched I2C bus\n", __func__);
1039 int i2c_reset_port_fdt(const void *blob, int node)
1041 struct s3c24x0_i2c_bus *i2c_bus;
1044 bus = i2c_get_bus_num_fdt(node);
1046 debug("could not get bus for node %d\n", node);
1050 i2c_bus = get_bus(bus);
1052 debug("get_bus() failed for node node %d\n", node);
1056 if (i2c_bus->is_highspeed) {
1057 if (hsi2c_get_clk_details(i2c_bus))
1059 hsi2c_ch_init(i2c_bus);
1061 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
1062 CONFIG_SYS_I2C_S3C24X0_SLAVE);
1070 * Register s3c24x0 i2c adapters
1072 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1073 s3c24x0_i2c_read, s3c24x0_i2c_write,
1074 s3c24x0_i2c_set_bus_speed,
1075 CONFIG_SYS_I2C_S3C24X0_SPEED,
1076 CONFIG_SYS_I2C_S3C24X0_SLAVE,
1078 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_1, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1079 s3c24x0_i2c_read, s3c24x0_i2c_write,
1080 s3c24x0_i2c_set_bus_speed,
1081 CONFIG_SYS_I2C_S3C24X0_SPEED,
1082 CONFIG_SYS_I2C_S3C24X0_SLAVE,
1084 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_2, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1085 s3c24x0_i2c_read, s3c24x0_i2c_write,
1086 s3c24x0_i2c_set_bus_speed,
1087 CONFIG_SYS_I2C_S3C24X0_SPEED,
1088 CONFIG_SYS_I2C_S3C24X0_SLAVE,
1090 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_3, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1091 s3c24x0_i2c_read, s3c24x0_i2c_write,
1092 s3c24x0_i2c_set_bus_speed,
1093 CONFIG_SYS_I2C_S3C24X0_SPEED,
1094 CONFIG_SYS_I2C_S3C24X0_SLAVE,
1096 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_4, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1097 s3c24x0_i2c_read, s3c24x0_i2c_write,
1098 s3c24x0_i2c_set_bus_speed,
1099 CONFIG_SYS_I2C_S3C24X0_SPEED,
1100 CONFIG_SYS_I2C_S3C24X0_SLAVE,
1102 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_5, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1103 s3c24x0_i2c_read, s3c24x0_i2c_write,
1104 s3c24x0_i2c_set_bus_speed,
1105 CONFIG_SYS_I2C_S3C24X0_SPEED,
1106 CONFIG_SYS_I2C_S3C24X0_SLAVE,
1108 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_6, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1109 s3c24x0_i2c_read, s3c24x0_i2c_write,
1110 s3c24x0_i2c_set_bus_speed,
1111 CONFIG_SYS_I2C_S3C24X0_SPEED,
1112 CONFIG_SYS_I2C_S3C24X0_SLAVE,
1114 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_7, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1115 s3c24x0_i2c_read, s3c24x0_i2c_write,
1116 s3c24x0_i2c_set_bus_speed,
1117 CONFIG_SYS_I2C_S3C24X0_SPEED,
1118 CONFIG_SYS_I2C_S3C24X0_SLAVE,