1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Google, Inc
5 * (C) Copyright 2008-2014 Rockchip Electronics
6 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/i2c.h>
18 #include <asm/arch-rockchip/periph.h>
19 #include <dm/pinctrl.h>
20 #include <linux/delay.h>
21 #include <linux/sizes.h>
24 #define I2C_TIMEOUT_MS 100
25 #define I2C_RETRY_COUNT 3
27 /* rk i2c fifo max transfer bytes */
28 #define RK_I2C_FIFO_SIZE 32
32 struct i2c_regs *regs;
42 * @controller_type: i2c controller type
44 struct rk_i2c_soc_data {
48 static inline void rk_i2c_get_div(int div, int *divh, int *divl)
54 *divh = DIV_ROUND_UP(div, 2);
58 * SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
59 * SCL = PCLK / SCLK Divisor
62 static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate)
67 /* First get i2c rate from pclk */
68 i2c_rate = clk_get_rate(&i2c->clk);
70 div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
74 rk_i2c_get_div(div, &divh, &divl);
75 writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv);
77 debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate,
79 debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl);
80 debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv));
83 static void rk_i2c_show_regs(struct i2c_regs *regs)
88 debug("i2c_con: 0x%08x\n", readl(®s->con));
89 debug("i2c_clkdiv: 0x%08x\n", readl(®s->clkdiv));
90 debug("i2c_mrxaddr: 0x%08x\n", readl(®s->mrxaddr));
91 debug("i2c_mrxraddR: 0x%08x\n", readl(®s->mrxraddr));
92 debug("i2c_mtxcnt: 0x%08x\n", readl(®s->mtxcnt));
93 debug("i2c_mrxcnt: 0x%08x\n", readl(®s->mrxcnt));
94 debug("i2c_ien: 0x%08x\n", readl(®s->ien));
95 debug("i2c_ipd: 0x%08x\n", readl(®s->ipd));
96 debug("i2c_fcnt: 0x%08x\n", readl(®s->fcnt));
97 for (i = 0; i < 8; i++)
98 debug("i2c_txdata%d: 0x%08x\n", i, readl(®s->txdata[i]));
99 for (i = 0; i < 8; i++)
100 debug("i2c_rxdata%d: 0x%08x\n", i, readl(®s->rxdata[i]));
104 static int rk_i2c_send_start_bit(struct rk_i2c *i2c)
106 struct i2c_regs *regs = i2c->regs;
109 debug("I2c Send Start bit.\n");
110 writel(I2C_IPD_ALL_CLEAN, ®s->ipd);
112 writel(I2C_CON_EN | I2C_CON_START, ®s->con);
113 writel(I2C_STARTIEN, ®s->ien);
115 start = get_timer(0);
117 if (readl(®s->ipd) & I2C_STARTIPD) {
118 writel(I2C_STARTIPD, ®s->ipd);
121 if (get_timer(start) > I2C_TIMEOUT_MS) {
122 debug("I2C Send Start Bit Timeout\n");
123 rk_i2c_show_regs(regs);
132 static int rk_i2c_send_stop_bit(struct rk_i2c *i2c)
134 struct i2c_regs *regs = i2c->regs;
137 debug("I2c Send Stop bit.\n");
138 writel(I2C_IPD_ALL_CLEAN, ®s->ipd);
140 writel(I2C_CON_EN | I2C_CON_STOP, ®s->con);
141 writel(I2C_CON_STOP, ®s->ien);
143 start = get_timer(0);
145 if (readl(®s->ipd) & I2C_STOPIPD) {
146 writel(I2C_STOPIPD, ®s->ipd);
149 if (get_timer(start) > I2C_TIMEOUT_MS) {
150 debug("I2C Send Start Bit Timeout\n");
151 rk_i2c_show_regs(regs);
160 static inline void rk_i2c_disable(struct rk_i2c *i2c)
162 writel(0, &i2c->regs->con);
165 static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
166 uchar *buf, uint b_len)
168 struct i2c_regs *regs = i2c->regs;
170 uint bytes_remain_len = b_len;
171 uint bytes_xferred = 0;
172 uint words_xferred = 0;
178 bool snd_chunk = false;
180 debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
181 chip, reg, r_len, b_len);
183 err = rk_i2c_send_start_bit(i2c);
187 writel(I2C_MRXADDR_SET(1, chip << 1 | 1), ®s->mrxaddr);
189 writel(0, ®s->mrxraddr);
190 } else if (r_len < 4) {
191 writel(I2C_MRXRADDR_SET(r_len, reg), ®s->mrxraddr);
193 debug("I2C Read: addr len %d not supported\n", r_len);
197 while (bytes_remain_len) {
198 if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
203 * The hw can read up to 32 bytes at a time. If we need
204 * more than one chunk, send an ACK after the last byte.
206 con = I2C_CON_EN | I2C_CON_LASTACK;
207 bytes_xferred = bytes_remain_len;
209 words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
212 * make sure we are in plain RX mode if we read a second chunk
215 con |= I2C_CON_MOD(I2C_MODE_RX);
217 con |= I2C_CON_MOD(I2C_MODE_TRX);
219 writel(con, ®s->con);
220 writel(bytes_xferred, ®s->mrxcnt);
221 writel(I2C_MBRFIEN | I2C_NAKRCVIEN, ®s->ien);
223 start = get_timer(0);
225 if (readl(®s->ipd) & I2C_NAKRCVIPD) {
226 writel(I2C_NAKRCVIPD, ®s->ipd);
229 if (readl(®s->ipd) & I2C_MBRFIPD) {
230 writel(I2C_MBRFIPD, ®s->ipd);
233 if (get_timer(start) > I2C_TIMEOUT_MS) {
234 debug("I2C Read Data Timeout\n");
236 rk_i2c_show_regs(regs);
242 for (i = 0; i < words_xferred; i++) {
243 rxdata = readl(®s->rxdata[i]);
244 debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata);
245 for (j = 0; j < 4; j++) {
246 if ((i * 4 + j) == bytes_xferred)
248 *pbuf++ = (rxdata >> (j * 8)) & 0xff;
252 bytes_remain_len -= bytes_xferred;
254 debug("I2C Read bytes_remain_len %d\n", bytes_remain_len);
263 static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
264 uchar *buf, uint b_len)
266 struct i2c_regs *regs = i2c->regs;
269 uint bytes_remain_len = b_len + r_len + 1;
270 uint bytes_xferred = 0;
271 uint words_xferred = 0;
276 debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
277 chip, reg, r_len, b_len);
278 err = rk_i2c_send_start_bit(i2c);
282 while (bytes_remain_len) {
283 if (bytes_remain_len > RK_I2C_FIFO_SIZE)
284 bytes_xferred = RK_I2C_FIFO_SIZE;
286 bytes_xferred = bytes_remain_len;
287 words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
289 for (i = 0; i < words_xferred; i++) {
291 for (j = 0; j < 4; j++) {
292 if ((i * 4 + j) == bytes_xferred)
295 if (i == 0 && j == 0 && pbuf == buf) {
296 txdata |= (chip << 1);
297 } else if (i == 0 && j <= r_len && pbuf == buf) {
299 (0xff << ((j - 1) * 8))) << 8;
301 txdata |= (*pbuf++)<<(j * 8);
304 writel(txdata, ®s->txdata[i]);
305 debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata);
308 writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX), ®s->con);
309 writel(bytes_xferred, ®s->mtxcnt);
310 writel(I2C_MBTFIEN | I2C_NAKRCVIEN, ®s->ien);
312 start = get_timer(0);
314 if (readl(®s->ipd) & I2C_NAKRCVIPD) {
315 writel(I2C_NAKRCVIPD, ®s->ipd);
318 if (readl(®s->ipd) & I2C_MBTFIPD) {
319 writel(I2C_MBTFIPD, ®s->ipd);
322 if (get_timer(start) > I2C_TIMEOUT_MS) {
323 debug("I2C Write Data Timeout\n");
325 rk_i2c_show_regs(regs);
331 bytes_remain_len -= bytes_xferred;
332 debug("I2C Write bytes_remain_len %d\n", bytes_remain_len);
341 static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
344 struct rk_i2c *i2c = dev_get_priv(bus);
347 debug("i2c_xfer: %d messages\n", nmsgs);
348 for (; nmsgs > 0; nmsgs--, msg++) {
349 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
350 if (msg->flags & I2C_M_RD) {
351 ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf,
354 ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf,
358 debug("i2c_write: error sending\n");
363 rk_i2c_send_stop_bit(i2c);
369 int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
371 struct rk_i2c *i2c = dev_get_priv(bus);
373 rk_i2c_set_clk(i2c, speed);
378 static int rockchip_i2c_of_to_plat(struct udevice *bus)
380 struct rk_i2c *priv = dev_get_priv(bus);
383 ret = clk_get_by_index(bus, 0, &priv->clk);
385 debug("%s: Could not get clock for %s: %d\n", __func__,
393 static int rockchip_i2c_probe(struct udevice *bus)
395 struct rk_i2c *priv = dev_get_priv(bus);
396 struct rk_i2c_soc_data *soc_data;
397 struct udevice *pinctrl;
401 priv->regs = dev_read_addr_ptr(bus);
403 soc_data = (struct rk_i2c_soc_data*)dev_get_driver_data(bus);
405 if (soc_data->controller_type == RK_I2C_LEGACY) {
406 ret = dev_read_alias_seq(bus, &bus_nr);
408 debug("%s: Could not get alias for %s: %d\n",
409 __func__, bus->name, ret);
413 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
415 debug("%s: Cannot find pinctrl device\n", __func__);
419 /* pinctrl will switch I2C to new type */
420 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_I2C0 + bus_nr);
422 debug("%s: Failed to switch I2C to new type %s: %d\n",
423 __func__, bus->name, ret);
431 static const struct dm_i2c_ops rockchip_i2c_ops = {
432 .xfer = rockchip_i2c_xfer,
433 .set_bus_speed = rockchip_i2c_set_bus_speed,
436 static const struct rk_i2c_soc_data rk3066_soc_data = {
437 .controller_type = RK_I2C_LEGACY,
440 static const struct rk_i2c_soc_data rk3188_soc_data = {
441 .controller_type = RK_I2C_LEGACY,
444 static const struct rk_i2c_soc_data rk3228_soc_data = {
445 .controller_type = RK_I2C_NEW,
448 static const struct rk_i2c_soc_data rk3288_soc_data = {
449 .controller_type = RK_I2C_NEW,
452 static const struct rk_i2c_soc_data rk3328_soc_data = {
453 .controller_type = RK_I2C_NEW,
456 static const struct rk_i2c_soc_data rk3399_soc_data = {
457 .controller_type = RK_I2C_NEW,
460 static const struct udevice_id rockchip_i2c_ids[] = {
462 .compatible = "rockchip,rk3066-i2c",
463 .data = (ulong)&rk3066_soc_data,
466 .compatible = "rockchip,rk3188-i2c",
467 .data = (ulong)&rk3188_soc_data,
470 .compatible = "rockchip,rk3228-i2c",
471 .data = (ulong)&rk3228_soc_data,
474 .compatible = "rockchip,rk3288-i2c",
475 .data = (ulong)&rk3288_soc_data,
478 .compatible = "rockchip,rk3328-i2c",
479 .data = (ulong)&rk3328_soc_data,
482 .compatible = "rockchip,rk3399-i2c",
483 .data = (ulong)&rk3399_soc_data,
488 U_BOOT_DRIVER(rockchip_rk3066_i2c) = {
489 .name = "rockchip_rk3066_i2c",
491 .of_match = rockchip_i2c_ids,
492 .of_to_plat = rockchip_i2c_of_to_plat,
493 .probe = rockchip_i2c_probe,
494 .priv_auto = sizeof(struct rk_i2c),
495 .ops = &rockchip_i2c_ops,
498 DM_DRIVER_ALIAS(rockchip_rk3066_i2c, rockchip_rk3288_i2c)