drivers/i2c/rcar_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/i2c/rcar_i2c.c
   4  *
   5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Clock configuration based on Linux i2c-rcar.c:
   8  * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
   9  * Copyright (C) 2011-2015 Renesas Electronics Corporation
  10  * Copyright (C) 2012-14 Renesas Solutions Corp.
  11  *   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  12  */
  13
  14 #include <common.h>
  15 #include <clk.h>
  16 #include <dm.h>
  17 #include <i2c.h>
  18 #include <asm/io.h>
  19 #include <wait_bit.h>
  20 #include <dm/device_compat.h>
  21 #include <linux/bitops.h>
  22 #include <linux/delay.h>
  23
  24 #define RCAR_I2C_ICSCR                  0x00 /* slave ctrl */
  25 #define RCAR_I2C_ICMCR                  0x04 /* master ctrl */
  26 #define RCAR_I2C_ICMCR_MDBS             BIT(7) /* non-fifo mode switch */
  27 #define RCAR_I2C_ICMCR_FSCL             BIT(6) /* override SCL pin */
  28 #define RCAR_I2C_ICMCR_FSDA             BIT(5) /* override SDA pin */
  29 #define RCAR_I2C_ICMCR_OBPC             BIT(4) /* override pins */
  30 #define RCAR_I2C_ICMCR_MIE              BIT(3) /* master if enable */
  31 #define RCAR_I2C_ICMCR_TSBE             BIT(2)
  32 #define RCAR_I2C_ICMCR_FSB              BIT(1) /* force stop bit */
  33 #define RCAR_I2C_ICMCR_ESG              BIT(0) /* enable start bit gen */
  34 #define RCAR_I2C_ICSSR                  0x08 /* slave status */
  35 #define RCAR_I2C_ICMSR                  0x0c /* master status */
  36 #define RCAR_I2C_ICMSR_MASK             0x7f
  37 #define RCAR_I2C_ICMSR_MNR              BIT(6) /* Nack */
  38 #define RCAR_I2C_ICMSR_MAL              BIT(5) /* Arbitration lost */
  39 #define RCAR_I2C_ICMSR_MST              BIT(4) /* Stop */
  40 #define RCAR_I2C_ICMSR_MDE              BIT(3)
  41 #define RCAR_I2C_ICMSR_MDT              BIT(2)
  42 #define RCAR_I2C_ICMSR_MDR              BIT(1)
  43 #define RCAR_I2C_ICMSR_MAT              BIT(0)
  44 #define RCAR_I2C_ICSIER                 0x10 /* slave irq enable */
  45 #define RCAR_I2C_ICMIER                 0x14 /* master irq enable */
  46 #define RCAR_I2C_ICCCR                  0x18 /* clock dividers */
  47 #define RCAR_I2C_ICCCR_SCGD_OFF         3
  48 #define RCAR_I2C_ICSAR                  0x1c /* slave address */
  49 #define RCAR_I2C_ICMAR                  0x20 /* master address */
  50 #define RCAR_I2C_ICRXD_ICTXD            0x24 /* data port */
  51 /*
  52  * First Bit Setup Cycle (Gen3).
  53  * Defines 1st bit delay between SDA and SCL.
  54  */
  55 #define RCAR_I2C_ICFBSCR                0x38
  56 #define RCAR_I2C_ICFBSCR_TCYC17         0x0f /* 17*Tcyc */
  57
  58
  59 enum rcar_i2c_type {
  60         RCAR_I2C_TYPE_GEN2,
  61         RCAR_I2C_TYPE_GEN3,
  62 };
  63
  64 struct rcar_i2c_priv {
  65         void __iomem            *base;
  66         struct clk              clk;
  67         u32                     fall_ns;
  68         u32                     rise_ns;
  69         u32                     intdelay;
  70         u32                     icccr;
  71         enum rcar_i2c_type      type;
  72 };
  73
  74 static int rcar_i2c_finish(struct udevice *dev)
  75 {
  76         struct rcar_i2c_priv *priv = dev_get_priv(dev);
  77         int ret;
  78
  79         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
  80                                 true, 10, true);
  81
  82         writel(0, priv->base + RCAR_I2C_ICSSR);
  83         writel(0, priv->base + RCAR_I2C_ICMSR);
  84         writel(0, priv->base + RCAR_I2C_ICMCR);
  85
  86         return ret;
  87 }
  88
  89 static int rcar_i2c_recover(struct udevice *dev)
  90 {
  91         struct rcar_i2c_priv *priv = dev_get_priv(dev);
  92         u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
  93         u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
  94         int i;
  95         u32 mstat;
  96
  97         /* Send 9 SCL pulses */
  98         for (i = 0; i < 9; i++) {
  99                 writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 100                 udelay(5);
 101                 writel(mcra, priv->base + RCAR_I2C_ICMCR);
 102                 udelay(5);
 103         }
 104
 105         /* Send stop condition */
 106         udelay(5);
 107         writel(mcra, priv->base + RCAR_I2C_ICMCR);
 108         udelay(5);
 109         writel(mcr, priv->base + RCAR_I2C_ICMCR);
 110         udelay(5);
 111         writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 112         udelay(5);
 113         writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 114         udelay(5);
 115
 116         mstat = readl(priv->base + RCAR_I2C_ICMSR);
 117         return mstat & RCAR_I2C_ICMCR_FSDA ? -EBUSY : 0;
 118 }
 119
 120 static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
 121 {
 122         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 123         u32 mask = RCAR_I2C_ICMSR_MAT |
 124                    (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
 125         int ret;
 126
 127         writel(0, priv->base + RCAR_I2C_ICMIER);
 128         writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
 129         writel(0, priv->base + RCAR_I2C_ICMSR);
 130         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
 131
 132         /* Wait for the bus */
 133         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
 134                                 RCAR_I2C_ICMCR_FSDA, false, 2, true);
 135         if (ret) {
 136                 if (rcar_i2c_recover(dev)) {
 137                         dev_err(dev, "Bus busy, aborting\n");
 138                         return ret;
 139                 }
 140         }
 141
 142         writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
 143         /* Reset */
 144         writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
 145                priv->base + RCAR_I2C_ICMCR);
 146         /* Clear Status */
 147         writel(0, priv->base + RCAR_I2C_ICMSR);
 148
 149         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
 150                                 true, 100, true);
 151         if (ret)
 152                 return ret;
 153
 154         /* Check NAK */
 155         if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
 156                 return -EREMOTEIO;
 157
 158         return 0;
 159 }
 160
 161 static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
 162 {
 163         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 164         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
 165         int i, ret = -EREMOTEIO;
 166
 167         for (i = 0; i < msg->len; i++) {
 168                 if (msg->len - 1 == i)
 169                         icmcr |= RCAR_I2C_ICMCR_FSB;
 170
 171                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 172                 writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
 173
 174                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
 175                                         RCAR_I2C_ICMSR_MDR, true, 100, true);
 176                 if (ret)
 177                         return ret;
 178
 179                 msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
 180         }
 181
 182         writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
 183
 184         return rcar_i2c_finish(dev);
 185 }
 186
 187 static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
 188 {
 189         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 190         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
 191         int i, ret = -EREMOTEIO;
 192
 193         for (i = 0; i < msg->len; i++) {
 194                 writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
 195                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 196                 writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
 197
 198                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
 199                                         RCAR_I2C_ICMSR_MDE, true, 100, true);
 200                 if (ret)
 201                         return ret;
 202         }
 203
 204         writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
 205         icmcr |= RCAR_I2C_ICMCR_FSB;
 206         writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 207
 208         return rcar_i2c_finish(dev);
 209 }
 210
 211 static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
 212 {
 213         int ret;
 214
 215         for (; nmsgs > 0; nmsgs--, msg++) {
 216                 ret = rcar_i2c_set_addr(dev, msg->addr, !!(msg->flags & I2C_M_RD));
 217                 if (ret)
 218                         return ret;
 219
 220                 if (msg->flags & I2C_M_RD)
 221                         ret = rcar_i2c_read_common(dev, msg);
 222                 else
 223                         ret = rcar_i2c_write_common(dev, msg);
 224
 225                 if (ret)
 226                         return ret;
 227         }
 228
 229         return 0;
 230 }
 231
 232 static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
 233 {
 234         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 235         int ret;
 236
 237         /* Ignore address 0, slave address */
 238         if (addr == 0)
 239                 return -EINVAL;
 240
 241         ret = rcar_i2c_set_addr(dev, addr, 1);
 242         writel(0, priv->base + RCAR_I2C_ICMSR);
 243         return ret;
 244 }
 245
 246 static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
 247 {
 248         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 249         u32 scgd, cdf, round, ick, sum, scl;
 250         unsigned long rate;
 251
 252         /*
 253          * calculate SCL clock
 254          * see
 255          *      ICCCR
 256          *
 257          * ick  = clkp / (1 + CDF)
 258          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 259          *
 260          * ick  : I2C internal clock < 20 MHz
 261          * ticf : I2C SCL falling time
 262          * tr   : I2C SCL rising  time
 263          * intd : LSI internal delay
 264          * clkp : peripheral_clk
 265          * F[]  : integer up-valuation
 266          */
 267         rate = clk_get_rate(&priv->clk);
 268         cdf = rate / 20000000;
 269         if (cdf >= 8) {
 270                 dev_err(dev, "Input clock %lu too high\n", rate);
 271                 return -EIO;
 272         }
 273         ick = rate / (cdf + 1);
 274
 275         /*
 276          * it is impossible to calculate large scale
 277          * number on u32. separate it
 278          *
 279          * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
 280          *  = F[sum * ick / 1000000000]
 281          *  = F[(ick / 1000000) * sum / 1000]
 282          */
 283         sum = priv->fall_ns + priv->rise_ns + priv->intdelay;
 284         round = (ick + 500000) / 1000000 * sum;
 285         round = (round + 500) / 1000;
 286
 287         /*
 288          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 289          *
 290          * Calculation result (= SCL) should be less than
 291          * bus_speed for hardware safety
 292          *
 293          * We could use something along the lines of
 294          *      div = ick / (bus_speed + 1) + 1;
 295          *      scgd = (div - 20 - round + 7) / 8;
 296          *      scl = ick / (20 + (scgd * 8) + round);
 297          * (not fully verified) but that would get pretty involved
 298          */
 299         for (scgd = 0; scgd < 0x40; scgd++) {
 300                 scl = ick / (20 + (scgd * 8) + round);
 301                 if (scl <= bus_freq_hz)
 302                         goto scgd_find;
 303         }
 304         dev_err(dev, "it is impossible to calculate best SCL\n");
 305         return -EIO;
 306
 307 scgd_find:
 308         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
 309                 scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
 310
 311         priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
 312         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
 313
 314         if (priv->type == RCAR_I2C_TYPE_GEN3) {
 315                 /* Set SCL/SDA delay */
 316                 writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int rcar_i2c_probe(struct udevice *dev)
 323 {
 324         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 325         int ret;
 326
 327         priv->base = dev_read_addr_ptr(dev);
 328         priv->rise_ns = dev_read_u32_default(dev,
 329                                              "i2c-scl-rising-time-ns", 200);
 330         priv->fall_ns = dev_read_u32_default(dev,
 331                                              "i2c-scl-falling-time-ns", 35);
 332         priv->intdelay = dev_read_u32_default(dev,
 333                                               "i2c-scl-internal-delay-ns", 5);
 334         priv->type = dev_get_driver_data(dev);
 335
 336         ret = clk_get_by_index(dev, 0, &priv->clk);
 337         if (ret)
 338                 return ret;
 339
 340         ret = clk_enable(&priv->clk);
 341         if (ret)
 342                 return ret;
 343
 344         /* reset slave mode */
 345         writel(0, priv->base + RCAR_I2C_ICSIER);
 346         writel(0, priv->base + RCAR_I2C_ICSAR);
 347         writel(0, priv->base + RCAR_I2C_ICSCR);
 348         writel(0, priv->base + RCAR_I2C_ICSSR);
 349
 350         /* reset master mode */
 351         writel(0, priv->base + RCAR_I2C_ICMIER);
 352         writel(0, priv->base + RCAR_I2C_ICMCR);
 353         writel(0, priv->base + RCAR_I2C_ICMSR);
 354         writel(0, priv->base + RCAR_I2C_ICMAR);
 355
 356         ret = rcar_i2c_set_speed(dev, I2C_SPEED_STANDARD_RATE);
 357         if (ret)
 358                 clk_disable(&priv->clk);
 359
 360         return ret;
 361 }
 362
 363 static const struct dm_i2c_ops rcar_i2c_ops = {
 364         .xfer           = rcar_i2c_xfer,
 365         .probe_chip     = rcar_i2c_probe_chip,
 366         .set_bus_speed  = rcar_i2c_set_speed,
 367 };
 368
 369 static const struct udevice_id rcar_i2c_ids[] = {
 370         { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
 371         { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
 372         { }
 373 };
 374
 375 U_BOOT_DRIVER(i2c_rcar) = {
 376         .name           = "i2c_rcar",
 377         .id             = UCLASS_I2C,
 378         .of_match       = rcar_i2c_ids,
 379         .probe          = rcar_i2c_probe,
 380         .priv_auto      = sizeof(struct rcar_i2c_priv),
 381         .ops            = &rcar_i2c_ops,
 382 };