drivers/i2c/rcar_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/i2c/rcar_i2c.c
   4  *
   5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Clock configuration based on Linux i2c-rcar.c:
   8  * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
   9  * Copyright (C) 2011-2015 Renesas Electronics Corporation
  10  * Copyright (C) 2012-14 Renesas Solutions Corp.
  11  *   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  12  */
  13
  14 #include <common.h>
  15 #include <clk.h>
  16 #include <dm.h>
  17 #include <i2c.h>
  18 #include <asm/io.h>
  19 #include <wait_bit.h>
  20
  21 #define RCAR_I2C_ICSCR                  0x00
  22 #define RCAR_I2C_ICMCR                  0x04
  23 #define RCAR_I2C_ICMCR_MDBS             BIT(7)
  24 #define RCAR_I2C_ICMCR_FSCL             BIT(6)
  25 #define RCAR_I2C_ICMCR_FSDA             BIT(5)
  26 #define RCAR_I2C_ICMCR_OBPC             BIT(4)
  27 #define RCAR_I2C_ICMCR_MIE              BIT(3)
  28 #define RCAR_I2C_ICMCR_TSBE             BIT(2)
  29 #define RCAR_I2C_ICMCR_FSB              BIT(1)
  30 #define RCAR_I2C_ICMCR_ESG              BIT(0)
  31 #define RCAR_I2C_ICSSR                  0x08
  32 #define RCAR_I2C_ICMSR                  0x0c
  33 #define RCAR_I2C_ICMSR_MASK             0x7f
  34 #define RCAR_I2C_ICMSR_MNR              BIT(6)
  35 #define RCAR_I2C_ICMSR_MAL              BIT(5)
  36 #define RCAR_I2C_ICMSR_MST              BIT(4)
  37 #define RCAR_I2C_ICMSR_MDE              BIT(3)
  38 #define RCAR_I2C_ICMSR_MDT              BIT(2)
  39 #define RCAR_I2C_ICMSR_MDR              BIT(1)
  40 #define RCAR_I2C_ICMSR_MAT              BIT(0)
  41 #define RCAR_I2C_ICSIER                 0x10
  42 #define RCAR_I2C_ICMIER                 0x14
  43 #define RCAR_I2C_ICCCR                  0x18
  44 #define RCAR_I2C_ICCCR_SCGD_OFF         3
  45 #define RCAR_I2C_ICSAR                  0x1c
  46 #define RCAR_I2C_ICMAR                  0x20
  47 #define RCAR_I2C_ICRXD_ICTXD            0x24
  48 #define RCAR_I2C_ICFBSCR                0x38
  49 #define RCAR_I2C_ICFBSCR_TCYC17         0x0f
  50
  51 enum rcar_i2c_type {
  52         RCAR_I2C_TYPE_GEN2,
  53         RCAR_I2C_TYPE_GEN3,
  54 };
  55
  56 struct rcar_i2c_priv {
  57         void __iomem            *base;
  58         struct clk              clk;
  59         u32                     intdelay;
  60         u32                     icccr;
  61         enum rcar_i2c_type      type;
  62 };
  63
  64 static int rcar_i2c_finish(struct udevice *dev)
  65 {
  66         struct rcar_i2c_priv *priv = dev_get_priv(dev);
  67         int ret;
  68
  69         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
  70                                 true, 10, true);
  71
  72         writel(0, priv->base + RCAR_I2C_ICSSR);
  73         writel(0, priv->base + RCAR_I2C_ICMSR);
  74         writel(0, priv->base + RCAR_I2C_ICMCR);
  75
  76         return ret;
  77 }
  78
  79 static void rcar_i2c_recover(struct udevice *dev)
  80 {
  81         struct rcar_i2c_priv *priv = dev_get_priv(dev);
  82         u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
  83         u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
  84         int i;
  85
  86         /* Send 9 SCL pulses */
  87         for (i = 0; i < 9; i++) {
  88                 writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
  89                 udelay(5);
  90                 writel(mcra, priv->base + RCAR_I2C_ICMCR);
  91                 udelay(5);
  92         }
  93
  94         /* Send stop condition */
  95         udelay(5);
  96         writel(mcra, priv->base + RCAR_I2C_ICMCR);
  97         udelay(5);
  98         writel(mcr, priv->base + RCAR_I2C_ICMCR);
  99         udelay(5);
 100         writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 101         udelay(5);
 102         writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 103         udelay(5);
 104 }
 105
 106 static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
 107 {
 108         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 109         u32 mask = RCAR_I2C_ICMSR_MAT |
 110                    (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
 111         u32 val;
 112         int ret;
 113
 114         writel(0, priv->base + RCAR_I2C_ICMIER);
 115         writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
 116         writel(0, priv->base + RCAR_I2C_ICMSR);
 117         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
 118
 119         /* Wait for the bus */
 120         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
 121                                 RCAR_I2C_ICMCR_FSDA, false, 2, true);
 122         if (ret) {
 123                 rcar_i2c_recover(dev);
 124                 val = readl(priv->base + RCAR_I2C_ICMSR);
 125                 if (val & RCAR_I2C_ICMCR_FSDA) {
 126                         dev_err(dev, "Bus busy, aborting\n");
 127                         return ret;
 128                 }
 129         }
 130
 131         writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
 132         writel(0, priv->base + RCAR_I2C_ICMSR);
 133         writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
 134                priv->base + RCAR_I2C_ICMCR);
 135
 136         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
 137                                 true, 100, true);
 138         if (ret)
 139                 return ret;
 140
 141         /* Check NAK */
 142         if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
 143                 return -EREMOTEIO;
 144
 145         return 0;
 146 }
 147
 148 static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
 149 {
 150         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 151         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
 152         int i, ret = -EREMOTEIO;
 153
 154         ret = rcar_i2c_set_addr(dev, msg->addr, 1);
 155         if (ret)
 156                 return ret;
 157
 158         for (i = 0; i < msg->len; i++) {
 159                 if (msg->len - 1 == i)
 160                         icmcr |= RCAR_I2C_ICMCR_FSB;
 161
 162                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 163                 writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
 164
 165                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
 166                                         RCAR_I2C_ICMSR_MDR, true, 100, true);
 167                 if (ret)
 168                         return ret;
 169
 170                 msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
 171         }
 172
 173         writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
 174
 175         return rcar_i2c_finish(dev);
 176 }
 177
 178 static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
 179 {
 180         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 181         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
 182         int i, ret = -EREMOTEIO;
 183
 184         ret = rcar_i2c_set_addr(dev, msg->addr, 0);
 185         if (ret)
 186                 return ret;
 187
 188         for (i = 0; i < msg->len; i++) {
 189                 writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
 190                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 191                 writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
 192
 193                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
 194                                         RCAR_I2C_ICMSR_MDE, true, 100, true);
 195                 if (ret)
 196                         return ret;
 197         }
 198
 199         writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
 200         icmcr |= RCAR_I2C_ICMCR_FSB;
 201         writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 202
 203         return rcar_i2c_finish(dev);
 204 }
 205
 206 static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
 207 {
 208         int ret;
 209
 210         for (; nmsgs > 0; nmsgs--, msg++) {
 211                 if (msg->flags & I2C_M_RD)
 212                         ret = rcar_i2c_read_common(dev, msg);
 213                 else
 214                         ret = rcar_i2c_write_common(dev, msg);
 215
 216                 if (ret)
 217                         return -EREMOTEIO;
 218         }
 219
 220         return ret;
 221 }
 222
 223 static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
 224 {
 225         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 226         int ret;
 227
 228         /* Ignore address 0, slave address */
 229         if (addr == 0)
 230                 return -EINVAL;
 231
 232         ret = rcar_i2c_set_addr(dev, addr, 1);
 233         writel(0, priv->base + RCAR_I2C_ICMSR);
 234         return ret;
 235 }
 236
 237 static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
 238 {
 239         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 240         u32 scgd, cdf, round, ick, sum, scl;
 241         unsigned long rate;
 242
 243         /*
 244          * calculate SCL clock
 245          * see
 246          *      ICCCR
 247          *
 248          * ick  = clkp / (1 + CDF)
 249          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 250          *
 251          * ick  : I2C internal clock < 20 MHz
 252          * ticf : I2C SCL falling time
 253          * tr   : I2C SCL rising  time
 254          * intd : LSI internal delay
 255          * clkp : peripheral_clk
 256          * F[]  : integer up-valuation
 257          */
 258         rate = clk_get_rate(&priv->clk);
 259         cdf = rate / 20000000;
 260         if (cdf >= 8) {
 261                 dev_err(dev, "Input clock %lu too high\n", rate);
 262                 return -EIO;
 263         }
 264         ick = rate / (cdf + 1);
 265
 266         /*
 267          * it is impossible to calculate large scale
 268          * number on u32. separate it
 269          *
 270          * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
 271          *  = F[sum * ick / 1000000000]
 272          *  = F[(ick / 1000000) * sum / 1000]
 273          */
 274         sum = 35 + 200 + priv->intdelay;
 275         round = (ick + 500000) / 1000000 * sum;
 276         round = (round + 500) / 1000;
 277
 278         /*
 279          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 280          *
 281          * Calculation result (= SCL) should be less than
 282          * bus_speed for hardware safety
 283          *
 284          * We could use something along the lines of
 285          *      div = ick / (bus_speed + 1) + 1;
 286          *      scgd = (div - 20 - round + 7) / 8;
 287          *      scl = ick / (20 + (scgd * 8) + round);
 288          * (not fully verified) but that would get pretty involved
 289          */
 290         for (scgd = 0; scgd < 0x40; scgd++) {
 291                 scl = ick / (20 + (scgd * 8) + round);
 292                 if (scl <= bus_freq_hz)
 293                         goto scgd_find;
 294         }
 295         dev_err(dev, "it is impossible to calculate best SCL\n");
 296         return -EIO;
 297
 298 scgd_find:
 299         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
 300                 scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
 301
 302         priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
 303         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
 304
 305         if (priv->type == RCAR_I2C_TYPE_GEN3) {
 306                 /* Set SCL/SDA delay */
 307                 writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
 308         }
 309
 310         return 0;
 311 }
 312
 313 static int rcar_i2c_probe(struct udevice *dev)
 314 {
 315         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 316         int ret;
 317
 318         priv->base = dev_read_addr_ptr(dev);
 319         priv->intdelay = dev_read_u32_default(dev,
 320                                               "i2c-scl-internal-delay-ns", 5);
 321         priv->type = dev_get_driver_data(dev);
 322
 323         ret = clk_get_by_index(dev, 0, &priv->clk);
 324         if (ret)
 325                 return ret;
 326
 327         ret = clk_enable(&priv->clk);
 328         if (ret)
 329                 return ret;
 330
 331         /* reset slave mode */
 332         writel(0, priv->base + RCAR_I2C_ICSIER);
 333         writel(0, priv->base + RCAR_I2C_ICSAR);
 334         writel(0, priv->base + RCAR_I2C_ICSCR);
 335         writel(0, priv->base + RCAR_I2C_ICSSR);
 336
 337         /* reset master mode */
 338         writel(0, priv->base + RCAR_I2C_ICMIER);
 339         writel(0, priv->base + RCAR_I2C_ICMCR);
 340         writel(0, priv->base + RCAR_I2C_ICMSR);
 341         writel(0, priv->base + RCAR_I2C_ICMAR);
 342
 343         ret = rcar_i2c_set_speed(dev, 100000);
 344         if (ret)
 345                 clk_disable(&priv->clk);
 346
 347         return ret;
 348 }
 349
 350 static const struct dm_i2c_ops rcar_i2c_ops = {
 351         .xfer           = rcar_i2c_xfer,
 352         .probe_chip     = rcar_i2c_probe_chip,
 353         .set_bus_speed  = rcar_i2c_set_speed,
 354 };
 355
 356 static const struct udevice_id rcar_i2c_ids[] = {
 357         { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
 358         { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
 359         { }
 360 };
 361
 362 U_BOOT_DRIVER(i2c_rcar) = {
 363         .name           = "i2c_rcar",
 364         .id             = UCLASS_I2C,
 365         .of_match       = rcar_i2c_ids,
 366         .probe          = rcar_i2c_probe,
 367         .priv_auto_alloc_size = sizeof(struct rcar_i2c_priv),
 368         .ops            = &rcar_i2c_ops,
 369 };