Merge branch 'master' of git://git.denx.de/u-boot-socfpga
[platform/kernel/u-boot.git] / drivers / i2c / rcar_i2c.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * drivers/i2c/rcar_i2c.c
4  *
5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6  *
7  * Clock configuration based on Linux i2c-rcar.c:
8  * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
9  * Copyright (C) 2011-2015 Renesas Electronics Corporation
10  * Copyright (C) 2012-14 Renesas Solutions Corp.
11  *   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
12  */
13
14 #include <common.h>
15 #include <clk.h>
16 #include <dm.h>
17 #include <i2c.h>
18 #include <asm/io.h>
19 #include <wait_bit.h>
20
21 #define RCAR_I2C_ICSCR                  0x00 /* slave ctrl */
22 #define RCAR_I2C_ICMCR                  0x04 /* master ctrl */
23 #define RCAR_I2C_ICMCR_MDBS             BIT(7) /* non-fifo mode switch */
24 #define RCAR_I2C_ICMCR_FSCL             BIT(6) /* override SCL pin */
25 #define RCAR_I2C_ICMCR_FSDA             BIT(5) /* override SDA pin */
26 #define RCAR_I2C_ICMCR_OBPC             BIT(4) /* override pins */
27 #define RCAR_I2C_ICMCR_MIE              BIT(3) /* master if enable */
28 #define RCAR_I2C_ICMCR_TSBE             BIT(2)
29 #define RCAR_I2C_ICMCR_FSB              BIT(1) /* force stop bit */
30 #define RCAR_I2C_ICMCR_ESG              BIT(0) /* enable start bit gen */
31 #define RCAR_I2C_ICSSR                  0x08 /* slave status */
32 #define RCAR_I2C_ICMSR                  0x0c /* master status */
33 #define RCAR_I2C_ICMSR_MASK             0x7f
34 #define RCAR_I2C_ICMSR_MNR              BIT(6) /* Nack */
35 #define RCAR_I2C_ICMSR_MAL              BIT(5) /* Arbitration lost */
36 #define RCAR_I2C_ICMSR_MST              BIT(4) /* Stop */
37 #define RCAR_I2C_ICMSR_MDE              BIT(3)
38 #define RCAR_I2C_ICMSR_MDT              BIT(2)
39 #define RCAR_I2C_ICMSR_MDR              BIT(1)
40 #define RCAR_I2C_ICMSR_MAT              BIT(0)
41 #define RCAR_I2C_ICSIER                 0x10 /* slave irq enable */
42 #define RCAR_I2C_ICMIER                 0x14 /* master irq enable */
43 #define RCAR_I2C_ICCCR                  0x18 /* clock dividers */
44 #define RCAR_I2C_ICCCR_SCGD_OFF         3
45 #define RCAR_I2C_ICSAR                  0x1c /* slave address */
46 #define RCAR_I2C_ICMAR                  0x20 /* master address */
47 #define RCAR_I2C_ICRXD_ICTXD            0x24 /* data port */
48 /*
49  * First Bit Setup Cycle (Gen3).
50  * Defines 1st bit delay between SDA and SCL.
51  */
52 #define RCAR_I2C_ICFBSCR                0x38
53 #define RCAR_I2C_ICFBSCR_TCYC17         0x0f /* 17*Tcyc */
54
55
56 enum rcar_i2c_type {
57         RCAR_I2C_TYPE_GEN2,
58         RCAR_I2C_TYPE_GEN3,
59 };
60
61 struct rcar_i2c_priv {
62         void __iomem            *base;
63         struct clk              clk;
64         u32                     intdelay;
65         u32                     icccr;
66         enum rcar_i2c_type      type;
67 };
68
69 static int rcar_i2c_finish(struct udevice *dev)
70 {
71         struct rcar_i2c_priv *priv = dev_get_priv(dev);
72         int ret;
73
74         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
75                                 true, 10, true);
76
77         writel(0, priv->base + RCAR_I2C_ICSSR);
78         writel(0, priv->base + RCAR_I2C_ICMSR);
79         writel(0, priv->base + RCAR_I2C_ICMCR);
80
81         return ret;
82 }
83
84 static int rcar_i2c_recover(struct udevice *dev)
85 {
86         struct rcar_i2c_priv *priv = dev_get_priv(dev);
87         u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
88         u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
89         int i;
90         u32 mstat;
91
92         /* Send 9 SCL pulses */
93         for (i = 0; i < 9; i++) {
94                 writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
95                 udelay(5);
96                 writel(mcra, priv->base + RCAR_I2C_ICMCR);
97                 udelay(5);
98         }
99
100         /* Send stop condition */
101         udelay(5);
102         writel(mcra, priv->base + RCAR_I2C_ICMCR);
103         udelay(5);
104         writel(mcr, priv->base + RCAR_I2C_ICMCR);
105         udelay(5);
106         writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
107         udelay(5);
108         writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
109         udelay(5);
110
111         mstat = readl(priv->base + RCAR_I2C_ICMSR);
112         return mstat & RCAR_I2C_ICMCR_FSDA ? -EBUSY : 0;
113 }
114
115 static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
116 {
117         struct rcar_i2c_priv *priv = dev_get_priv(dev);
118         u32 mask = RCAR_I2C_ICMSR_MAT |
119                    (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
120         int ret;
121
122         writel(0, priv->base + RCAR_I2C_ICMIER);
123         writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
124         writel(0, priv->base + RCAR_I2C_ICMSR);
125         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
126
127         /* Wait for the bus */
128         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
129                                 RCAR_I2C_ICMCR_FSDA, false, 2, true);
130         if (ret) {
131                 if (rcar_i2c_recover(dev)) {
132                         dev_err(dev, "Bus busy, aborting\n");
133                         return ret;
134                 }
135         }
136
137         writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
138         /* Reset */
139         writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
140                priv->base + RCAR_I2C_ICMCR);
141         /* Clear Status */
142         writel(0, priv->base + RCAR_I2C_ICMSR);
143
144         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
145                                 true, 100, true);
146         if (ret)
147                 return ret;
148
149         /* Check NAK */
150         if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
151                 return -EREMOTEIO;
152
153         return 0;
154 }
155
156 static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
157 {
158         struct rcar_i2c_priv *priv = dev_get_priv(dev);
159         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
160         int i, ret = -EREMOTEIO;
161
162         for (i = 0; i < msg->len; i++) {
163                 if (msg->len - 1 == i)
164                         icmcr |= RCAR_I2C_ICMCR_FSB;
165
166                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
167                 writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
168
169                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
170                                         RCAR_I2C_ICMSR_MDR, true, 100, true);
171                 if (ret)
172                         return ret;
173
174                 msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
175         }
176
177         writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
178
179         return rcar_i2c_finish(dev);
180 }
181
182 static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
183 {
184         struct rcar_i2c_priv *priv = dev_get_priv(dev);
185         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
186         int i, ret = -EREMOTEIO;
187
188         for (i = 0; i < msg->len; i++) {
189                 writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
190                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
191                 writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
192
193                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
194                                         RCAR_I2C_ICMSR_MDE, true, 100, true);
195                 if (ret)
196                         return ret;
197         }
198
199         writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
200         icmcr |= RCAR_I2C_ICMCR_FSB;
201         writel(icmcr, priv->base + RCAR_I2C_ICMCR);
202
203         return rcar_i2c_finish(dev);
204 }
205
206 static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
207 {
208         int ret;
209
210         for (; nmsgs > 0; nmsgs--, msg++) {
211                 ret = rcar_i2c_set_addr(dev, msg->addr, 1);
212                 if (ret)
213                         return ret;
214
215                 if (msg->flags & I2C_M_RD)
216                         ret = rcar_i2c_read_common(dev, msg);
217                 else
218                         ret = rcar_i2c_write_common(dev, msg);
219
220                 if (ret)
221                         return ret;
222         }
223
224         return 0;
225 }
226
227 static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
228 {
229         struct rcar_i2c_priv *priv = dev_get_priv(dev);
230         int ret;
231
232         /* Ignore address 0, slave address */
233         if (addr == 0)
234                 return -EINVAL;
235
236         ret = rcar_i2c_set_addr(dev, addr, 1);
237         writel(0, priv->base + RCAR_I2C_ICMSR);
238         return ret;
239 }
240
241 static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
242 {
243         struct rcar_i2c_priv *priv = dev_get_priv(dev);
244         u32 scgd, cdf, round, ick, sum, scl;
245         unsigned long rate;
246
247         /*
248          * calculate SCL clock
249          * see
250          *      ICCCR
251          *
252          * ick  = clkp / (1 + CDF)
253          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
254          *
255          * ick  : I2C internal clock < 20 MHz
256          * ticf : I2C SCL falling time
257          * tr   : I2C SCL rising  time
258          * intd : LSI internal delay
259          * clkp : peripheral_clk
260          * F[]  : integer up-valuation
261          */
262         rate = clk_get_rate(&priv->clk);
263         cdf = rate / 20000000;
264         if (cdf >= 8) {
265                 dev_err(dev, "Input clock %lu too high\n", rate);
266                 return -EIO;
267         }
268         ick = rate / (cdf + 1);
269
270         /*
271          * it is impossible to calculate large scale
272          * number on u32. separate it
273          *
274          * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
275          *  = F[sum * ick / 1000000000]
276          *  = F[(ick / 1000000) * sum / 1000]
277          */
278         sum = 35 + 200 + priv->intdelay;
279         round = (ick + 500000) / 1000000 * sum;
280         round = (round + 500) / 1000;
281
282         /*
283          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
284          *
285          * Calculation result (= SCL) should be less than
286          * bus_speed for hardware safety
287          *
288          * We could use something along the lines of
289          *      div = ick / (bus_speed + 1) + 1;
290          *      scgd = (div - 20 - round + 7) / 8;
291          *      scl = ick / (20 + (scgd * 8) + round);
292          * (not fully verified) but that would get pretty involved
293          */
294         for (scgd = 0; scgd < 0x40; scgd++) {
295                 scl = ick / (20 + (scgd * 8) + round);
296                 if (scl <= bus_freq_hz)
297                         goto scgd_find;
298         }
299         dev_err(dev, "it is impossible to calculate best SCL\n");
300         return -EIO;
301
302 scgd_find:
303         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
304                 scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
305
306         priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
307         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
308
309         if (priv->type == RCAR_I2C_TYPE_GEN3) {
310                 /* Set SCL/SDA delay */
311                 writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
312         }
313
314         return 0;
315 }
316
317 static int rcar_i2c_probe(struct udevice *dev)
318 {
319         struct rcar_i2c_priv *priv = dev_get_priv(dev);
320         int ret;
321
322         priv->base = dev_read_addr_ptr(dev);
323         priv->intdelay = dev_read_u32_default(dev,
324                                               "i2c-scl-internal-delay-ns", 5);
325         priv->type = dev_get_driver_data(dev);
326
327         ret = clk_get_by_index(dev, 0, &priv->clk);
328         if (ret)
329                 return ret;
330
331         ret = clk_enable(&priv->clk);
332         if (ret)
333                 return ret;
334
335         /* reset slave mode */
336         writel(0, priv->base + RCAR_I2C_ICSIER);
337         writel(0, priv->base + RCAR_I2C_ICSAR);
338         writel(0, priv->base + RCAR_I2C_ICSCR);
339         writel(0, priv->base + RCAR_I2C_ICSSR);
340
341         /* reset master mode */
342         writel(0, priv->base + RCAR_I2C_ICMIER);
343         writel(0, priv->base + RCAR_I2C_ICMCR);
344         writel(0, priv->base + RCAR_I2C_ICMSR);
345         writel(0, priv->base + RCAR_I2C_ICMAR);
346
347         ret = rcar_i2c_set_speed(dev, 100000);
348         if (ret)
349                 clk_disable(&priv->clk);
350
351         return ret;
352 }
353
354 static const struct dm_i2c_ops rcar_i2c_ops = {
355         .xfer           = rcar_i2c_xfer,
356         .probe_chip     = rcar_i2c_probe_chip,
357         .set_bus_speed  = rcar_i2c_set_speed,
358 };
359
360 static const struct udevice_id rcar_i2c_ids[] = {
361         { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
362         { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
363         { }
364 };
365
366 U_BOOT_DRIVER(i2c_rcar) = {
367         .name           = "i2c_rcar",
368         .id             = UCLASS_I2C,
369         .of_match       = rcar_i2c_ids,
370         .probe          = rcar_i2c_probe,
371         .priv_auto_alloc_size = sizeof(struct rcar_i2c_priv),
372         .ops            = &rcar_i2c_ops,
373 };