1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/i2c/rcar_i2c.c
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
7 * Clock configuration based on Linux i2c-rcar.c:
8 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
9 * Copyright (C) 2011-2015 Renesas Electronics Corporation
10 * Copyright (C) 2012-14 Renesas Solutions Corp.
11 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
21 #define RCAR_I2C_ICSCR 0x00
22 #define RCAR_I2C_ICMCR 0x04
23 #define RCAR_I2C_ICMCR_MDBS BIT(7)
24 #define RCAR_I2C_ICMCR_FSCL BIT(6)
25 #define RCAR_I2C_ICMCR_FSDA BIT(5)
26 #define RCAR_I2C_ICMCR_OBPC BIT(4)
27 #define RCAR_I2C_ICMCR_MIE BIT(3)
28 #define RCAR_I2C_ICMCR_TSBE BIT(2)
29 #define RCAR_I2C_ICMCR_FSB BIT(1)
30 #define RCAR_I2C_ICMCR_ESG BIT(0)
31 #define RCAR_I2C_ICSSR 0x08
32 #define RCAR_I2C_ICMSR 0x0c
33 #define RCAR_I2C_ICMSR_MASK 0x7f
34 #define RCAR_I2C_ICMSR_MNR BIT(6)
35 #define RCAR_I2C_ICMSR_MAL BIT(5)
36 #define RCAR_I2C_ICMSR_MST BIT(4)
37 #define RCAR_I2C_ICMSR_MDE BIT(3)
38 #define RCAR_I2C_ICMSR_MDT BIT(2)
39 #define RCAR_I2C_ICMSR_MDR BIT(1)
40 #define RCAR_I2C_ICMSR_MAT BIT(0)
41 #define RCAR_I2C_ICSIER 0x10
42 #define RCAR_I2C_ICMIER 0x14
43 #define RCAR_I2C_ICCCR 0x18
44 #define RCAR_I2C_ICCCR_SCGD_OFF 3
45 #define RCAR_I2C_ICSAR 0x1c
46 #define RCAR_I2C_ICMAR 0x20
47 #define RCAR_I2C_ICRXD_ICTXD 0x24
48 #define RCAR_I2C_ICFBSCR 0x38
49 #define RCAR_I2C_ICFBSCR_TCYC17 0x0f
56 struct rcar_i2c_priv {
61 enum rcar_i2c_type type;
64 static int rcar_i2c_finish(struct udevice *dev)
66 struct rcar_i2c_priv *priv = dev_get_priv(dev);
69 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
72 writel(0, priv->base + RCAR_I2C_ICSSR);
73 writel(0, priv->base + RCAR_I2C_ICMSR);
74 writel(0, priv->base + RCAR_I2C_ICMCR);
79 static void rcar_i2c_recover(struct udevice *dev)
81 struct rcar_i2c_priv *priv = dev_get_priv(dev);
82 u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
83 u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
86 /* Send 9 SCL pulses */
87 for (i = 0; i < 9; i++) {
88 writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
90 writel(mcra, priv->base + RCAR_I2C_ICMCR);
94 /* Send stop condition */
96 writel(mcra, priv->base + RCAR_I2C_ICMCR);
98 writel(mcr, priv->base + RCAR_I2C_ICMCR);
100 writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
102 writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
106 static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
108 struct rcar_i2c_priv *priv = dev_get_priv(dev);
109 u32 mask = RCAR_I2C_ICMSR_MAT |
110 (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
114 writel(0, priv->base + RCAR_I2C_ICMIER);
115 writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
116 writel(0, priv->base + RCAR_I2C_ICMSR);
117 writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
119 if (priv->type == RCAR_I2C_TYPE_GEN3)
120 writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
122 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
123 RCAR_I2C_ICMCR_FSDA, false, 2, true);
125 rcar_i2c_recover(dev);
126 val = readl(priv->base + RCAR_I2C_ICMSR);
127 if (val & RCAR_I2C_ICMCR_FSDA) {
128 dev_err(dev, "Bus busy, aborting\n");
133 writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
134 writel(0, priv->base + RCAR_I2C_ICMSR);
135 writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
136 priv->base + RCAR_I2C_ICMCR);
138 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
144 if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
150 static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
152 struct rcar_i2c_priv *priv = dev_get_priv(dev);
153 u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
154 int i, ret = -EREMOTEIO;
156 ret = rcar_i2c_set_addr(dev, msg->addr, 1);
160 for (i = 0; i < msg->len; i++) {
161 if (msg->len - 1 == i)
162 icmcr |= RCAR_I2C_ICMCR_FSB;
164 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
165 writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
167 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
168 RCAR_I2C_ICMSR_MDR, true, 100, true);
172 msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
175 writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
177 return rcar_i2c_finish(dev);
180 static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
182 struct rcar_i2c_priv *priv = dev_get_priv(dev);
183 u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
184 int i, ret = -EREMOTEIO;
186 ret = rcar_i2c_set_addr(dev, msg->addr, 0);
190 for (i = 0; i < msg->len; i++) {
191 writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
192 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
193 writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
195 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
196 RCAR_I2C_ICMSR_MDE, true, 100, true);
201 writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
202 icmcr |= RCAR_I2C_ICMCR_FSB;
203 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
205 return rcar_i2c_finish(dev);
208 static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
212 for (; nmsgs > 0; nmsgs--, msg++) {
213 if (msg->flags & I2C_M_RD)
214 ret = rcar_i2c_read_common(dev, msg);
216 ret = rcar_i2c_write_common(dev, msg);
225 static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
227 struct rcar_i2c_priv *priv = dev_get_priv(dev);
230 /* Ignore address 0, slave address */
234 ret = rcar_i2c_set_addr(dev, addr, 1);
235 writel(0, priv->base + RCAR_I2C_ICMSR);
239 static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
241 struct rcar_i2c_priv *priv = dev_get_priv(dev);
242 u32 scgd, cdf, round, ick, sum, scl;
246 * calculate SCL clock
250 * ick = clkp / (1 + CDF)
251 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
253 * ick : I2C internal clock < 20 MHz
254 * ticf : I2C SCL falling time
255 * tr : I2C SCL rising time
256 * intd : LSI internal delay
257 * clkp : peripheral_clk
258 * F[] : integer up-valuation
260 rate = clk_get_rate(&priv->clk);
261 cdf = rate / 20000000;
263 dev_err(dev, "Input clock %lu too high\n", rate);
266 ick = rate / (cdf + 1);
269 * it is impossible to calculate large scale
270 * number on u32. separate it
272 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
273 * = F[sum * ick / 1000000000]
274 * = F[(ick / 1000000) * sum / 1000]
276 sum = 35 + 200 + priv->intdelay;
277 round = (ick + 500000) / 1000000 * sum;
278 round = (round + 500) / 1000;
281 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
283 * Calculation result (= SCL) should be less than
284 * bus_speed for hardware safety
286 * We could use something along the lines of
287 * div = ick / (bus_speed + 1) + 1;
288 * scgd = (div - 20 - round + 7) / 8;
289 * scl = ick / (20 + (scgd * 8) + round);
290 * (not fully verified) but that would get pretty involved
292 for (scgd = 0; scgd < 0x40; scgd++) {
293 scl = ick / (20 + (scgd * 8) + round);
294 if (scl <= bus_freq_hz)
297 dev_err(dev, "it is impossible to calculate best SCL\n");
301 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
302 scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
304 priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
305 writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
310 static int rcar_i2c_probe(struct udevice *dev)
312 struct rcar_i2c_priv *priv = dev_get_priv(dev);
315 priv->base = dev_read_addr_ptr(dev);
316 priv->intdelay = dev_read_u32_default(dev,
317 "i2c-scl-internal-delay-ns", 5);
318 priv->type = dev_get_driver_data(dev);
320 ret = clk_get_by_index(dev, 0, &priv->clk);
324 ret = clk_enable(&priv->clk);
328 /* reset slave mode */
329 writel(0, priv->base + RCAR_I2C_ICSIER);
330 writel(0, priv->base + RCAR_I2C_ICSAR);
331 writel(0, priv->base + RCAR_I2C_ICSCR);
332 writel(0, priv->base + RCAR_I2C_ICSSR);
334 /* reset master mode */
335 writel(0, priv->base + RCAR_I2C_ICMIER);
336 writel(0, priv->base + RCAR_I2C_ICMCR);
337 writel(0, priv->base + RCAR_I2C_ICMSR);
338 writel(0, priv->base + RCAR_I2C_ICMAR);
340 ret = rcar_i2c_set_speed(dev, 100000);
342 clk_disable(&priv->clk);
347 static const struct dm_i2c_ops rcar_i2c_ops = {
348 .xfer = rcar_i2c_xfer,
349 .probe_chip = rcar_i2c_probe_chip,
350 .set_bus_speed = rcar_i2c_set_speed,
353 static const struct udevice_id rcar_i2c_ids[] = {
354 { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
355 { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
359 U_BOOT_DRIVER(i2c_rcar) = {
362 .of_match = rcar_i2c_ids,
363 .probe = rcar_i2c_probe,
364 .priv_auto_alloc_size = sizeof(struct rcar_i2c_priv),
365 .ops = &rcar_i2c_ops,