4 * Copyright (c) 2004 Texas Instruments
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
21 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22 * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23 * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24 * OMAPs and derivatives as well. The only anticipated exception would
25 * be the OMAP2420, which shall require driver modification.
26 * - Rewritten i2c_read to operate correctly with all types of chips
27 * (old function could not read consistent data from some I2C slaves).
28 * - Optimized i2c_write.
29 * - New i2c_probe, performs write access vs read. The old probe could
30 * hang the system under certain conditions (e.g. unconfigured pads).
31 * - The read/write/probe functions try to identify unconfigured bus.
32 * - Status functions now read irqstatus_raw as per TRM guidelines
33 * (except for OMAP243X and OMAP34XX).
34 * - Driver now supports up to I2C5 (OMAP5).
40 #include <asm/arch/i2c.h>
43 #include "omap24xx_i2c.h"
45 DECLARE_GLOBAL_DATA_PTR;
47 #define I2C_TIMEOUT 1000
49 /* Absolutely safe for status update at 100 kHz I2C: */
52 static int wait_for_bb(struct i2c_adapter *adap);
53 static struct i2c *omap24_get_base(struct i2c_adapter *adap);
54 static u16 wait_for_event(struct i2c_adapter *adap);
55 static void flush_fifo(struct i2c_adapter *adap);
57 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
59 struct i2c *i2c_base = omap24_get_base(adap);
60 int psc, fsscll, fssclh;
61 int hsscll = 0, hssclh = 0;
63 int timeout = I2C_TIMEOUT;
65 /* Only handle standard, fast and high speeds */
66 if ((speed != OMAP_I2C_STANDARD) &&
67 (speed != OMAP_I2C_FAST_MODE) &&
68 (speed != OMAP_I2C_HIGH_SPEED)) {
69 printf("Error : I2C unsupported speed %d\n", speed);
73 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
75 if (psc < I2C_PSC_MIN) {
76 printf("Error : I2C unsupported prescalar %d\n", psc);
80 if (speed == OMAP_I2C_HIGH_SPEED) {
83 /* For first phase of HS mode */
84 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
85 (2 * OMAP_I2C_FAST_MODE);
87 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
88 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
89 if (((fsscll < 0) || (fssclh < 0)) ||
90 ((fsscll > 255) || (fssclh > 255))) {
91 puts("Error : I2C initializing first phase clock\n");
95 /* For second phase of HS mode */
96 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
98 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
99 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
100 if (((fsscll < 0) || (fssclh < 0)) ||
101 ((fsscll > 255) || (fssclh > 255))) {
102 puts("Error : I2C initializing second phase clock\n");
106 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
107 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
110 /* Standard and fast speed */
111 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
113 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
114 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
115 if (((fsscll < 0) || (fssclh < 0)) ||
116 ((fsscll > 255) || (fssclh > 255))) {
117 puts("Error : I2C initializing clock\n");
121 scll = (unsigned int)fsscll;
122 sclh = (unsigned int)fssclh;
125 if (readw(&i2c_base->con) & I2C_CON_EN) {
126 writew(0, &i2c_base->con);
130 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
133 writew(I2C_CON_EN, &i2c_base->con);
134 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
136 puts("ERROR: Timeout in soft-reset\n");
142 writew(0, &i2c_base->con);
143 writew(psc, &i2c_base->psc);
144 writew(scll, &i2c_base->scll);
145 writew(sclh, &i2c_base->sclh);
148 writew(slaveadd, &i2c_base->oa);
149 writew(I2C_CON_EN, &i2c_base->con);
150 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
152 * Have to enable interrupts for OMAP2/3, these IPs don't have
153 * an 'irqstatus_raw' register and we shall have to poll 'stat'
155 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
156 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
160 writew(0xFFFF, &i2c_base->stat);
163 static void flush_fifo(struct i2c_adapter *adap)
165 struct i2c *i2c_base = omap24_get_base(adap);
168 /* note: if you try and read data when its not there or ready
169 * you get a bus error
172 stat = readw(&i2c_base->stat);
173 if (stat == I2C_STAT_RRDY) {
174 readb(&i2c_base->data);
175 writew(I2C_STAT_RRDY, &i2c_base->stat);
183 * i2c_probe: Use write access. Allows to identify addresses that are
184 * write-only (like the config register of dual-port EEPROMs)
186 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
188 struct i2c *i2c_base = omap24_get_base(adap);
190 int res = 1; /* default = fail */
192 if (chip == readw(&i2c_base->oa))
195 /* Wait until bus is free */
196 if (wait_for_bb(adap))
199 /* No data transfer, slave addr only */
200 writew(chip, &i2c_base->sa);
201 /* Stop bit needed here */
202 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
203 I2C_CON_STP, &i2c_base->con);
205 status = wait_for_event(adap);
207 if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
209 * With current high-level command implementation, notifying
210 * the user shall flood the console with 127 messages. If
211 * silent exit is desired upon unconfigured bus, remove the
212 * following 'if' section:
214 if (status == I2C_STAT_XRDY)
215 printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
216 adap->hwadapnr, status);
221 /* Check for ACK (!NAK) */
222 if (!(status & I2C_STAT_NACK)) {
223 res = 0; /* Device found */
224 udelay(I2C_WAIT); /* Required by AM335X in SPL */
225 /* Abort transfer (force idle state) */
226 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
228 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
229 I2C_CON_STP, &i2c_base->con); /* STP */
233 writew(0xFFFF, &i2c_base->stat);
238 * i2c_read: Function now uses a single I2C read transaction with bulk transfer
239 * of the requested number of bytes (note that the 'i2c md' command
240 * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
241 * defined in the board config header, this transaction shall be with
242 * Repeated Start (Sr) between the address and data phases; otherwise
243 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
244 * The address (reg offset) may be 0, 1 or 2 bytes long.
245 * Function now reads correctly from chips that return more than one
246 * byte of data per addressed register (like TI temperature sensors),
247 * or that do not need a register address at all (such as some clock
250 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
251 int alen, uchar *buffer, int len)
253 struct i2c *i2c_base = omap24_get_base(adap);
258 puts("I2C read: addr len < 0\n");
262 puts("I2C read: data len < 0\n");
265 if (buffer == NULL) {
266 puts("I2C read: NULL pointer passed\n");
271 printf("I2C read: addr len %d not supported\n", alen);
275 if (addr + len > (1 << 16)) {
276 puts("I2C read: address out of range\n");
280 /* Wait until bus not busy */
281 if (wait_for_bb(adap))
284 /* Zero, one or two bytes reg address (offset) */
285 writew(alen, &i2c_base->cnt);
286 /* Set slave address */
287 writew(chip, &i2c_base->sa);
290 /* Must write reg offset first */
291 #ifdef CONFIG_I2C_REPEATED_START
292 /* No stop bit, use Repeated Start (Sr) */
293 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
294 I2C_CON_TRX, &i2c_base->con);
296 /* Stop - Start (P-S) */
297 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
298 I2C_CON_TRX, &i2c_base->con);
300 /* Send register offset */
302 status = wait_for_event(adap);
303 /* Try to identify bus that is not padconf'd for I2C */
304 if (status == I2C_STAT_XRDY) {
306 printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
307 adap->hwadapnr, status);
310 if (status == 0 || status & I2C_STAT_NACK) {
312 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
317 if (status & I2C_STAT_XRDY) {
319 /* Do we have to use byte access? */
320 writeb((addr >> (8 * alen)) & 0xff,
322 writew(I2C_STAT_XRDY, &i2c_base->stat);
325 if (status & I2C_STAT_ARDY) {
326 writew(I2C_STAT_ARDY, &i2c_base->stat);
331 /* Set slave address */
332 writew(chip, &i2c_base->sa);
333 /* Read len bytes from slave */
334 writew(len, &i2c_base->cnt);
335 /* Need stop bit here */
336 writew(I2C_CON_EN | I2C_CON_MST |
337 I2C_CON_STT | I2C_CON_STP,
342 status = wait_for_event(adap);
344 * Try to identify bus that is not padconf'd for I2C. This
345 * state could be left over from previous transactions if
346 * the address phase is skipped due to alen=0.
348 if (status == I2C_STAT_XRDY) {
350 printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
351 adap->hwadapnr, status);
354 if (status == 0 || status & I2C_STAT_NACK) {
358 if (status & I2C_STAT_RRDY) {
359 *buffer++ = readb(&i2c_base->data);
360 writew(I2C_STAT_RRDY, &i2c_base->stat);
362 if (status & I2C_STAT_ARDY) {
363 writew(I2C_STAT_ARDY, &i2c_base->stat);
370 writew(0xFFFF, &i2c_base->stat);
374 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
375 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
376 int alen, uchar *buffer, int len)
378 struct i2c *i2c_base = omap24_get_base(adap);
384 puts("I2C write: addr len < 0\n");
389 puts("I2C write: data len < 0\n");
393 if (buffer == NULL) {
394 puts("I2C write: NULL pointer passed\n");
399 printf("I2C write: addr len %d not supported\n", alen);
403 if (addr + len > (1 << 16)) {
404 printf("I2C write: address 0x%x + 0x%x out of range\n",
409 /* Wait until bus not busy */
410 if (wait_for_bb(adap))
413 /* Start address phase - will write regoffset + len bytes data */
414 writew(alen + len, &i2c_base->cnt);
415 /* Set slave address */
416 writew(chip, &i2c_base->sa);
417 /* Stop bit needed here */
418 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
419 I2C_CON_STP, &i2c_base->con);
422 /* Must write reg offset (one or two bytes) */
423 status = wait_for_event(adap);
424 /* Try to identify bus that is not padconf'd for I2C */
425 if (status == I2C_STAT_XRDY) {
427 printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
428 adap->hwadapnr, status);
431 if (status == 0 || status & I2C_STAT_NACK) {
433 printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
437 if (status & I2C_STAT_XRDY) {
439 writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
440 writew(I2C_STAT_XRDY, &i2c_base->stat);
443 printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
448 /* Address phase is over, now write data */
449 for (i = 0; i < len; i++) {
450 status = wait_for_event(adap);
451 if (status == 0 || status & I2C_STAT_NACK) {
453 printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
457 if (status & I2C_STAT_XRDY) {
458 writeb(buffer[i], &i2c_base->data);
459 writew(I2C_STAT_XRDY, &i2c_base->stat);
462 printf("i2c_write: bus not ready for data Tx (i=%d)\n",
470 writew(0xFFFF, &i2c_base->stat);
475 * Wait for the bus to be free by checking the Bus Busy (BB)
476 * bit to become clear
478 static int wait_for_bb(struct i2c_adapter *adap)
480 struct i2c *i2c_base = omap24_get_base(adap);
481 int timeout = I2C_TIMEOUT;
484 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
485 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
486 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
488 /* Read RAW status */
489 while ((stat = readw(&i2c_base->irqstatus_raw) &
490 I2C_STAT_BB) && timeout--) {
492 writew(stat, &i2c_base->stat);
497 printf("Timed out in wait_for_bb: status=%04x\n",
501 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
506 * Wait for the I2C controller to complete current action
509 static u16 wait_for_event(struct i2c_adapter *adap)
511 struct i2c *i2c_base = omap24_get_base(adap);
513 int timeout = I2C_TIMEOUT;
517 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
518 status = readw(&i2c_base->stat);
520 /* Read RAW status */
521 status = readw(&i2c_base->irqstatus_raw);
524 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
525 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
526 I2C_STAT_AL)) && timeout--);
529 printf("Timed out in wait_for_event: status=%04x\n",
532 * If status is still 0 here, probably the bus pads have
533 * not been configured for I2C, and/or pull-ups are missing.
535 printf("Check if pads/pull-ups of bus %d are properly configured\n",
537 writew(0xFFFF, &i2c_base->stat);
544 static struct i2c *omap24_get_base(struct i2c_adapter *adap)
546 switch (adap->hwadapnr) {
548 return (struct i2c *)I2C_BASE1;
551 return (struct i2c *)I2C_BASE2;
553 #if (I2C_BUS_MAX > 2)
555 return (struct i2c *)I2C_BASE3;
557 #if (I2C_BUS_MAX > 3)
559 return (struct i2c *)I2C_BASE4;
561 #if (I2C_BUS_MAX > 4)
563 return (struct i2c *)I2C_BASE5;
569 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
575 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
576 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
578 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
579 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
582 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
583 omap24_i2c_read, omap24_i2c_write, NULL,
584 CONFIG_SYS_OMAP24_I2C_SPEED,
585 CONFIG_SYS_OMAP24_I2C_SLAVE,
587 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
588 omap24_i2c_read, omap24_i2c_write, NULL,
589 CONFIG_SYS_OMAP24_I2C_SPEED1,
590 CONFIG_SYS_OMAP24_I2C_SLAVE1,
592 #if (I2C_BUS_MAX > 2)
593 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
594 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
596 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
597 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
600 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
601 omap24_i2c_read, omap24_i2c_write, NULL,
602 CONFIG_SYS_OMAP24_I2C_SPEED2,
603 CONFIG_SYS_OMAP24_I2C_SLAVE2,
605 #if (I2C_BUS_MAX > 3)
606 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
607 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
609 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
610 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
613 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
614 omap24_i2c_read, omap24_i2c_write, NULL,
615 CONFIG_SYS_OMAP24_I2C_SPEED3,
616 CONFIG_SYS_OMAP24_I2C_SLAVE3,
618 #if (I2C_BUS_MAX > 4)
619 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
620 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
622 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
623 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
626 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
627 omap24_i2c_read, omap24_i2c_write, NULL,
628 CONFIG_SYS_OMAP24_I2C_SPEED4,
629 CONFIG_SYS_OMAP24_I2C_SLAVE4,