4 * Copyright (c) 2004 Texas Instruments
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
25 #include <asm/arch/i2c.h>
28 #include "omap24xx_i2c.h"
30 DECLARE_GLOBAL_DATA_PTR;
32 #define I2C_TIMEOUT 1000
34 static int wait_for_bb(void);
35 static u16 wait_for_pin(void);
36 static void flush_fifo(void);
39 * For SPL boot some boards need i2c before SDRAM is initialised so force
40 * variables to live in SRAM
42 static struct i2c __attribute__((section (".data"))) *i2c_base =
43 (struct i2c *)I2C_DEFAULT_BASE;
44 static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
45 { [0 ... (I2C_BUS_MAX-1)] = 0 };
46 static unsigned int __attribute__((section (".data"))) current_bus = 0;
48 void i2c_init(int speed, int slaveadd)
50 int psc, fsscll, fssclh;
51 int hsscll = 0, hssclh = 0;
53 int timeout = I2C_TIMEOUT;
55 /* Only handle standard, fast and high speeds */
56 if ((speed != OMAP_I2C_STANDARD) &&
57 (speed != OMAP_I2C_FAST_MODE) &&
58 (speed != OMAP_I2C_HIGH_SPEED)) {
59 printf("Error : I2C unsupported speed %d\n", speed);
63 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
65 if (psc < I2C_PSC_MIN) {
66 printf("Error : I2C unsupported prescalar %d\n", psc);
70 if (speed == OMAP_I2C_HIGH_SPEED) {
73 /* For first phase of HS mode */
74 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
75 (2 * OMAP_I2C_FAST_MODE);
77 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
78 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
79 if (((fsscll < 0) || (fssclh < 0)) ||
80 ((fsscll > 255) || (fssclh > 255))) {
81 puts("Error : I2C initializing first phase clock\n");
85 /* For second phase of HS mode */
86 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
88 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
89 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
90 if (((fsscll < 0) || (fssclh < 0)) ||
91 ((fsscll > 255) || (fssclh > 255))) {
92 puts("Error : I2C initializing second phase clock\n");
96 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
97 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
100 /* Standard and fast speed */
101 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
103 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
104 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
105 if (((fsscll < 0) || (fssclh < 0)) ||
106 ((fsscll > 255) || (fssclh > 255))) {
107 puts("Error : I2C initializing clock\n");
111 scll = (unsigned int)fsscll;
112 sclh = (unsigned int)fssclh;
115 if (readw(&i2c_base->con) & I2C_CON_EN) {
116 writew(0, &i2c_base->con);
120 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
123 writew(I2C_CON_EN, &i2c_base->con);
124 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
126 puts("ERROR: Timeout in soft-reset\n");
132 writew(0, &i2c_base->con);
133 writew(psc, &i2c_base->psc);
134 writew(scll, &i2c_base->scll);
135 writew(sclh, &i2c_base->sclh);
138 writew(slaveadd, &i2c_base->oa);
139 writew(I2C_CON_EN, &i2c_base->con);
141 /* have to enable intrrupts or OMAP i2c module doesn't work */
142 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
143 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
146 writew(0xFFFF, &i2c_base->stat);
147 writew(0, &i2c_base->cnt);
149 if (gd->flags & GD_FLG_RELOC)
150 bus_initialized[current_bus] = 1;
153 static int i2c_read_byte(u8 devaddr, u16 regoffset, u8 alen, u8 *value)
158 u8 tmpbuf[2] = {(regoffset) >> 8, regoffset & 0xff};
161 /* wait until bus not busy */
166 writew(alen, &i2c_base->cnt);
167 /* set slave address */
168 writew(devaddr, &i2c_base->sa);
169 /* no stop bit needed here */
170 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
171 I2C_CON_TRX, &i2c_base->con);
173 /* send register offset */
175 status = wait_for_pin();
176 if (status == 0 || status & I2C_STAT_NACK) {
180 if (status & I2C_STAT_XRDY) {
182 #if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
183 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
184 defined(CONFIG_OMAP54XX))
185 w |= tmpbuf[i++] << 8;
187 writew(w, &i2c_base->data);
188 writew(I2C_STAT_XRDY, &i2c_base->stat);
190 if (status & I2C_STAT_ARDY) {
191 writew(I2C_STAT_ARDY, &i2c_base->stat);
196 /* set slave address */
197 writew(devaddr, &i2c_base->sa);
198 /* read one byte from slave */
199 writew(1, &i2c_base->cnt);
200 /* need stop bit here */
201 writew(I2C_CON_EN | I2C_CON_MST |
202 I2C_CON_STT | I2C_CON_STP,
207 status = wait_for_pin();
208 if (status == 0 || status & I2C_STAT_NACK) {
212 if (status & I2C_STAT_RRDY) {
213 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
214 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
215 defined(CONFIG_OMAP54XX)
216 *value = readb(&i2c_base->data);
218 *value = readw(&i2c_base->data);
220 writew(I2C_STAT_RRDY, &i2c_base->stat);
222 if (status & I2C_STAT_ARDY) {
223 writew(I2C_STAT_ARDY, &i2c_base->stat);
230 writew(0xFFFF, &i2c_base->stat);
231 writew(0, &i2c_base->cnt);
235 static void flush_fifo(void)
238 /* note: if you try and read data when its not there or ready
239 * you get a bus error
242 stat = readw(&i2c_base->stat);
243 if (stat == I2C_STAT_RRDY) {
244 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
245 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
246 defined(CONFIG_OMAP54XX)
247 readb(&i2c_base->data);
249 readw(&i2c_base->data);
251 writew(I2C_STAT_RRDY, &i2c_base->stat);
258 int i2c_probe(uchar chip)
261 int res = 1; /* default = fail */
263 if (chip == readw(&i2c_base->oa))
266 /* wait until bus not busy */
270 /* try to read one byte */
271 writew(1, &i2c_base->cnt);
272 /* set slave address */
273 writew(chip, &i2c_base->sa);
274 /* stop bit needed here */
275 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
278 status = wait_for_pin();
279 if (status == 0 || status & I2C_STAT_AL) {
283 if (status & I2C_STAT_NACK) {
285 writew(0xff, &i2c_base->stat);
286 writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
293 if (status & I2C_STAT_ARDY) {
294 writew(I2C_STAT_ARDY, &i2c_base->stat);
297 if (status & I2C_STAT_RRDY) {
299 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
300 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
301 defined(CONFIG_OMAP54XX)
302 readb(&i2c_base->data);
304 readw(&i2c_base->data);
306 writew(I2C_STAT_RRDY, &i2c_base->stat);
312 /* don't allow any more data in... we don't want it. */
313 writew(0, &i2c_base->cnt);
314 writew(0xFFFF, &i2c_base->stat);
318 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
323 printf("I2C read: addr len %d not supported\n", alen);
327 if (addr + len > (1 << 16)) {
328 puts("I2C read: address out of range\n");
332 for (i = 0; i < len; i++) {
333 if (i2c_read_byte(chip, addr + i, alen, &buffer[i])) {
334 puts("I2C read: I/O error\n");
335 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
343 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
349 u8 tmpbuf[2] = {addr >> 8, addr & 0xff};
352 printf("I2C write: addr len %d not supported\n", alen);
356 if (addr + len > (1 << 16)) {
357 printf("I2C write: address 0x%x + 0x%x out of range\n",
362 /* wait until bus not busy */
366 /* start address phase - will write regoffset + len bytes data */
367 /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
368 writew(alen + len, &i2c_base->cnt);
369 /* set slave address */
370 writew(chip, &i2c_base->sa);
371 /* stop bit needed here */
372 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
373 I2C_CON_STP, &i2c_base->con);
375 /* Send address and data */
376 for (i = -alen; i < len; i++) {
377 status = wait_for_pin();
379 if (status == 0 || status & I2C_STAT_NACK) {
381 printf("i2c error waiting for data ACK (status=0x%x)\n",
386 if (status & I2C_STAT_XRDY) {
387 w = (i < 0) ? tmpbuf[2+i] : buffer[i];
388 #if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
389 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
390 defined(CONFIG_OMAP54XX))
391 w |= ((++i < 0) ? tmpbuf[2+i] : buffer[i]) << 8;
393 writew(w, &i2c_base->data);
394 writew(I2C_STAT_XRDY, &i2c_base->stat);
397 printf("i2c bus not ready for Tx (i=%d)\n", i);
404 writew(0xFFFF, &i2c_base->stat);
408 static int wait_for_bb(void)
410 int timeout = I2C_TIMEOUT;
413 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
414 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
415 writew(stat, &i2c_base->stat);
420 printf("timed out in wait_for_bb: I2C_STAT=%x\n",
421 readw(&i2c_base->stat));
424 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
428 static u16 wait_for_pin(void)
431 int timeout = I2C_TIMEOUT;
435 status = readw(&i2c_base->stat);
437 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
438 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
439 I2C_STAT_AL)) && timeout--);
442 printf("timed out in wait_for_pin: I2C_STAT=%x\n",
443 readw(&i2c_base->stat));
444 writew(0xFFFF, &i2c_base->stat);
451 int i2c_set_bus_num(unsigned int bus)
453 if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
454 printf("Bad bus: %d\n", bus);
460 i2c_base = (struct i2c *)I2C_BASE4;
463 i2c_base = (struct i2c *)I2C_BASE3;
468 i2c_base = (struct i2c *)I2C_BASE3;
472 i2c_base = (struct i2c *)I2C_BASE2;
474 i2c_base = (struct i2c *)I2C_BASE1;
478 if (!bus_initialized[current_bus])
479 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
484 int i2c_get_bus_num(void)
486 return (int) current_bus;