4 * Copyright (c) 2004 Texas Instruments
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
25 #include <asm/arch/i2c.h>
28 #include "omap24xx_i2c.h"
30 #define I2C_TIMEOUT 10
32 static void wait_for_bb (void);
33 static u16 wait_for_pin (void);
34 static void flush_fifo(void);
36 static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
38 static unsigned int bus_initialized[I2C_BUS_MAX];
39 static unsigned int current_bus;
41 void i2c_init (int speed, int slaveadd)
43 int psc, fsscll, fssclh;
44 int hsscll = 0, hssclh = 0;
46 int timeout = I2C_TIMEOUT;
48 /* Only handle standard, fast and high speeds */
49 if ((speed != OMAP_I2C_STANDARD) &&
50 (speed != OMAP_I2C_FAST_MODE) &&
51 (speed != OMAP_I2C_HIGH_SPEED)) {
52 printf("Error : I2C unsupported speed %d\n", speed);
56 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
58 if (psc < I2C_PSC_MIN) {
59 printf("Error : I2C unsupported prescalar %d\n", psc);
63 if (speed == OMAP_I2C_HIGH_SPEED) {
66 /* For first phase of HS mode */
67 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
68 (2 * OMAP_I2C_FAST_MODE);
70 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
71 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
72 if (((fsscll < 0) || (fssclh < 0)) ||
73 ((fsscll > 255) || (fssclh > 255))) {
74 printf("Error : I2C initializing first phase clock\n");
78 /* For second phase of HS mode */
79 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
81 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
82 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
83 if (((fsscll < 0) || (fssclh < 0)) ||
84 ((fsscll > 255) || (fssclh > 255))) {
85 printf("Error : I2C initializing second phase clock\n");
89 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
90 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
93 /* Standard and fast speed */
94 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
96 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
97 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
98 if (((fsscll < 0) || (fssclh < 0)) ||
99 ((fsscll > 255) || (fssclh > 255))) {
100 printf("Error : I2C initializing clock\n");
104 scll = (unsigned int)fsscll;
105 sclh = (unsigned int)fssclh;
108 if (readw (&i2c_base->con) & I2C_CON_EN) {
109 writew (0, &i2c_base->con);
113 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
116 writew(I2C_CON_EN, &i2c_base->con);
117 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
119 printf("ERROR: Timeout in soft-reset\n");
125 writew(0, &i2c_base->con);
126 writew(psc, &i2c_base->psc);
127 writew(scll, &i2c_base->scll);
128 writew(sclh, &i2c_base->sclh);
131 writew (slaveadd, &i2c_base->oa);
132 writew (I2C_CON_EN, &i2c_base->con);
134 /* have to enable intrrupts or OMAP i2c module doesn't work */
135 writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
136 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
139 writew (0xFFFF, &i2c_base->stat);
140 writew (0, &i2c_base->cnt);
142 bus_initialized[current_bus] = 1;
145 static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
150 /* wait until bus not busy */
154 writew (1, &i2c_base->cnt);
155 /* set slave address */
156 writew (devaddr, &i2c_base->sa);
157 /* no stop bit needed here */
158 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
160 status = wait_for_pin ();
162 if (status & I2C_STAT_XRDY) {
163 /* Important: have to use byte access */
164 writeb (regoffset, &i2c_base->data);
166 if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
174 writew (I2C_CON_EN, &i2c_base->con);
175 while (readw(&i2c_base->stat) &
176 (I2C_STAT_XRDY | I2C_STAT_ARDY)) {
178 /* Have to clear pending interrupt to clear I2C_STAT */
179 writew (0xFFFF, &i2c_base->stat);
182 /* set slave address */
183 writew (devaddr, &i2c_base->sa);
184 /* read one byte from slave */
185 writew (1, &i2c_base->cnt);
186 /* need stop bit here */
187 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
190 status = wait_for_pin ();
191 if (status & I2C_STAT_RRDY) {
192 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
193 defined(CONFIG_OMAP44XX)
194 *value = readb (&i2c_base->data);
196 *value = readw (&i2c_base->data);
204 writew (I2C_CON_EN, &i2c_base->con);
205 while (readw (&i2c_base->stat) &
206 (I2C_STAT_RRDY | I2C_STAT_ARDY)) {
208 writew (0xFFFF, &i2c_base->stat);
213 writew (0xFFFF, &i2c_base->stat);
214 writew (0, &i2c_base->cnt);
218 static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
223 /* wait until bus not busy */
227 writew (2, &i2c_base->cnt);
228 /* set slave address */
229 writew (devaddr, &i2c_base->sa);
230 /* stop bit needed here */
231 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
232 I2C_CON_STP, &i2c_base->con);
234 /* wait until state change */
235 status = wait_for_pin ();
237 if (status & I2C_STAT_XRDY) {
238 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
239 defined(CONFIG_OMAP44XX)
240 /* send out 1 byte */
241 writeb (regoffset, &i2c_base->data);
242 writew (I2C_STAT_XRDY, &i2c_base->stat);
244 status = wait_for_pin ();
245 if ((status & I2C_STAT_XRDY)) {
246 /* send out next 1 byte */
247 writeb (value, &i2c_base->data);
248 writew (I2C_STAT_XRDY, &i2c_base->stat);
253 /* send out two bytes */
254 writew ((value << 8) + regoffset, &i2c_base->data);
256 /* must have enough delay to allow BB bit to go low */
258 if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
268 writew (I2C_CON_EN, &i2c_base->con);
269 while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) {
271 /* have to read to clear intrrupt */
272 writew (0xFFFF, &i2c_base->stat);
273 if(--eout == 0) /* better leave with error than hang */
278 writew (0xFFFF, &i2c_base->stat);
279 writew (0, &i2c_base->cnt);
283 static void flush_fifo(void)
286 /* note: if you try and read data when its not there or ready
287 * you get a bus error
290 stat = readw(&i2c_base->stat);
291 if(stat == I2C_STAT_RRDY){
292 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
293 defined(CONFIG_OMAP44XX)
294 readb(&i2c_base->data);
296 readw(&i2c_base->data);
298 writew(I2C_STAT_RRDY,&i2c_base->stat);
305 int i2c_probe (uchar chip)
307 int res = 1; /* default = fail */
309 if (chip == readw (&i2c_base->oa)) {
313 /* wait until bus not busy */
316 /* try to read one byte */
317 writew (1, &i2c_base->cnt);
318 /* set slave address */
319 writew (chip, &i2c_base->sa);
320 /* stop bit needed here */
321 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
322 /* enough delay for the NACK bit set */
325 if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
326 res = 0; /* success case */
328 writew(0xFFFF, &i2c_base->stat);
330 writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/
331 writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */
336 writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
337 writew(0xFFFF, &i2c_base->stat);
341 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
346 printf ("I2C read: addr len %d not supported\n", alen);
350 if (addr + len > 256) {
351 printf ("I2C read: address out of range\n");
355 for (i = 0; i < len; i++) {
356 if (i2c_read_byte (chip, addr + i, &buffer[i])) {
357 printf ("I2C read: I/O error\n");
358 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
366 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
371 printf ("I2C read: addr len %d not supported\n", alen);
375 if (addr + len > 256) {
376 printf ("I2C read: address out of range\n");
380 for (i = 0; i < len; i++) {
381 if (i2c_write_byte (chip, addr + i, buffer[i])) {
382 printf ("I2C read: I/O error\n");
383 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
391 static void wait_for_bb (void)
396 writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/
397 while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
398 writew (stat, &i2c_base->stat);
403 printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
404 readw (&i2c_base->stat));
406 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
409 static u16 wait_for_pin (void)
416 status = readw (&i2c_base->stat);
418 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
419 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
420 I2C_STAT_AL)) && timeout--);
423 printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
424 readw (&i2c_base->stat));
425 writew(0xFFFF, &i2c_base->stat);
430 int i2c_set_bus_num(unsigned int bus)
432 if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
433 printf("Bad bus: %d\n", bus);
439 i2c_base = (struct i2c *)I2C_BASE3;
443 i2c_base = (struct i2c *)I2C_BASE2;
445 i2c_base = (struct i2c *)I2C_BASE1;
449 if(!bus_initialized[current_bus])
450 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
455 int i2c_get_bus_num(void)
457 return (int) current_bus;