4 * Copyright (c) 2004 Texas Instruments
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
25 #include <asm/arch/i2c.h>
28 #include "omap24xx_i2c.h"
30 DECLARE_GLOBAL_DATA_PTR;
32 #define I2C_TIMEOUT 1000
34 static void wait_for_bb (void);
35 static u16 wait_for_pin (void);
36 static void flush_fifo(void);
38 static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
40 static unsigned int bus_initialized[I2C_BUS_MAX];
41 static unsigned int current_bus;
43 void i2c_init (int speed, int slaveadd)
45 int psc, fsscll, fssclh;
46 int hsscll = 0, hssclh = 0;
48 int timeout = I2C_TIMEOUT;
50 /* Only handle standard, fast and high speeds */
51 if ((speed != OMAP_I2C_STANDARD) &&
52 (speed != OMAP_I2C_FAST_MODE) &&
53 (speed != OMAP_I2C_HIGH_SPEED)) {
54 printf("Error : I2C unsupported speed %d\n", speed);
58 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
60 if (psc < I2C_PSC_MIN) {
61 printf("Error : I2C unsupported prescalar %d\n", psc);
65 if (speed == OMAP_I2C_HIGH_SPEED) {
68 /* For first phase of HS mode */
69 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
70 (2 * OMAP_I2C_FAST_MODE);
72 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
73 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
74 if (((fsscll < 0) || (fssclh < 0)) ||
75 ((fsscll > 255) || (fssclh > 255))) {
76 printf("Error : I2C initializing first phase clock\n");
80 /* For second phase of HS mode */
81 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
83 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
84 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
85 if (((fsscll < 0) || (fssclh < 0)) ||
86 ((fsscll > 255) || (fssclh > 255))) {
87 printf("Error : I2C initializing second phase clock\n");
91 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
92 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
95 /* Standard and fast speed */
96 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
98 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
99 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
100 if (((fsscll < 0) || (fssclh < 0)) ||
101 ((fsscll > 255) || (fssclh > 255))) {
102 printf("Error : I2C initializing clock\n");
106 scll = (unsigned int)fsscll;
107 sclh = (unsigned int)fssclh;
110 if (readw (&i2c_base->con) & I2C_CON_EN) {
111 writew (0, &i2c_base->con);
115 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
118 writew(I2C_CON_EN, &i2c_base->con);
119 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
121 printf("ERROR: Timeout in soft-reset\n");
127 writew(0, &i2c_base->con);
128 writew(psc, &i2c_base->psc);
129 writew(scll, &i2c_base->scll);
130 writew(sclh, &i2c_base->sclh);
133 writew (slaveadd, &i2c_base->oa);
134 writew (I2C_CON_EN, &i2c_base->con);
136 /* have to enable intrrupts or OMAP i2c module doesn't work */
137 writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
138 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
141 writew (0xFFFF, &i2c_base->stat);
142 writew (0, &i2c_base->cnt);
144 if (gd->flags & GD_FLG_RELOC)
145 bus_initialized[current_bus] = 1;
148 static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
153 /* wait until bus not busy */
157 writew (1, &i2c_base->cnt);
158 /* set slave address */
159 writew (devaddr, &i2c_base->sa);
160 /* no stop bit needed here */
161 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
163 /* send register offset */
165 status = wait_for_pin();
166 if (status == 0 || status & I2C_STAT_NACK) {
170 if (status & I2C_STAT_XRDY) {
171 /* Important: have to use byte access */
172 writeb(regoffset, &i2c_base->data);
173 writew(I2C_STAT_XRDY, &i2c_base->stat);
175 if (status & I2C_STAT_ARDY) {
176 writew(I2C_STAT_ARDY, &i2c_base->stat);
181 /* set slave address */
182 writew(devaddr, &i2c_base->sa);
183 /* read one byte from slave */
184 writew(1, &i2c_base->cnt);
185 /* need stop bit here */
186 writew(I2C_CON_EN | I2C_CON_MST |
187 I2C_CON_STT | I2C_CON_STP,
192 status = wait_for_pin();
193 if (status == 0 || status & I2C_STAT_NACK) {
197 if (status & I2C_STAT_RRDY) {
198 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
199 defined(CONFIG_OMAP44XX)
200 *value = readb(&i2c_base->data);
202 *value = readw(&i2c_base->data);
204 writew(I2C_STAT_RRDY, &i2c_base->stat);
206 if (status & I2C_STAT_ARDY) {
207 writew(I2C_STAT_ARDY, &i2c_base->stat);
214 writew (0xFFFF, &i2c_base->stat);
215 writew (0, &i2c_base->cnt);
219 static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
224 /* wait until bus not busy */
228 writew (2, &i2c_base->cnt);
229 /* set slave address */
230 writew (devaddr, &i2c_base->sa);
231 /* stop bit needed here */
232 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
233 I2C_CON_STP, &i2c_base->con);
236 status = wait_for_pin();
237 if (status == 0 || status & I2C_STAT_NACK) {
241 if (status & I2C_STAT_XRDY) {
242 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
243 defined(CONFIG_OMAP44XX)
244 /* send register offset */
245 writeb(regoffset, &i2c_base->data);
246 writew(I2C_STAT_XRDY, &i2c_base->stat);
249 status = wait_for_pin();
250 if (status == 0 || status & I2C_STAT_NACK) {
254 if (status & I2C_STAT_XRDY) {
256 writeb(value, &i2c_base->data);
257 writew(I2C_STAT_XRDY, &i2c_base->stat);
259 if (status & I2C_STAT_ARDY) {
260 writew(I2C_STAT_ARDY, &i2c_base->stat);
266 /* send out two bytes */
267 writew((value << 8) + regoffset, &i2c_base->data);
268 writew(I2C_STAT_XRDY, &i2c_base->stat);
271 if (status & I2C_STAT_ARDY) {
272 writew(I2C_STAT_ARDY, &i2c_base->stat);
279 status = readw(&i2c_base->stat);
280 if (status & I2C_STAT_NACK)
285 writew (0xFFFF, &i2c_base->stat);
286 writew (0, &i2c_base->cnt);
290 static void flush_fifo(void)
293 /* note: if you try and read data when its not there or ready
294 * you get a bus error
297 stat = readw(&i2c_base->stat);
298 if(stat == I2C_STAT_RRDY){
299 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
300 defined(CONFIG_OMAP44XX)
301 readb(&i2c_base->data);
303 readw(&i2c_base->data);
305 writew(I2C_STAT_RRDY,&i2c_base->stat);
312 int i2c_probe (uchar chip)
315 int res = 1; /* default = fail */
317 if (chip == readw (&i2c_base->oa)) {
321 /* wait until bus not busy */
324 /* try to write one byte */
325 writew (1, &i2c_base->cnt);
326 /* set slave address */
327 writew (chip, &i2c_base->sa);
328 /* stop bit needed here */
329 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
330 I2C_CON_STP, &i2c_base->con);
332 status = wait_for_pin();
334 /* check for ACK (!NAK) */
335 if (!(status & I2C_STAT_NACK))
338 /* abort transfer (force idle state) */
339 writew(0, &i2c_base->con);
342 writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
343 writew(0xFFFF, &i2c_base->stat);
347 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
352 printf ("I2C read: addr len %d not supported\n", alen);
356 if (addr + len > 256) {
357 printf ("I2C read: address out of range\n");
361 for (i = 0; i < len; i++) {
362 if (i2c_read_byte (chip, addr + i, &buffer[i])) {
363 printf ("I2C read: I/O error\n");
364 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
372 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
377 printf ("I2C read: addr len %d not supported\n", alen);
381 if (addr + len > 256) {
382 printf ("I2C read: address out of range\n");
386 for (i = 0; i < len; i++) {
387 if (i2c_write_byte (chip, addr + i, buffer[i])) {
388 printf ("I2C read: I/O error\n");
389 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
397 static void wait_for_bb (void)
399 int timeout = I2C_TIMEOUT;
402 writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/
403 while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
404 writew (stat, &i2c_base->stat);
409 printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
410 readw (&i2c_base->stat));
412 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
415 static u16 wait_for_pin (void)
418 int timeout = I2C_TIMEOUT;
422 status = readw (&i2c_base->stat);
424 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
425 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
426 I2C_STAT_AL)) && timeout--);
429 printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
430 readw (&i2c_base->stat));
431 writew(0xFFFF, &i2c_base->stat);
438 int i2c_set_bus_num(unsigned int bus)
440 if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
441 printf("Bad bus: %d\n", bus);
447 i2c_base = (struct i2c *)I2C_BASE3;
451 i2c_base = (struct i2c *)I2C_BASE2;
453 i2c_base = (struct i2c *)I2C_BASE1;
457 if(!bus_initialized[current_bus])
458 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
463 int i2c_get_bus_num(void)
465 return (int) current_bus;