4 * Copyright (c) 2004 Texas Instruments
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
25 #include <asm/arch/i2c.h>
28 #include "omap24xx_i2c.h"
30 DECLARE_GLOBAL_DATA_PTR;
32 #define I2C_TIMEOUT 1000
34 static void wait_for_bb(void);
35 static u16 wait_for_pin(void);
36 static void flush_fifo(void);
39 * For SPL boot some boards need i2c before SDRAM is initialised so force
40 * variables to live in SRAM
42 static struct i2c __attribute__((section (".data"))) *i2c_base =
43 (struct i2c *)I2C_DEFAULT_BASE;
44 static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
45 { [0 ... (I2C_BUS_MAX-1)] = 0 };
46 static unsigned int __attribute__((section (".data"))) current_bus = 0;
48 void i2c_init(int speed, int slaveadd)
50 int psc, fsscll, fssclh;
51 int hsscll = 0, hssclh = 0;
53 int timeout = I2C_TIMEOUT;
55 /* Only handle standard, fast and high speeds */
56 if ((speed != OMAP_I2C_STANDARD) &&
57 (speed != OMAP_I2C_FAST_MODE) &&
58 (speed != OMAP_I2C_HIGH_SPEED)) {
59 printf("Error : I2C unsupported speed %d\n", speed);
63 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
65 if (psc < I2C_PSC_MIN) {
66 printf("Error : I2C unsupported prescalar %d\n", psc);
70 if (speed == OMAP_I2C_HIGH_SPEED) {
73 /* For first phase of HS mode */
74 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
75 (2 * OMAP_I2C_FAST_MODE);
77 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
78 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
79 if (((fsscll < 0) || (fssclh < 0)) ||
80 ((fsscll > 255) || (fssclh > 255))) {
81 puts("Error : I2C initializing first phase clock\n");
85 /* For second phase of HS mode */
86 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
88 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
89 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
90 if (((fsscll < 0) || (fssclh < 0)) ||
91 ((fsscll > 255) || (fssclh > 255))) {
92 puts("Error : I2C initializing second phase clock\n");
96 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
97 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
100 /* Standard and fast speed */
101 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
103 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
104 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
105 if (((fsscll < 0) || (fssclh < 0)) ||
106 ((fsscll > 255) || (fssclh > 255))) {
107 puts("Error : I2C initializing clock\n");
111 scll = (unsigned int)fsscll;
112 sclh = (unsigned int)fssclh;
115 if (readw(&i2c_base->con) & I2C_CON_EN) {
116 writew(0, &i2c_base->con);
120 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
123 writew(I2C_CON_EN, &i2c_base->con);
124 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
126 puts("ERROR: Timeout in soft-reset\n");
132 writew(0, &i2c_base->con);
133 writew(psc, &i2c_base->psc);
134 writew(scll, &i2c_base->scll);
135 writew(sclh, &i2c_base->sclh);
138 writew(slaveadd, &i2c_base->oa);
139 writew(I2C_CON_EN, &i2c_base->con);
141 /* have to enable intrrupts or OMAP i2c module doesn't work */
142 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
143 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
146 writew(0xFFFF, &i2c_base->stat);
147 writew(0, &i2c_base->cnt);
149 if (gd->flags & GD_FLG_RELOC)
150 bus_initialized[current_bus] = 1;
153 static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
158 /* wait until bus not busy */
162 writew(1, &i2c_base->cnt);
163 /* set slave address */
164 writew(devaddr, &i2c_base->sa);
165 /* no stop bit needed here */
166 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
167 I2C_CON_TRX, &i2c_base->con);
169 /* send register offset */
171 status = wait_for_pin();
172 if (status == 0 || status & I2C_STAT_NACK) {
176 if (status & I2C_STAT_XRDY) {
177 /* Important: have to use byte access */
178 writeb(regoffset, &i2c_base->data);
179 writew(I2C_STAT_XRDY, &i2c_base->stat);
181 if (status & I2C_STAT_ARDY) {
182 writew(I2C_STAT_ARDY, &i2c_base->stat);
187 /* set slave address */
188 writew(devaddr, &i2c_base->sa);
189 /* read one byte from slave */
190 writew(1, &i2c_base->cnt);
191 /* need stop bit here */
192 writew(I2C_CON_EN | I2C_CON_MST |
193 I2C_CON_STT | I2C_CON_STP,
198 status = wait_for_pin();
199 if (status == 0 || status & I2C_STAT_NACK) {
203 if (status & I2C_STAT_RRDY) {
204 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
205 defined(CONFIG_OMAP44XX)
206 *value = readb(&i2c_base->data);
208 *value = readw(&i2c_base->data);
210 writew(I2C_STAT_RRDY, &i2c_base->stat);
212 if (status & I2C_STAT_ARDY) {
213 writew(I2C_STAT_ARDY, &i2c_base->stat);
220 writew(0xFFFF, &i2c_base->stat);
221 writew(0, &i2c_base->cnt);
225 static void flush_fifo(void)
228 /* note: if you try and read data when its not there or ready
229 * you get a bus error
232 stat = readw(&i2c_base->stat);
233 if (stat == I2C_STAT_RRDY) {
234 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
235 defined(CONFIG_OMAP44XX)
236 readb(&i2c_base->data);
238 readw(&i2c_base->data);
240 writew(I2C_STAT_RRDY, &i2c_base->stat);
247 int i2c_probe(uchar chip)
250 int res = 1; /* default = fail */
252 if (chip == readw(&i2c_base->oa))
255 /* wait until bus not busy */
258 /* try to read one byte */
259 writew(1, &i2c_base->cnt);
260 /* set slave address */
261 writew(chip, &i2c_base->sa);
262 /* stop bit needed here */
263 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
266 status = wait_for_pin();
267 if (status == 0 || status & I2C_STAT_AL) {
271 if (status & I2C_STAT_NACK) {
273 writew(0xff, &i2c_base->stat);
274 writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
278 if (status & I2C_STAT_ARDY) {
279 writew(I2C_STAT_ARDY, &i2c_base->stat);
282 if (status & I2C_STAT_RRDY) {
284 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
285 defined(CONFIG_OMAP44XX)
286 readb(&i2c_base->data);
288 readw(&i2c_base->data);
290 writew(I2C_STAT_RRDY, &i2c_base->stat);
296 /* don't allow any more data in... we don't want it. */
297 writew(0, &i2c_base->cnt);
298 writew(0xFFFF, &i2c_base->stat);
302 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
307 printf("I2C read: addr len %d not supported\n", alen);
311 if (addr + len > 256) {
312 puts("I2C read: address out of range\n");
316 for (i = 0; i < len; i++) {
317 if (i2c_read_byte(chip, addr + i, &buffer[i])) {
318 puts("I2C read: I/O error\n");
319 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
327 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
334 printf("I2C write: addr len %d not supported\n", alen);
338 if (addr + len > 256) {
339 printf("I2C write: address 0x%x + 0x%x out of range\n",
344 /* wait until bus not busy */
347 /* start address phase - will write regoffset + len bytes data */
348 /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
349 writew(alen + len, &i2c_base->cnt);
350 /* set slave address */
351 writew(chip, &i2c_base->sa);
352 /* stop bit needed here */
353 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
354 I2C_CON_STP, &i2c_base->con);
356 /* Send address byte */
357 status = wait_for_pin();
359 if (status == 0 || status & I2C_STAT_NACK) {
361 printf("error waiting for i2c address ACK (status=0x%x)\n",
366 if (status & I2C_STAT_XRDY) {
367 writeb(addr & 0xFF, &i2c_base->data);
368 writew(I2C_STAT_XRDY, &i2c_base->stat);
371 printf("i2c bus not ready for transmit (status=0x%x)\n",
376 /* address phase is over, now write data */
377 for (i = 0; i < len; i++) {
378 status = wait_for_pin();
380 if (status == 0 || status & I2C_STAT_NACK) {
382 printf("i2c error waiting for data ACK (status=0x%x)\n",
387 if (status & I2C_STAT_XRDY) {
388 writeb(buffer[i], &i2c_base->data);
389 writew(I2C_STAT_XRDY, &i2c_base->stat);
392 printf("i2c bus not ready for Tx (i=%d)\n", i);
399 writew(0xFFFF, &i2c_base->stat);
403 static void wait_for_bb(void)
405 int timeout = I2C_TIMEOUT;
408 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
409 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
410 writew(stat, &i2c_base->stat);
415 printf("timed out in wait_for_bb: I2C_STAT=%x\n",
416 readw(&i2c_base->stat));
418 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
421 static u16 wait_for_pin(void)
424 int timeout = I2C_TIMEOUT;
428 status = readw(&i2c_base->stat);
430 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
431 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
432 I2C_STAT_AL)) && timeout--);
435 printf("timed out in wait_for_pin: I2C_STAT=%x\n",
436 readw(&i2c_base->stat));
437 writew(0xFFFF, &i2c_base->stat);
444 int i2c_set_bus_num(unsigned int bus)
446 if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
447 printf("Bad bus: %d\n", bus);
453 i2c_base = (struct i2c *)I2C_BASE3;
457 i2c_base = (struct i2c *)I2C_BASE2;
459 i2c_base = (struct i2c *)I2C_BASE1;
463 if (!bus_initialized[current_bus])
464 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
469 int i2c_get_bus_num(void)
471 return (int) current_bus;