drivers/i2c/ocores_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * ocores-i2c.c: I2C bus driver for OpenCores I2C controller
   4  * (https://opencores.org/projects/i2c)
   5  *
   6  * (C) Copyright Peter Korsgaard <peter@korsgaard.com>
   7  *
   8  * Copyright (C) 2020 SiFive, Inc.
   9  * Pragnesh Patel <pragnesh.patel@sifive.com>
  10  *
  11  * Support for the GRLIB port of the controller by
  12  * Andreas Larsson <andreas@gaisler.com>
  13  */
  14
  15 #include <common.h>
  16 #include <asm/global_data.h>
  17 #include <asm/io.h>
  18 #include <clk.h>
  19 #include <dm.h>
  20 #include <dm/device_compat.h>
  21 #include <i2c.h>
  22 #include <linux/io.h>
  23 #include <linux/compat.h>
  24 #include <linux/log2.h>
  25 #include <linux/delay.h>
  26
  27 /* registers */
  28 #define OCI2C_PRELOW            0
  29 #define OCI2C_PREHIGH           1
  30 #define OCI2C_CONTROL           2
  31 #define OCI2C_DATA              3
  32 #define OCI2C_CMD               4 /* write only */
  33 #define OCI2C_STATUS            4 /* read only, same address as OCI2C_CMD */
  34
  35 #define OCI2C_CTRL_IEN          0x40
  36 #define OCI2C_CTRL_EN           0x80
  37
  38 #define OCI2C_CMD_START         0x91
  39 #define OCI2C_CMD_STOP          0x41
  40 #define OCI2C_CMD_READ          0x21
  41 #define OCI2C_CMD_WRITE         0x11
  42 #define OCI2C_CMD_READ_ACK      0x21
  43 #define OCI2C_CMD_READ_NACK     0x29
  44 #define OCI2C_CMD_IACK          0x01
  45
  46 #define OCI2C_STAT_IF           0x01
  47 #define OCI2C_STAT_TIP          0x02
  48 #define OCI2C_STAT_ARBLOST      0x20
  49 #define OCI2C_STAT_BUSY         0x40
  50 #define OCI2C_STAT_NACK         0x80
  51
  52 #define STATE_DONE              0
  53 #define STATE_START             1
  54 #define STATE_WRITE             2
  55 #define STATE_READ              3
  56 #define STATE_ERROR             4
  57
  58 #define TYPE_OCORES             0
  59 #define TYPE_GRLIB              1
  60
  61 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
  62
  63 struct ocores_i2c_bus {
  64         void __iomem *base;
  65         u32 reg_shift;
  66         u32 reg_io_width;
  67         unsigned long flags;
  68         struct i2c_msg *msg;
  69         int pos;
  70         int nmsgs;
  71         int state; /* see STATE_ */
  72         struct clk clk;
  73         int ip_clk_khz;
  74         int bus_clk_khz;
  75         void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value);
  76         u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg);
  77 };
  78
  79 DECLARE_GLOBAL_DATA_PTR;
  80
  81 /* Boolean attribute values */
  82 enum {
  83         FALSE = 0,
  84         TRUE,
  85 };
  86
  87 static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value)
  88 {
  89         writeb(value, i2c->base + (reg << i2c->reg_shift));
  90 }
  91
  92 static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value)
  93 {
  94         writew(value, i2c->base + (reg << i2c->reg_shift));
  95 }
  96
  97 static void oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value)
  98 {
  99         writel(value, i2c->base + (reg << i2c->reg_shift));
 100 }
 101
 102 static void oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value)
 103 {
 104         out_be16(i2c->base + (reg << i2c->reg_shift), value);
 105 }
 106
 107 static void oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value)
 108 {
 109         out_be32(i2c->base + (reg << i2c->reg_shift), value);
 110 }
 111
 112 static inline u8 oc_getreg_8(struct ocores_i2c_bus *i2c, int reg)
 113 {
 114         return readb(i2c->base + (reg << i2c->reg_shift));
 115 }
 116
 117 static inline u8 oc_getreg_16(struct ocores_i2c_bus *i2c, int reg)
 118 {
 119         return readw(i2c->base + (reg << i2c->reg_shift));
 120 }
 121
 122 static inline u8 oc_getreg_32(struct ocores_i2c_bus *i2c, int reg)
 123 {
 124         return readl(i2c->base + (reg << i2c->reg_shift));
 125 }
 126
 127 static inline u8 oc_getreg_16be(struct ocores_i2c_bus *i2c, int reg)
 128 {
 129         return in_be16(i2c->base + (reg << i2c->reg_shift));
 130 }
 131
 132 static inline u8 oc_getreg_32be(struct ocores_i2c_bus *i2c, int reg)
 133 {
 134         return in_be32(i2c->base + (reg << i2c->reg_shift));
 135 }
 136
 137 static inline void oc_setreg(struct ocores_i2c_bus *i2c, int reg, u8 value)
 138 {
 139         i2c->setreg(i2c, reg, value);
 140 }
 141
 142 static inline u8 oc_getreg(struct ocores_i2c_bus *i2c, int reg)
 143 {
 144         return i2c->getreg(i2c, reg);
 145 }
 146
 147 static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
 148 {
 149         return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
 150 }
 151
 152 static void ocores_process(struct ocores_i2c_bus *i2c, u8 stat)
 153 {
 154         struct i2c_msg *msg = i2c->msg;
 155
 156         if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
 157                 /* stop has been sent */
 158                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 159                 return;
 160         }
 161
 162         /* error? */
 163         if (stat & OCI2C_STAT_ARBLOST) {
 164                 i2c->state = STATE_ERROR;
 165                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 166                 return;
 167         }
 168
 169         if (i2c->state == STATE_START || i2c->state == STATE_WRITE) {
 170                 i2c->state =
 171                         (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
 172
 173                 if (stat & OCI2C_STAT_NACK) {
 174                         i2c->state = STATE_ERROR;
 175                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 176                         return;
 177                 }
 178         } else {
 179                 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
 180         }
 181
 182         /* end of msg? */
 183         if (i2c->pos == msg->len) {
 184                 i2c->nmsgs--;
 185                 i2c->msg++;
 186                 i2c->pos = 0;
 187                 msg = i2c->msg;
 188
 189                 if (i2c->nmsgs) {       /* end? */
 190                         /* send start? */
 191                         if (!(msg->flags & I2C_M_NOSTART)) {
 192                                 u8 addr = i2c_8bit_addr_from_msg(msg);
 193
 194                                 i2c->state = STATE_START;
 195
 196                                 oc_setreg(i2c, OCI2C_DATA, addr);
 197                                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
 198                                 return;
 199                         }
 200                         i2c->state = (msg->flags & I2C_M_RD)
 201                                 ? STATE_READ : STATE_WRITE;
 202                 } else {
 203                         i2c->state = STATE_DONE;
 204                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 205                         return;
 206                 }
 207         }
 208
 209         if (i2c->state == STATE_READ) {
 210                 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len - 1) ?
 211                                 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
 212         } else {
 213                 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
 214                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
 215         }
 216 }
 217
 218 static irqreturn_t ocores_isr(int irq, void *dev_id)
 219 {
 220         struct ocores_i2c_bus *i2c = dev_id;
 221         u8 stat = oc_getreg(i2c, OCI2C_STATUS);
 222
 223         if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
 224                 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
 225                         return IRQ_NONE;
 226         } else if (!(stat & OCI2C_STAT_IF)) {
 227                 return IRQ_NONE;
 228         }
 229         ocores_process(i2c, stat);
 230
 231         return IRQ_HANDLED;
 232 }
 233
 234 /**
 235  * Wait until something change in a given register
 236  * @i2c: ocores I2C device instance
 237  * @reg: register to query
 238  * @mask: bitmask to apply on register value
 239  * @val: expected result
 240  * @msec: timeout in msec
 241  *
 242  * Timeout is necessary to avoid to stay here forever when the chip
 243  * does not answer correctly.
 244  *
 245  * Return: 0 on success, -ETIMEDOUT on timeout
 246  */
 247 static int ocores_wait(struct ocores_i2c_bus *i2c,
 248                        int reg, u8 mask, u8 val,
 249                        const unsigned long msec)
 250 {
 251         u32 count = 0;
 252
 253         while (1) {
 254                 u8 status = oc_getreg(i2c, reg);
 255
 256                 if ((status & mask) == val)
 257                         break;
 258
 259                 udelay(1);
 260                 count += 1;
 261
 262                 if (count == (1000 * msec))
 263                         return -ETIMEDOUT;
 264         }
 265         return 0;
 266 }
 267
 268 /**
 269  * Wait until is possible to process some data
 270  * @i2c: ocores I2C device instance
 271  *
 272  * Used when the device is in polling mode (interrupts disabled).
 273  *
 274  * Return: 0 on success, -ETIMEDOUT on timeout
 275  */
 276 static int ocores_poll_wait(struct ocores_i2c_bus *i2c)
 277 {
 278         u8 mask;
 279         int err;
 280
 281         if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
 282                 /* transfer is over */
 283                 mask = OCI2C_STAT_BUSY;
 284         } else {
 285                 /* on going transfer */
 286                 mask = OCI2C_STAT_TIP;
 287                 /*
 288                  * We wait for the data to be transferred (8bit),
 289                  * then we start polling on the ACK/NACK bit
 290                  */
 291                 udelay((8 * 1000) / i2c->bus_clk_khz);
 292         }
 293
 294         /*
 295          * once we are here we expect to get the expected result immediately
 296          * so if after 1ms we timeout then something is broken.
 297          */
 298         err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, 1);
 299         if (err)
 300                 debug("%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
 301                       __func__, mask);
 302         return err;
 303 }
 304
 305 /**
 306  * It handles an IRQ-less transfer
 307  * @i2c: ocores I2C device instance
 308  *
 309  * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
 310  * (only that IRQ are not produced). This means that we can re-use entirely
 311  * ocores_isr(), we just add our polling code around it.
 312  *
 313  * It can run in atomic context
 314  */
 315 static void ocores_process_polling(struct ocores_i2c_bus *i2c)
 316 {
 317         while (1) {
 318                 irqreturn_t ret;
 319                 int err;
 320
 321                 err = ocores_poll_wait(i2c);
 322                 if (err) {
 323                         i2c->state = STATE_ERROR;
 324                         break; /* timeout */
 325                 }
 326
 327                 ret = ocores_isr(-1, i2c);
 328                 if (ret == IRQ_NONE) {
 329                         break; /* all messages have been transferred */
 330                 } else {
 331                         if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
 332                                 if (i2c->state == STATE_DONE)
 333                                         break;
 334                 }
 335         }
 336 }
 337
 338 static int ocores_xfer_core(struct ocores_i2c_bus *i2c,
 339                             struct i2c_msg *msgs, int num, bool polling)
 340 {
 341         u8 ctrl;
 342
 343         ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 344
 345         if (polling)
 346                 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
 347
 348         i2c->msg = msgs;
 349         i2c->pos = 0;
 350         i2c->nmsgs = num;
 351         i2c->state = STATE_START;
 352
 353         oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
 354         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
 355
 356         if (polling)
 357                 ocores_process_polling(i2c);
 358
 359         return (i2c->state == STATE_DONE) ? num : -EIO;
 360 }
 361
 362 static int ocores_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
 363 {
 364         struct ocores_i2c_bus *bus = dev_get_priv(dev);
 365         int ret;
 366
 367         debug("i2c_xfer: %d messages\n", nmsgs);
 368
 369         ret = ocores_xfer_core(bus, msg, nmsgs, 1);
 370
 371         if (ret != nmsgs) {
 372                 debug("i2c_write: error sending\n");
 373                 return -EREMOTEIO;
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int ocores_i2c_enable_clk(struct udevice *dev)
 380 {
 381         struct ocores_i2c_bus *bus = dev_get_priv(dev);
 382         ulong clk_rate;
 383         int ret;
 384
 385         ret = clk_get_by_index(dev, 0, &bus->clk);
 386         if (ret)
 387                 return -EINVAL;
 388
 389         ret = clk_enable(&bus->clk);
 390         if (ret)
 391                 return ret;
 392
 393         clk_rate = clk_get_rate(&bus->clk);
 394         if (!clk_rate)
 395                 return -EINVAL;
 396
 397         bus->ip_clk_khz = clk_rate / 1000;
 398
 399         clk_free(&bus->clk);
 400
 401         return 0;
 402 }
 403
 404 static int ocores_init(struct udevice *dev, struct ocores_i2c_bus *bus)
 405 {
 406         int prescale;
 407         int diff;
 408         u8 ctrl = oc_getreg(bus, OCI2C_CONTROL);
 409
 410         /* make sure the device is disabled */
 411         ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
 412         oc_setreg(bus, OCI2C_CONTROL, ctrl);
 413
 414         prescale = (bus->ip_clk_khz / (5 * bus->bus_clk_khz)) - 1;
 415         prescale = clamp(prescale, 0, 0xffff);
 416
 417         diff = bus->ip_clk_khz / (5 * (prescale + 1)) - bus->bus_clk_khz;
 418         if (abs(diff) > bus->bus_clk_khz / 10) {
 419                 debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
 420                       bus->ip_clk_khz, bus->bus_clk_khz);
 421                 return -EINVAL;
 422         }
 423
 424         oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff);
 425         oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8);
 426
 427         /* Init the device */
 428         oc_setreg(bus, OCI2C_CMD, OCI2C_CMD_IACK);
 429         oc_setreg(bus, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
 430
 431         return 0;
 432 }
 433
 434 /*
 435  * Read and write functions for the GRLIB port of the controller. Registers are
 436  * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
 437  * register. The subsequent registers have their offsets decreased accordingly.
 438  */
 439 static u8 oc_getreg_grlib(struct ocores_i2c_bus *i2c, int reg)
 440 {
 441         u32 rd;
 442         int rreg = reg;
 443
 444         if (reg != OCI2C_PRELOW)
 445                 rreg--;
 446         rd = in_be32(i2c->base + (rreg << i2c->reg_shift));
 447         if (reg == OCI2C_PREHIGH)
 448                 return (u8)(rd >> 8);
 449         else
 450                 return (u8)rd;
 451 }
 452
 453 static void oc_setreg_grlib(struct ocores_i2c_bus *i2c, int reg, u8 value)
 454 {
 455         u32 curr, wr;
 456         int rreg = reg;
 457
 458         if (reg != OCI2C_PRELOW)
 459                 rreg--;
 460         if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
 461                 curr = in_be32(i2c->base + (rreg << i2c->reg_shift));
 462                 if (reg == OCI2C_PRELOW)
 463                         wr = (curr & 0xff00) | value;
 464                 else
 465                         wr = (((u32)value) << 8) | (curr & 0xff);
 466         } else {
 467                 wr = value;
 468         }
 469         out_be32(i2c->base + (rreg << i2c->reg_shift), wr);
 470 }
 471
 472 static int ocores_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 473 {
 474         int prescale;
 475         int diff;
 476         struct ocores_i2c_bus *bus = dev_get_priv(dev);
 477
 478         /* speed in Khz */
 479         speed = speed / 1000;
 480
 481         prescale = (bus->ip_clk_khz / (5 * speed)) - 1;
 482         prescale = clamp(prescale, 0, 0xffff);
 483
 484         diff = bus->ip_clk_khz / (5 * (prescale + 1)) - speed;
 485         if (abs(diff) > speed / 10) {
 486                 debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
 487                       bus->ip_clk_khz, speed);
 488                 return -EINVAL;
 489         }
 490
 491         oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff);
 492         oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8);
 493
 494         bus->bus_clk_khz = speed;
 495         return 0;
 496 }
 497
 498 int ocores_i2c_get_bus_speed(struct udevice *dev)
 499 {
 500         struct ocores_i2c_bus *bus = dev_get_priv(dev);
 501
 502         return (bus->bus_clk_khz * 1000);
 503 }
 504
 505 static const struct dm_i2c_ops ocores_i2c_ops = {
 506         .xfer           = ocores_i2c_xfer,
 507         .set_bus_speed  = ocores_i2c_set_bus_speed,
 508         .get_bus_speed  = ocores_i2c_get_bus_speed,
 509 };
 510
 511 static int ocores_i2c_probe(struct udevice *dev)
 512 {
 513         struct ocores_i2c_bus *bus = dev_get_priv(dev);
 514         bool clock_frequency_present;
 515         u32 val;
 516         u32 clock_frequency_khz;
 517         int ret;
 518
 519         bus->base = dev_read_addr_ptr(dev);
 520
 521         if (dev_read_u32(dev, "reg-shift", &bus->reg_shift)) {
 522                 /* no 'reg-shift', check for deprecated 'regstep' */
 523                 ret = dev_read_u32(dev, "regstep", &val);
 524                 if (ret) {
 525                         dev_err(dev,
 526                                 "missing both reg-shift and regstep property: %d\n", ret);
 527                         return -EINVAL;
 528                 } else {
 529                         bus->reg_shift = ilog2(val);
 530                         dev_warn(dev,
 531                                  "regstep property deprecated, use reg-shift\n");
 532                 }
 533         }
 534
 535         if (dev_read_u32(dev, "clock-frequency", &val)) {
 536                 bus->bus_clk_khz = 100;
 537                 clock_frequency_present = FALSE;
 538         } else {
 539                 bus->bus_clk_khz = val / 1000;
 540                 clock_frequency_khz = val / 1000;
 541                 clock_frequency_present = TRUE;
 542         }
 543
 544         ret = ocores_i2c_enable_clk(dev);
 545         if (ret)
 546                 return ret;
 547
 548         if (bus->ip_clk_khz == 0) {
 549                 if (dev_read_u32(dev, "opencores,ip-clock-frequency", &val)) {
 550                         if (!clock_frequency_present) {
 551                                 dev_err(dev,
 552                                         "Missing required parameter 'opencores,ip-clock-frequency'\n");
 553                                 clk_disable(&bus->clk);
 554                                 return -ENODEV;
 555                         }
 556
 557                         bus->ip_clk_khz = clock_frequency_khz;
 558                         dev_warn(dev,
 559                                  "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
 560                 } else {
 561                         bus->ip_clk_khz = val / 1000;
 562                         if (clock_frequency_present)
 563                                 bus->bus_clk_khz = clock_frequency_khz;
 564                 }
 565         }
 566
 567         bus->reg_io_width = dev_read_u32_default(dev, "reg-io-width", 1);
 568
 569         if (dev_get_driver_data(dev) == TYPE_GRLIB) {
 570                 debug("GRLIB variant of i2c-ocores\n");
 571                 bus->setreg = oc_setreg_grlib;
 572                 bus->getreg = oc_getreg_grlib;
 573         }
 574
 575         if (!bus->setreg || !bus->getreg) {
 576                 bool be = (cpu_to_be32(0x12345678) == 0x12345678);
 577
 578                 switch (bus->reg_io_width) {
 579                 case 1:
 580                         bus->setreg = oc_setreg_8;
 581                         bus->getreg = oc_getreg_8;
 582                         break;
 583
 584                 case 2:
 585                         bus->setreg = be ? oc_setreg_16be : oc_setreg_16;
 586                         bus->getreg = be ? oc_getreg_16be : oc_getreg_16;
 587                         break;
 588
 589                 case 4:
 590                         bus->setreg = be ? oc_setreg_32be : oc_setreg_32;
 591                         bus->getreg = be ? oc_getreg_32be : oc_getreg_32;
 592                         break;
 593
 594                 default:
 595                         debug("Unsupported I/O width (%d)\n",
 596                               bus->reg_io_width);
 597                         ret = -EINVAL;
 598                         goto err_clk;
 599                 }
 600         }
 601
 602         /*
 603          * Set OCORES_FLAG_BROKEN_IRQ to enable workaround for
 604          * FU540-C000 SoC in polling mode.
 605          * Since the SoC does have an interrupt, its DT has an interrupt
 606          * property - But this should be bypassed as the IRQ logic in this
 607          * SoC is broken.
 608          */
 609
 610         if (device_is_compatible(dev, "sifive,fu540-c000-i2c"))
 611                 bus->flags |= OCORES_FLAG_BROKEN_IRQ;
 612
 613         ret = ocores_init(dev, bus);
 614         if (ret)
 615                 goto err_clk;
 616
 617         return 0;
 618
 619 err_clk:
 620         clk_disable(&bus->clk);
 621         return ret;
 622 }
 623
 624 static const struct udevice_id ocores_i2c_ids[] = {
 625 { .compatible = "opencores,i2c-ocores", .data = TYPE_OCORES },
 626 { .compatible = "aeroflexgaisler,i2cmst", .data = TYPE_GRLIB },
 627 { .compatible = "sifive,fu540-c000-i2c" },
 628 { .compatible = "sifive,i2c0" },
 629 { }
 630 };
 631
 632 U_BOOT_DRIVER(i2c_ocores) = {
 633         .name   = "i2c_ocores",
 634         .id     = UCLASS_I2C,
 635         .of_match = ocores_i2c_ids,
 636         .probe = ocores_i2c_probe,
 637         .priv_auto = sizeof(struct ocores_i2c_bus),
 638         .ops    = &ocores_i2c_ops,
 639 };