2 * Freescale i.MX28 I2C Driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Partly based on Linux kernel i2c-mxs.c driver:
8 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
10 * Which was based on a (non-working) driver which was:
11 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
13 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/errno.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/imx-regs.h>
23 #include <asm/arch/sys_proto.h>
25 #define MXS_I2C_MAX_TIMEOUT 1000000
27 static void mxs_i2c_reset(void)
29 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
31 int speed = i2c_get_bus_speed();
33 ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
35 debug("MXS I2C: Block reset timeout\n");
39 writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
40 I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
41 I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
42 &i2c_regs->hw_i2c_ctrl1_clr);
44 writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
46 i2c_set_bus_speed(speed);
49 static void mxs_i2c_setup_read(uint8_t chip, int len)
51 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
53 writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
54 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
55 (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
56 &i2c_regs->hw_i2c_queuecmd);
58 writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
60 writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
61 (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
62 I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
64 writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
67 static void mxs_i2c_write(uchar chip, uint addr, int alen,
68 uchar *buf, int blen, int stop)
70 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
74 if ((alen > 4) || (alen == 0)) {
75 debug("MXS I2C: Invalid address length\n");
80 stop = I2C_QUEUECMD_POST_SEND_STOP;
82 writel(I2C_QUEUECMD_PRE_SEND_START |
83 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
84 ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
85 &i2c_regs->hw_i2c_queuecmd);
87 data = (chip << 1) << 24;
89 for (i = 0; i < alen; i++) {
91 data |= ((char *)&addr)[alen - i - 1] << 24;
93 writel(data, &i2c_regs->hw_i2c_data);
97 for (; i < off + blen; i++) {
99 data |= buf[i - off] << 24;
101 writel(data, &i2c_regs->hw_i2c_data);
104 remain = 24 - ((i & 3) * 8);
106 writel(data >> remain, &i2c_regs->hw_i2c_data);
108 writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
111 static int mxs_i2c_wait_for_ack(void)
113 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
115 int timeout = MXS_I2C_MAX_TIMEOUT;
118 tmp = readl(&i2c_regs->hw_i2c_ctrl1);
119 if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
120 debug("MXS I2C: No slave ACK\n");
125 I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
126 I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
127 debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
131 if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
135 debug("MXS I2C: Operation timed out\n");
149 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
151 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
153 int timeout = MXS_I2C_MAX_TIMEOUT;
157 mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
158 ret = mxs_i2c_wait_for_ack();
160 debug("MXS I2C: Failed writing address\n");
164 mxs_i2c_setup_read(chip, len);
165 ret = mxs_i2c_wait_for_ack();
167 debug("MXS I2C: Failed reading address\n");
171 for (i = 0; i < len; i++) {
174 tmp = readl(&i2c_regs->hw_i2c_queuestat);
175 if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
180 debug("MXS I2C: Failed receiving data!\n");
184 tmp = readl(&i2c_regs->hw_i2c_queuedata);
186 buffer[i] = tmp & 0xff;
193 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
196 mxs_i2c_write(chip, addr, alen, buffer, len, 1);
197 ret = mxs_i2c_wait_for_ack();
199 debug("MXS I2C: Failed writing address\n");
204 int i2c_probe(uchar chip)
207 mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
208 ret = mxs_i2c_wait_for_ack();
213 int i2c_set_bus_speed(unsigned int speed)
215 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
217 * The timing derivation algorithm. There is no documentation for this
218 * algorithm available, it was derived by using the scope and fiddling
219 * with constants until the result observed on the scope was good enough
220 * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
221 * possible to assume the algorithm works for other frequencies as well.
223 * Note it was necessary to cap the frequency on both ends as it's not
224 * possible to configure completely arbitrary frequency for the I2C bus
227 uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
228 uint32_t base = ((clk / speed) - 38) / 2;
229 uint16_t high_count = base + 3;
230 uint16_t low_count = base - 3;
231 uint16_t rcv_count = (high_count * 3) / 4;
232 uint16_t xmit_count = low_count / 4;
234 if (speed > 540000) {
235 printf("MXS I2C: Speed too high (%d Hz)\n", speed);
240 printf("MXS I2C: Speed too low (%d Hz)\n", speed);
244 writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
245 writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
247 writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
248 (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
249 &i2c_regs->hw_i2c_timing2);
254 unsigned int i2c_get_bus_speed(void)
256 struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
257 uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
260 timing0 = readl(&i2c_regs->hw_i2c_timing0);
262 * This is a reverse version of the algorithm presented in
263 * i2c_set_bus_speed(). Please refer there for details.
265 return clk / ((((timing0 >> 16) - 3) * 2) + 38);
268 void i2c_init(int speed, int slaveadd)
271 i2c_set_bus_speed(speed);