2 * i2c driver for Freescale i.MX series
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #if defined(CONFIG_HARD_I2C)
38 #include <asm/arch/clock.h>
39 #include <asm/arch/imx-regs.h>
50 #define I2CR_IEN (1 << 7)
51 #define I2CR_IIEN (1 << 6)
52 #define I2CR_MSTA (1 << 5)
53 #define I2CR_MTX (1 << 4)
54 #define I2CR_TX_NO_AK (1 << 3)
55 #define I2CR_RSTA (1 << 2)
57 #define I2SR_ICF (1 << 7)
58 #define I2SR_IBB (1 << 5)
59 #define I2SR_IIF (1 << 1)
60 #define I2SR_RX_NO_AK (1 << 0)
62 #ifdef CONFIG_SYS_I2C_BASE
63 #define I2C_BASE CONFIG_SYS_I2C_BASE
65 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
68 #define I2C_MAX_TIMEOUT 10000
70 static u16 i2c_clk_div[50][2] = {
71 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
72 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
73 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
74 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
75 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
76 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
77 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
78 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
79 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
80 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
81 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
82 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
83 { 3072, 0x1E }, { 3840, 0x1F }
87 * Calculate and set proper clock divider
89 static uint8_t i2c_imx_get_clk(unsigned int rate)
91 unsigned int i2c_clk_rate;
95 #if defined(CONFIG_MX31)
96 struct clock_control_regs *sc_regs =
97 (struct clock_control_regs *)CCM_BASE;
99 /* start the required I2C clock */
100 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
104 /* Divider value calculation */
105 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
106 div = (i2c_clk_rate + rate - 1) / rate;
107 if (div < i2c_clk_div[0][0])
109 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
110 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
112 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
115 /* Store divider value */
120 * Reset I2C Controller
124 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
126 writeb(0, &i2c_regs->i2cr); /* Reset module */
127 writeb(0, &i2c_regs->i2sr);
133 void i2c_init(int speed, int unused)
135 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
136 u8 clk_idx = i2c_imx_get_clk(speed);
137 u8 idx = i2c_clk_div[clk_idx][1];
139 /* Store divider value */
140 writeb(idx, &i2c_regs->ifdr);
148 int i2c_set_bus_speed(unsigned int speed)
157 unsigned int i2c_get_bus_speed(void)
159 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
160 u8 clk_idx = readb(&i2c_regs->ifdr);
163 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
166 return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
170 * Wait for bus to be busy (or free if for_busy = 0)
172 * for_busy = 1: Wait for IBB to be asserted
173 * for_busy = 0: Wait for IBB to be de-asserted
175 int i2c_imx_bus_busy(int for_busy)
177 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
180 int timeout = I2C_MAX_TIMEOUT;
183 temp = readb(&i2c_regs->i2sr);
185 if (for_busy && (temp & I2SR_IBB))
187 if (!for_busy && !(temp & I2SR_IBB))
197 * Wait for transaction to complete
199 int i2c_imx_trx_complete(void)
201 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
202 int timeout = I2C_MAX_TIMEOUT;
205 if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
206 writeb(0, &i2c_regs->i2sr);
217 * Check if the transaction was ACKed
219 int i2c_imx_acked(void)
221 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
223 return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK;
227 * Start the controller
229 int i2c_imx_start(void)
231 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
232 unsigned int temp = 0;
234 int speed = i2c_get_bus_speed();
235 u8 clk_idx = i2c_imx_get_clk(speed);
236 u8 idx = i2c_clk_div[clk_idx][1];
238 /* Store divider value */
239 writeb(idx, &i2c_regs->ifdr);
241 /* Enable I2C controller */
242 writeb(0, &i2c_regs->i2sr);
243 writeb(I2CR_IEN, &i2c_regs->i2cr);
245 /* Wait controller to be stable */
248 /* Start I2C transaction */
249 temp = readb(&i2c_regs->i2cr);
251 writeb(temp, &i2c_regs->i2cr);
253 result = i2c_imx_bus_busy(1);
257 temp |= I2CR_MTX | I2CR_TX_NO_AK;
258 writeb(temp, &i2c_regs->i2cr);
264 * Stop the controller
266 void i2c_imx_stop(void)
268 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
269 unsigned int temp = 0;
271 /* Stop I2C transaction */
272 temp = readb(&i2c_regs->i2cr);
273 temp |= ~(I2CR_MSTA | I2CR_MTX);
274 writeb(temp, &i2c_regs->i2cr);
278 /* Disable I2C controller */
279 writeb(0, &i2c_regs->i2cr);
283 * Set chip address and access mode
285 * read = 1: READ access
286 * read = 0: WRITE access
288 int i2c_imx_set_chip_addr(uchar chip, int read)
290 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
293 writeb((chip << 1) | read, &i2c_regs->i2dr);
295 ret = i2c_imx_trx_complete();
299 ret = i2c_imx_acked();
307 * Write register address
309 int i2c_imx_set_reg_addr(uint addr, int alen)
311 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
315 writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr);
317 ret = i2c_imx_trx_complete();
321 ret = i2c_imx_acked();
330 * Try if a chip add given address responds (probe the chip)
332 int i2c_probe(uchar chip)
336 ret = i2c_imx_start();
340 ret = i2c_imx_set_chip_addr(chip, 0);
350 * Read data from I2C device
352 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
354 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
359 ret = i2c_imx_start();
363 /* write slave address */
364 ret = i2c_imx_set_chip_addr(chip, 0);
368 ret = i2c_imx_set_reg_addr(addr, alen);
372 temp = readb(&i2c_regs->i2cr);
374 writeb(temp, &i2c_regs->i2cr);
376 ret = i2c_imx_set_chip_addr(chip, 1);
380 /* setup bus to read data */
381 temp = readb(&i2c_regs->i2cr);
382 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
384 temp |= I2CR_TX_NO_AK;
385 writeb(temp, &i2c_regs->i2cr);
386 readb(&i2c_regs->i2dr);
389 for (i = 0; i < len; i++) {
390 ret = i2c_imx_trx_complete();
395 * It must generate STOP before read I2DR to prevent
396 * controller from generating another clock cycle
398 if (i == (len - 1)) {
399 temp = readb(&i2c_regs->i2cr);
400 temp &= ~(I2CR_MSTA | I2CR_MTX);
401 writeb(temp, &i2c_regs->i2cr);
403 } else if (i == (len - 2)) {
404 temp = readb(&i2c_regs->i2cr);
405 temp |= I2CR_TX_NO_AK;
406 writeb(temp, &i2c_regs->i2cr);
409 buf[i] = readb(&i2c_regs->i2dr);
418 * Write data to I2C device
420 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
422 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
426 ret = i2c_imx_start();
430 /* write slave address */
431 ret = i2c_imx_set_chip_addr(chip, 0);
435 ret = i2c_imx_set_reg_addr(addr, alen);
439 for (i = 0; i < len; i++) {
440 writeb(buf[i], &i2c_regs->i2dr);
442 ret = i2c_imx_trx_complete();
446 ret = i2c_imx_acked();
455 #endif /* CONFIG_HARD_I2C */