1 // SPDX-License-Identifier: GPL-2.0+
3 * i2c driver for Freescale i.MX series
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
9 * Based on i2c-imx.c from linux kernel:
10 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
11 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
12 * Copyright (C) 2007 RightHand Technologies, Inc.
13 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/global_data.h>
22 #include <dm/device_compat.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <asm/mach-imx/mxc_i2c.h>
26 #include <asm/mach-imx/sys_proto.h>
31 #include <dm/pinctrl.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 #define I2C_QUIRK_FLAG (1 << 0)
38 #define IMX_I2C_REGSHIFT 2
39 #define VF610_I2C_REGSHIFT 0
41 #define I2C_EARLY_INIT_INDEX 0
42 #ifdef CONFIG_SYS_I2C_IFDR_DIV
43 #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
45 #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
55 #define I2CR_IIEN (1 << 6)
56 #define I2CR_MSTA (1 << 5)
57 #define I2CR_MTX (1 << 4)
58 #define I2CR_TX_NO_AK (1 << 3)
59 #define I2CR_RSTA (1 << 2)
61 #define I2SR_ICF (1 << 7)
62 #define I2SR_IBB (1 << 5)
63 #define I2SR_IAL (1 << 4)
64 #define I2SR_IIF (1 << 1)
65 #define I2SR_RX_NO_AK (1 << 0)
68 #define I2CR_IEN (0 << 7)
69 #define I2CR_IDIS (1 << 7)
70 #define I2SR_IIF_CLEAR (1 << 1)
72 #define I2CR_IEN (1 << 7)
73 #define I2CR_IDIS (0 << 7)
74 #define I2SR_IIF_CLEAR (0 << 1)
78 static u16 i2c_clk_div[60][2] = {
79 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
80 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
81 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
82 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
83 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
84 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
85 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
86 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
87 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
88 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
89 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
90 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
91 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
92 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
93 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
96 static u16 i2c_clk_div[50][2] = {
97 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
98 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
99 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
100 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
101 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
102 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
103 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
104 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
105 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
106 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
107 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
108 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
109 { 3072, 0x1E }, { 3840, 0x1F }
113 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
114 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
116 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
117 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
119 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
120 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
122 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
123 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
126 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
127 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
129 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
130 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
132 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
133 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
135 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
136 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
140 * Calculate and set proper clock divider
142 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
144 unsigned int i2c_clk_rate;
148 #if defined(CONFIG_MX31)
149 struct clock_control_regs *sc_regs =
150 (struct clock_control_regs *)CCM_BASE;
152 /* start the required I2C clock */
153 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
157 /* Divider value calculation */
158 #if CONFIG_IS_ENABLED(CLK)
159 i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
161 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
164 div = (i2c_clk_rate + rate - 1) / rate;
165 if (div < i2c_clk_div[0][0])
167 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
168 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
170 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
173 /* Store divider value */
180 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
182 ulong base = i2c_bus->base;
183 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
184 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
185 u8 idx = i2c_clk_div[clk_idx][1];
186 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
191 /* Store divider value */
192 writeb(idx, base + (IFDR << reg_shift));
195 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
196 writeb(0, base + (I2SR << reg_shift));
200 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
201 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
202 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
204 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
208 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
209 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
210 ulong base = i2c_bus->base;
211 ulong start_time = get_timer(0);
213 sr = readb(base + (I2SR << reg_shift));
216 writeb(sr | I2SR_IAL, base +
217 (I2SR << reg_shift));
219 writeb(sr & ~I2SR_IAL, base +
220 (I2SR << reg_shift));
221 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
222 __func__, sr, readb(base + (I2CR << reg_shift)),
226 if ((sr & (state >> 8)) == (unsigned char)state)
229 elapsed = get_timer(start_time);
230 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
233 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
234 sr, readb(base + (I2CR << reg_shift)), state);
238 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
241 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
242 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
243 ulong base = i2c_bus->base;
245 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
246 writeb(byte, base + (I2DR << reg_shift));
248 ret = wait_for_sr_state(i2c_bus, ST_IIF);
251 if (ret & I2SR_RX_NO_AK)
257 * Stub implementations for outer i2c slave operations.
259 void __i2c_force_reset_slave(void)
262 void i2c_force_reset_slave(void)
263 __attribute__((weak, alias("__i2c_force_reset_slave")));
266 * Stop I2C transaction
268 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
271 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
272 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
273 ulong base = i2c_bus->base;
274 unsigned int temp = readb(base + (I2CR << reg_shift));
276 temp &= ~(I2CR_MSTA | I2CR_MTX);
277 writeb(temp, base + (I2CR << reg_shift));
278 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
280 printf("%s:trigger stop failed\n", __func__);
284 * Send start signal, chip address and
285 * write register address
287 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
292 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
293 ulong base = i2c_bus->base;
294 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
296 /* Reset i2c slave */
297 i2c_force_reset_slave();
299 /* Enable I2C controller */
301 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
303 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
306 writeb(I2CR_IEN, base + (I2CR << reg_shift));
307 /* Wait for controller to be stable */
311 if (readb(base + (IADR << reg_shift)) == (chip << 1))
312 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
313 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
314 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
318 /* Start I2C transaction */
319 temp = readb(base + (I2CR << reg_shift));
321 writeb(temp, base + (I2CR << reg_shift));
323 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
327 temp |= I2CR_MTX | I2CR_TX_NO_AK;
328 writeb(temp, base + (I2CR << reg_shift));
331 /* write slave address */
332 ret = tx_byte(i2c_bus, chip << 1);
337 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
346 #if !defined(I2C2_BASE_ADDR)
347 #define I2C2_BASE_ADDR 0
350 #if !defined(I2C3_BASE_ADDR)
351 #define I2C3_BASE_ADDR 0
354 #if !defined(I2C4_BASE_ADDR)
355 #define I2C4_BASE_ADDR 0
358 #if !defined(I2C5_BASE_ADDR)
359 #define I2C5_BASE_ADDR 0
362 #if !defined(I2C6_BASE_ADDR)
363 #define I2C6_BASE_ADDR 0
366 #if !defined(I2C7_BASE_ADDR)
367 #define I2C7_BASE_ADDR 0
370 #if !defined(I2C8_BASE_ADDR)
371 #define I2C8_BASE_ADDR 0
374 static struct mxc_i2c_bus mxc_i2c_buses[] = {
375 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
376 defined(CONFIG_FSL_LAYERSCAPE)
377 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
378 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
379 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
380 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
381 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
382 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
383 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
384 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
386 { 0, I2C1_BASE_ADDR, 0 },
387 { 1, I2C2_BASE_ADDR, 0 },
388 { 2, I2C3_BASE_ADDR, 0 },
389 { 3, I2C4_BASE_ADDR, 0 },
390 { 4, I2C5_BASE_ADDR, 0 },
391 { 5, I2C6_BASE_ADDR, 0 },
392 { 6, I2C7_BASE_ADDR, 0 },
393 { 7, I2C8_BASE_ADDR, 0 },
397 #ifndef CONFIG_DM_I2C
398 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
400 if (i2c_bus && i2c_bus->idle_bus_fn)
401 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
406 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
408 * scl-gpios: specify the gpio related to SCL pin
409 * sda-gpios: specify the gpio related to SDA pin
410 * add pinctrl to configure i2c pins to gpio function for i2c
411 * bus recovery, call it "gpio" state
414 * The i2c_idle_bus is an implementation following Linux Kernel.
416 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
418 struct udevice *bus = i2c_bus->bus;
419 struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
420 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
421 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
422 int sda, scl, idle_sclks;
424 ulong elapsed, start_time;
426 if (pinctrl_select_state(bus, "gpio")) {
427 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
429 * GPIO pinctrl for i2c force idle is not a must,
430 * but it is strongly recommended to be used.
431 * Because it can help you to recover from bad
432 * i2c bus state. Do not return failure, because
438 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
439 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
440 scl = dm_gpio_get_value(scl_gpio);
441 sda = dm_gpio_get_value(sda_gpio);
443 if ((sda & scl) == 1)
444 goto exit; /* Bus is idle already */
447 * In most cases it is just enough to generate 8 + 1 SCLK
448 * clocks to recover I2C slave device from 'stuck' state
449 * (when for example SW reset was performed, in the middle of
452 * However, there are devices which send data in packets of
453 * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
458 if (i2c->max_transaction_bytes > 0)
459 idle_sclks = i2c->max_transaction_bytes * 8 + 1;
460 /* Send high and low on the SCL line */
461 for (i = 0; i < idle_sclks; i++) {
462 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
463 dm_gpio_set_value(scl_gpio, 0);
465 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
468 start_time = get_timer(0);
470 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
471 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
472 scl = dm_gpio_get_value(scl_gpio);
473 sda = dm_gpio_get_value(sda_gpio);
474 if ((sda & scl) == 1)
477 elapsed = get_timer(start_time);
478 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
480 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
486 pinctrl_select_state(bus, "default");
491 * Early init I2C for prepare read the clk through I2C.
493 void i2c_early_init_f(void)
495 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
496 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
497 & I2C_QUIRK_FLAG ? true : false;
498 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
500 /* Set I2C divider value */
501 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
503 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
504 writeb(0, base + (I2SR << reg_shift));
506 writeb(I2CR_IEN, base + (I2CR << reg_shift));
509 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
514 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
515 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
520 for (retry = 0; retry < 3; retry++) {
521 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
524 i2c_imx_stop(i2c_bus);
525 if (ret == -EREMOTEIO)
528 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
530 if (ret != -ERESTART)
531 /* Disable controller */
532 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
534 if (i2c_idle_bus(i2c_bus) < 0)
537 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
542 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
547 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
548 debug("write_data: ");
549 /* use rc for counter */
550 for (i = 0; i < len; ++i)
551 debug(" 0x%02x", buf[i]);
554 for (i = 0; i < len; i++) {
555 ret = tx_byte(i2c_bus, buf[i]);
557 debug("i2c_write_data(): rc=%d\n", ret);
565 /* Will generate a STOP after the last byte if "last" is true, i.e. this is the
566 * final message of a transaction. If not, it switches the bus back to TX mode
567 * and does not send a STOP, leaving the bus in a state where a repeated start
568 * and address can be sent for another message.
570 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
576 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
577 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
578 ulong base = i2c_bus->base;
580 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
582 /* setup bus to read data */
583 temp = readb(base + (I2CR << reg_shift));
584 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
586 temp |= I2CR_TX_NO_AK;
587 writeb(temp, base + (I2CR << reg_shift));
588 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
589 /* dummy read to clear ICF */
590 readb(base + (I2DR << reg_shift));
593 for (i = 0; i < len; i++) {
594 ret = wait_for_sr_state(i2c_bus, ST_IIF);
596 debug("i2c_read_data(): ret=%d\n", ret);
597 i2c_imx_stop(i2c_bus);
601 if (i == (len - 1)) {
602 /* Final byte has already been received by master! When
603 * we read it from I2DR, the master will start another
604 * cycle. We must program it first to send a STOP or
605 * switch to TX to avoid this.
608 i2c_imx_stop(i2c_bus);
610 /* Final read, no stop, switch back to tx */
611 temp = readb(base + (I2CR << reg_shift));
612 temp |= I2CR_MTX | I2CR_TX_NO_AK;
613 writeb(temp, base + (I2CR << reg_shift));
615 } else if (i == (len - 2)) {
616 /* Master has already recevied penultimate byte. When
617 * we read it from I2DR, master will start RX of final
618 * byte. We must set TX_NO_AK now so it does not ACK
621 temp = readb(base + (I2CR << reg_shift));
622 temp |= I2CR_TX_NO_AK;
623 writeb(temp, base + (I2CR << reg_shift));
626 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
627 buf[i] = readb(base + (I2DR << reg_shift));
630 /* reuse ret for counter*/
631 for (ret = 0; ret < len; ++ret)
632 debug(" 0x%02x", buf[ret]);
635 /* It is not clear to me that this is necessary */
637 i2c_imx_stop(i2c_bus);
641 int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
646 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
647 __attribute__((weak, alias("__enable_i2c_clk")));
649 #ifndef CONFIG_DM_I2C
651 * Read data from I2C device
653 * The transactions use the syntax defined in the Linux kernel I2C docs.
655 * If alen is > 0, then this function will send a transaction of the form:
656 * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
657 * This is a normal I2C register read: writing the register address, then doing
658 * a repeated start and reading the data.
660 * If alen == 0, then we get this transaction:
661 * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
662 * This is somewhat unusual, though valid, transaction. It addresses the chip
663 * in write mode, but doesn't actually write any register address or data, then
664 * does a repeated start and reads data.
666 * If alen < 0, then we get this transaction:
667 * S Chip Rd [A] [data] A ... NA P
668 * The chip is addressed in read mode and then data is read. No register
669 * address is written first. This is perfectly valid on most devices and
670 * required on some (usually those that don't act like an array of registers).
672 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
673 int alen, u8 *buf, int len)
677 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
678 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
679 ulong base = i2c_bus->base;
681 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
686 temp = readb(base + (I2CR << reg_shift));
688 writeb(temp, base + (I2CR << reg_shift));
691 ret = tx_byte(i2c_bus, (chip << 1) | 1);
693 i2c_imx_stop(i2c_bus);
697 ret = i2c_read_data(i2c_bus, chip, buf, len, true);
699 i2c_imx_stop(i2c_bus);
704 * Write data to I2C device
706 * If alen > 0, we get this transaction:
707 * S Chip Wr [A] addr [A] data [A] ... [A] P
708 * An ordinary write register command.
710 * If alen == 0, then we get this:
711 * S Chip Wr [A] data [A] ... [A] P
712 * This is a simple I2C write.
714 * If alen < 0, then we get this:
715 * S data [A] ... [A] P
716 * This is most likely NOT something that should be used. It doesn't send the
717 * chip address first, so in effect, the first byte of data will be used as the
720 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
721 int alen, const u8 *buf, int len)
725 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
729 ret = i2c_write_data(i2c_bus, chip, buf, len);
731 i2c_imx_stop(i2c_bus);
736 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
738 return &mxc_i2c_buses[adap->hwadapnr];
741 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
742 uint addr, int alen, uint8_t *buffer,
745 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
748 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
749 uint addr, int alen, uint8_t *buffer,
752 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
756 * Test if a chip at a given address responds (probe the chip)
758 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
760 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
763 void bus_i2c_init(int index, int speed, int unused,
764 int (*idle_bus_fn)(void *p), void *idle_bus_data)
768 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
769 debug("Error i2c index\n");
773 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
774 if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
775 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
776 (ulong)mxc_i2c_buses[index].base);
782 * Warning: Be careful to allow the assignment to a static
783 * variable here. This function could be called while U-Boot is
784 * still running in flash memory. So such assignment is equal
785 * to write data to flash without erasing.
788 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
790 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
792 ret = enable_i2c_clk(1, index);
794 debug("I2C-%d clk fail to enable.\n", index);
798 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
806 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
808 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
814 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
816 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
820 * Register mxc i2c adapters
822 #ifdef CONFIG_SYS_I2C_MXC_I2C1
823 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
824 mxc_i2c_read, mxc_i2c_write,
825 mxc_i2c_set_bus_speed,
826 CONFIG_SYS_MXC_I2C1_SPEED,
827 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
830 #ifdef CONFIG_SYS_I2C_MXC_I2C2
831 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
832 mxc_i2c_read, mxc_i2c_write,
833 mxc_i2c_set_bus_speed,
834 CONFIG_SYS_MXC_I2C2_SPEED,
835 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
838 #ifdef CONFIG_SYS_I2C_MXC_I2C3
839 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
840 mxc_i2c_read, mxc_i2c_write,
841 mxc_i2c_set_bus_speed,
842 CONFIG_SYS_MXC_I2C3_SPEED,
843 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
846 #ifdef CONFIG_SYS_I2C_MXC_I2C4
847 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
848 mxc_i2c_read, mxc_i2c_write,
849 mxc_i2c_set_bus_speed,
850 CONFIG_SYS_MXC_I2C4_SPEED,
851 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
854 #ifdef CONFIG_SYS_I2C_MXC_I2C5
855 U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
856 mxc_i2c_read, mxc_i2c_write,
857 mxc_i2c_set_bus_speed,
858 CONFIG_SYS_MXC_I2C5_SPEED,
859 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
862 #ifdef CONFIG_SYS_I2C_MXC_I2C6
863 U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
864 mxc_i2c_read, mxc_i2c_write,
865 mxc_i2c_set_bus_speed,
866 CONFIG_SYS_MXC_I2C6_SPEED,
867 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
870 #ifdef CONFIG_SYS_I2C_MXC_I2C7
871 U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
872 mxc_i2c_read, mxc_i2c_write,
873 mxc_i2c_set_bus_speed,
874 CONFIG_SYS_MXC_I2C7_SPEED,
875 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
878 #ifdef CONFIG_SYS_I2C_MXC_I2C8
879 U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
880 mxc_i2c_read, mxc_i2c_write,
881 mxc_i2c_set_bus_speed,
882 CONFIG_SYS_MXC_I2C8_SPEED,
883 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
888 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
890 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
892 return bus_i2c_set_bus_speed(i2c_bus, speed);
895 static int mxc_i2c_probe(struct udevice *bus)
897 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
898 const void *fdt = gd->fdt_blob;
899 int node = dev_of_offset(bus);
903 i2c_bus->driver_data = dev_get_driver_data(bus);
905 addr = dev_read_addr(bus);
906 if (addr == FDT_ADDR_T_NONE)
909 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
910 if (i2c_fused((ulong)addr)) {
911 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
917 i2c_bus->base = addr;
918 i2c_bus->index = dev_seq(bus);
922 #if CONFIG_IS_ENABLED(CLK)
923 ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
925 printf("Failed to get i2c clk\n");
928 ret = clk_enable(&i2c_bus->per_clk);
930 printf("Failed to enable i2c clk\n");
934 ret = enable_i2c_clk(1, dev_seq(bus));
940 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
941 * Use gpio to force bus idle when necessary.
943 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
945 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
946 dev_seq(bus), i2c_bus->base);
948 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
949 "scl-gpios", 0, &i2c_bus->scl_gpio,
951 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
952 "sda-gpios", 0, &i2c_bus->sda_gpio,
954 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
955 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
958 "i2c bus %d at 0x%2lx, fail to request scl/sda gpio\n",
959 dev_seq(bus), i2c_bus->base);
965 * Pinmux settings are in board file now, until pinmux is supported,
966 * we can set pinmux here in probe function.
969 debug("i2c : controller bus %d at %lu , speed %d: ",
970 dev_seq(bus), i2c_bus->base,
976 /* Sends: S Addr Wr [A|NA] P */
977 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
981 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
983 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
985 debug("%s failed, ret = %d\n", __func__, ret);
989 i2c_imx_stop(i2c_bus);
994 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
996 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
998 ulong base = i2c_bus->base;
999 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
1000 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
1003 /* Here address len is set to -1 to not send any address at first.
1004 * Otherwise i2c_init_transfer will send the chip address with write
1005 * mode set. This is wrong if the 1st message is read.
1007 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
1009 debug("i2c_init_transfer error: %d\n", ret);
1013 read_mode = -1; /* So it's always different on the first message */
1014 for (; nmsgs > 0; nmsgs--, msg++) {
1015 const int msg_is_read = !!(msg->flags & I2C_M_RD);
1017 debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
1018 msg->len, msg_is_read ? 'R' : 'W');
1020 if (msg_is_read != read_mode) {
1021 /* Send repeated start if not 1st message */
1022 if (read_mode != -1) {
1023 debug("i2c_xfer: [RSTART]\n");
1024 ret = readb(base + (I2CR << reg_shift));
1026 writeb(ret, base + (I2CR << reg_shift));
1028 debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
1029 msg_is_read ? 'R' : 'W');
1030 ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
1032 debug("i2c_xfer: [STOP]\n");
1033 i2c_imx_stop(i2c_bus);
1036 read_mode = msg_is_read;
1039 if (msg->flags & I2C_M_RD)
1040 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1041 msg->len, nmsgs == 1 ||
1042 (msg->flags & I2C_M_STOP));
1044 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1052 debug("i2c_write: error sending\n");
1054 i2c_imx_stop(i2c_bus);
1059 static const struct dm_i2c_ops mxc_i2c_ops = {
1060 .xfer = mxc_i2c_xfer,
1061 .probe_chip = mxc_i2c_probe_chip,
1062 .set_bus_speed = mxc_i2c_set_bus_speed,
1065 static const struct udevice_id mxc_i2c_ids[] = {
1066 { .compatible = "fsl,imx21-i2c", },
1067 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
1071 U_BOOT_DRIVER(i2c_mxc) = {
1074 .of_match = mxc_i2c_ids,
1075 .probe = mxc_i2c_probe,
1076 .priv_auto = sizeof(struct mxc_i2c_bus),
1077 .ops = &mxc_i2c_ops,
1078 .flags = DM_FLAG_PRE_RELOC,