1 // SPDX-License-Identifier: GPL-2.0+
3 * i2c driver for Freescale i.MX series
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
9 * Based on i2c-imx.c from linux kernel:
10 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
11 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
12 * Copyright (C) 2007 RightHand Technologies, Inc.
13 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/global_data.h>
22 #include <dm/device_compat.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <asm/mach-imx/mxc_i2c.h>
26 #include <asm/mach-imx/sys_proto.h>
31 #include <dm/pinctrl.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 #define I2C_QUIRK_FLAG (1 << 0)
38 #define IMX_I2C_REGSHIFT 2
39 #define VF610_I2C_REGSHIFT 0
41 #define I2C_EARLY_INIT_INDEX 0
42 #ifdef CONFIG_SYS_I2C_IFDR_DIV
43 #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
45 #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
55 #define I2CR_IIEN (1 << 6)
56 #define I2CR_MSTA (1 << 5)
57 #define I2CR_MTX (1 << 4)
58 #define I2CR_TX_NO_AK (1 << 3)
59 #define I2CR_RSTA (1 << 2)
61 #define I2SR_ICF (1 << 7)
62 #define I2SR_IBB (1 << 5)
63 #define I2SR_IAL (1 << 4)
64 #define I2SR_IIF (1 << 1)
65 #define I2SR_RX_NO_AK (1 << 0)
68 #define I2CR_IEN (0 << 7)
69 #define I2CR_IDIS (1 << 7)
70 #define I2SR_IIF_CLEAR (1 << 1)
72 #define I2CR_IEN (1 << 7)
73 #define I2CR_IDIS (0 << 7)
74 #define I2SR_IIF_CLEAR (0 << 1)
78 static u16 i2c_clk_div[60][2] = {
79 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
80 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
81 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
82 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
83 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
84 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
85 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
86 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
87 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
88 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
89 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
90 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
91 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
92 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
93 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
96 static u16 i2c_clk_div[50][2] = {
97 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
98 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
99 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
100 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
101 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
102 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
103 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
104 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
105 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
106 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
107 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
108 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
109 { 3072, 0x1E }, { 3840, 0x1F }
114 * Calculate and set proper clock divider
116 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
118 unsigned int i2c_clk_rate;
122 #if defined(CONFIG_MX31)
123 struct clock_control_regs *sc_regs =
124 (struct clock_control_regs *)CCM_BASE;
126 /* start the required I2C clock */
127 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
131 /* Divider value calculation */
132 #if CONFIG_IS_ENABLED(CLK)
133 i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
135 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
138 div = (i2c_clk_rate + rate - 1) / rate;
139 if (div < i2c_clk_div[0][0])
141 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
142 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
144 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
147 /* Store divider value */
154 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
156 ulong base = i2c_bus->base;
157 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
158 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
159 u8 idx = i2c_clk_div[clk_idx][1];
160 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
165 /* Store divider value */
166 writeb(idx, base + (IFDR << reg_shift));
169 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
170 writeb(0, base + (I2SR << reg_shift));
174 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
175 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
176 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
178 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
182 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
183 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
184 ulong base = i2c_bus->base;
185 ulong start_time = get_timer(0);
187 sr = readb(base + (I2SR << reg_shift));
190 writeb(sr | I2SR_IAL, base +
191 (I2SR << reg_shift));
193 writeb(sr & ~I2SR_IAL, base +
194 (I2SR << reg_shift));
195 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
196 __func__, sr, readb(base + (I2CR << reg_shift)),
200 if ((sr & (state >> 8)) == (unsigned char)state)
203 elapsed = get_timer(start_time);
204 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
207 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
208 sr, readb(base + (I2CR << reg_shift)), state);
212 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
215 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
216 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
217 ulong base = i2c_bus->base;
219 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
220 writeb(byte, base + (I2DR << reg_shift));
222 ret = wait_for_sr_state(i2c_bus, ST_IIF);
225 if (ret & I2SR_RX_NO_AK)
231 * Stub implementations for outer i2c slave operations.
233 void __i2c_force_reset_slave(void)
236 void i2c_force_reset_slave(void)
237 __attribute__((weak, alias("__i2c_force_reset_slave")));
240 * Stop I2C transaction
242 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
245 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
246 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
247 ulong base = i2c_bus->base;
248 unsigned int temp = readb(base + (I2CR << reg_shift));
250 temp &= ~(I2CR_MSTA | I2CR_MTX);
251 writeb(temp, base + (I2CR << reg_shift));
252 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
254 printf("%s:trigger stop failed\n", __func__);
258 * Send start signal, chip address and
259 * write register address
261 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
266 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
267 ulong base = i2c_bus->base;
268 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
270 /* Reset i2c slave */
271 i2c_force_reset_slave();
273 /* Enable I2C controller */
275 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
277 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
280 writeb(I2CR_IEN, base + (I2CR << reg_shift));
281 /* Wait for controller to be stable */
285 if (readb(base + (IADR << reg_shift)) == (chip << 1))
286 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
287 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
288 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
292 /* Start I2C transaction */
293 temp = readb(base + (I2CR << reg_shift));
295 writeb(temp, base + (I2CR << reg_shift));
297 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
301 temp |= I2CR_MTX | I2CR_TX_NO_AK;
302 writeb(temp, base + (I2CR << reg_shift));
305 /* write slave address */
306 ret = tx_byte(i2c_bus, chip << 1);
311 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
320 #if !defined(I2C2_BASE_ADDR)
321 #define I2C2_BASE_ADDR 0
324 #if !defined(I2C3_BASE_ADDR)
325 #define I2C3_BASE_ADDR 0
328 #if !defined(I2C4_BASE_ADDR)
329 #define I2C4_BASE_ADDR 0
332 #if !defined(I2C5_BASE_ADDR)
333 #define I2C5_BASE_ADDR 0
336 #if !defined(I2C6_BASE_ADDR)
337 #define I2C6_BASE_ADDR 0
340 #if !defined(I2C7_BASE_ADDR)
341 #define I2C7_BASE_ADDR 0
344 #if !defined(I2C8_BASE_ADDR)
345 #define I2C8_BASE_ADDR 0
348 static struct mxc_i2c_bus mxc_i2c_buses[] = {
349 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
350 defined(CONFIG_FSL_LAYERSCAPE)
351 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
352 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
353 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
354 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
355 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
356 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
357 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
358 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
360 { 0, I2C1_BASE_ADDR, 0 },
361 { 1, I2C2_BASE_ADDR, 0 },
362 { 2, I2C3_BASE_ADDR, 0 },
363 { 3, I2C4_BASE_ADDR, 0 },
364 { 4, I2C5_BASE_ADDR, 0 },
365 { 5, I2C6_BASE_ADDR, 0 },
366 { 6, I2C7_BASE_ADDR, 0 },
367 { 7, I2C8_BASE_ADDR, 0 },
371 #if !CONFIG_IS_ENABLED(DM_I2C)
372 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
374 if (i2c_bus && i2c_bus->idle_bus_fn)
375 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
380 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
382 * scl-gpios: specify the gpio related to SCL pin
383 * sda-gpios: specify the gpio related to SDA pin
384 * add pinctrl to configure i2c pins to gpio function for i2c
385 * bus recovery, call it "gpio" state
388 * The i2c_idle_bus is an implementation following Linux Kernel.
390 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
392 struct udevice *bus = i2c_bus->bus;
393 struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
394 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
395 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
396 int sda, scl, idle_sclks;
398 ulong elapsed, start_time;
400 if (pinctrl_select_state(bus, "gpio")) {
401 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
403 * GPIO pinctrl for i2c force idle is not a must,
404 * but it is strongly recommended to be used.
405 * Because it can help you to recover from bad
406 * i2c bus state. Do not return failure, because
412 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
413 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
414 scl = dm_gpio_get_value(scl_gpio);
415 sda = dm_gpio_get_value(sda_gpio);
417 if ((sda & scl) == 1)
418 goto exit; /* Bus is idle already */
421 * In most cases it is just enough to generate 8 + 1 SCLK
422 * clocks to recover I2C slave device from 'stuck' state
423 * (when for example SW reset was performed, in the middle of
426 * However, there are devices which send data in packets of
427 * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
432 if (i2c->max_transaction_bytes > 0)
433 idle_sclks = i2c->max_transaction_bytes * 8 + 1;
434 /* Send high and low on the SCL line */
435 for (i = 0; i < idle_sclks; i++) {
436 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
437 dm_gpio_set_value(scl_gpio, 0);
439 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
442 start_time = get_timer(0);
444 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
445 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
446 scl = dm_gpio_get_value(scl_gpio);
447 sda = dm_gpio_get_value(sda_gpio);
448 if ((sda & scl) == 1)
451 elapsed = get_timer(start_time);
452 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
454 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
460 pinctrl_select_state(bus, "default");
465 * Early init I2C for prepare read the clk through I2C.
467 void i2c_early_init_f(void)
469 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
470 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
471 & I2C_QUIRK_FLAG ? true : false;
472 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
474 /* Set I2C divider value */
475 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
477 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
478 writeb(0, base + (I2SR << reg_shift));
480 writeb(I2CR_IEN, base + (I2CR << reg_shift));
483 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
488 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
489 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
494 for (retry = 0; retry < 3; retry++) {
495 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
498 i2c_imx_stop(i2c_bus);
499 if (ret == -EREMOTEIO)
502 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
504 if (ret != -ERESTART)
505 /* Disable controller */
506 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
508 if (i2c_idle_bus(i2c_bus) < 0)
511 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
516 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
521 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
522 debug("write_data: ");
523 /* use rc for counter */
524 for (i = 0; i < len; ++i)
525 debug(" 0x%02x", buf[i]);
528 for (i = 0; i < len; i++) {
529 ret = tx_byte(i2c_bus, buf[i]);
531 debug("i2c_write_data(): rc=%d\n", ret);
539 /* Will generate a STOP after the last byte if "last" is true, i.e. this is the
540 * final message of a transaction. If not, it switches the bus back to TX mode
541 * and does not send a STOP, leaving the bus in a state where a repeated start
542 * and address can be sent for another message.
544 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
550 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
551 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
552 ulong base = i2c_bus->base;
554 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
556 /* setup bus to read data */
557 temp = readb(base + (I2CR << reg_shift));
558 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
560 temp |= I2CR_TX_NO_AK;
561 writeb(temp, base + (I2CR << reg_shift));
562 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
563 /* dummy read to clear ICF */
564 readb(base + (I2DR << reg_shift));
567 for (i = 0; i < len; i++) {
568 ret = wait_for_sr_state(i2c_bus, ST_IIF);
570 debug("i2c_read_data(): ret=%d\n", ret);
571 i2c_imx_stop(i2c_bus);
575 if (i == (len - 1)) {
576 /* Final byte has already been received by master! When
577 * we read it from I2DR, the master will start another
578 * cycle. We must program it first to send a STOP or
579 * switch to TX to avoid this.
582 i2c_imx_stop(i2c_bus);
584 /* Final read, no stop, switch back to tx */
585 temp = readb(base + (I2CR << reg_shift));
586 temp |= I2CR_MTX | I2CR_TX_NO_AK;
587 writeb(temp, base + (I2CR << reg_shift));
589 } else if (i == (len - 2)) {
590 /* Master has already recevied penultimate byte. When
591 * we read it from I2DR, master will start RX of final
592 * byte. We must set TX_NO_AK now so it does not ACK
595 temp = readb(base + (I2CR << reg_shift));
596 temp |= I2CR_TX_NO_AK;
597 writeb(temp, base + (I2CR << reg_shift));
600 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
601 buf[i] = readb(base + (I2DR << reg_shift));
604 /* reuse ret for counter*/
605 for (ret = 0; ret < len; ++ret)
606 debug(" 0x%02x", buf[ret]);
609 /* It is not clear to me that this is necessary */
611 i2c_imx_stop(i2c_bus);
615 int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
620 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
621 __attribute__((weak, alias("__enable_i2c_clk")));
623 #if !CONFIG_IS_ENABLED(DM_I2C)
625 * Read data from I2C device
627 * The transactions use the syntax defined in the Linux kernel I2C docs.
629 * If alen is > 0, then this function will send a transaction of the form:
630 * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
631 * This is a normal I2C register read: writing the register address, then doing
632 * a repeated start and reading the data.
634 * If alen == 0, then we get this transaction:
635 * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
636 * This is somewhat unusual, though valid, transaction. It addresses the chip
637 * in write mode, but doesn't actually write any register address or data, then
638 * does a repeated start and reads data.
640 * If alen < 0, then we get this transaction:
641 * S Chip Rd [A] [data] A ... NA P
642 * The chip is addressed in read mode and then data is read. No register
643 * address is written first. This is perfectly valid on most devices and
644 * required on some (usually those that don't act like an array of registers).
646 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
647 int alen, u8 *buf, int len)
651 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
652 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
653 ulong base = i2c_bus->base;
655 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
660 temp = readb(base + (I2CR << reg_shift));
662 writeb(temp, base + (I2CR << reg_shift));
665 ret = tx_byte(i2c_bus, (chip << 1) | 1);
667 i2c_imx_stop(i2c_bus);
671 ret = i2c_read_data(i2c_bus, chip, buf, len, true);
673 i2c_imx_stop(i2c_bus);
678 * Write data to I2C device
680 * If alen > 0, we get this transaction:
681 * S Chip Wr [A] addr [A] data [A] ... [A] P
682 * An ordinary write register command.
684 * If alen == 0, then we get this:
685 * S Chip Wr [A] data [A] ... [A] P
686 * This is a simple I2C write.
688 * If alen < 0, then we get this:
689 * S data [A] ... [A] P
690 * This is most likely NOT something that should be used. It doesn't send the
691 * chip address first, so in effect, the first byte of data will be used as the
694 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
695 int alen, const u8 *buf, int len)
699 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
703 ret = i2c_write_data(i2c_bus, chip, buf, len);
705 i2c_imx_stop(i2c_bus);
710 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
712 return &mxc_i2c_buses[adap->hwadapnr];
715 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
716 uint addr, int alen, uint8_t *buffer,
719 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
722 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
723 uint addr, int alen, uint8_t *buffer,
726 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
730 * Test if a chip at a given address responds (probe the chip)
732 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
734 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
737 void bus_i2c_init(int index, int speed, int unused,
738 int (*idle_bus_fn)(void *p), void *idle_bus_data)
742 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
743 debug("Error i2c index\n");
747 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
748 if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
749 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
750 (ulong)mxc_i2c_buses[index].base);
756 * Warning: Be careful to allow the assignment to a static
757 * variable here. This function could be called while U-Boot is
758 * still running in flash memory. So such assignment is equal
759 * to write data to flash without erasing.
762 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
764 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
766 ret = enable_i2c_clk(1, index);
768 debug("I2C-%d clk fail to enable.\n", index);
772 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
780 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
782 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
788 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
790 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
794 * Register mxc i2c adapters
796 #ifdef CONFIG_SYS_I2C_MXC_I2C1
797 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
798 mxc_i2c_read, mxc_i2c_write,
799 mxc_i2c_set_bus_speed,
800 CONFIG_SYS_MXC_I2C1_SPEED,
801 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
804 #ifdef CONFIG_SYS_I2C_MXC_I2C2
805 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
806 mxc_i2c_read, mxc_i2c_write,
807 mxc_i2c_set_bus_speed,
808 CONFIG_SYS_MXC_I2C2_SPEED,
809 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
812 #ifdef CONFIG_SYS_I2C_MXC_I2C3
813 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
814 mxc_i2c_read, mxc_i2c_write,
815 mxc_i2c_set_bus_speed,
816 CONFIG_SYS_MXC_I2C3_SPEED,
817 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
820 #ifdef CONFIG_SYS_I2C_MXC_I2C4
821 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
822 mxc_i2c_read, mxc_i2c_write,
823 mxc_i2c_set_bus_speed,
824 CONFIG_SYS_MXC_I2C4_SPEED,
825 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
828 #ifdef CONFIG_SYS_I2C_MXC_I2C5
829 U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
830 mxc_i2c_read, mxc_i2c_write,
831 mxc_i2c_set_bus_speed,
832 CONFIG_SYS_MXC_I2C5_SPEED,
833 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
836 #ifdef CONFIG_SYS_I2C_MXC_I2C6
837 U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
838 mxc_i2c_read, mxc_i2c_write,
839 mxc_i2c_set_bus_speed,
840 CONFIG_SYS_MXC_I2C6_SPEED,
841 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
844 #ifdef CONFIG_SYS_I2C_MXC_I2C7
845 U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
846 mxc_i2c_read, mxc_i2c_write,
847 mxc_i2c_set_bus_speed,
848 CONFIG_SYS_MXC_I2C7_SPEED,
849 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
852 #ifdef CONFIG_SYS_I2C_MXC_I2C8
853 U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
854 mxc_i2c_read, mxc_i2c_write,
855 mxc_i2c_set_bus_speed,
856 CONFIG_SYS_MXC_I2C8_SPEED,
857 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
862 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
864 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
866 return bus_i2c_set_bus_speed(i2c_bus, speed);
869 static int mxc_i2c_probe(struct udevice *bus)
871 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
872 const void *fdt = gd->fdt_blob;
873 int node = dev_of_offset(bus);
877 i2c_bus->driver_data = dev_get_driver_data(bus);
879 addr = dev_read_addr(bus);
880 if (addr == FDT_ADDR_T_NONE)
883 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
884 if (i2c_fused((ulong)addr)) {
885 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
891 i2c_bus->base = addr;
892 i2c_bus->index = dev_seq(bus);
896 #if CONFIG_IS_ENABLED(CLK)
897 ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
899 printf("Failed to get i2c clk\n");
902 ret = clk_enable(&i2c_bus->per_clk);
904 printf("Failed to enable i2c clk\n");
908 ret = enable_i2c_clk(1, dev_seq(bus));
914 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
915 * Use gpio to force bus idle when necessary.
917 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
919 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
920 dev_seq(bus), i2c_bus->base);
922 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
923 "scl-gpios", 0, &i2c_bus->scl_gpio,
925 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
926 "sda-gpios", 0, &i2c_bus->sda_gpio,
928 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
929 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
932 "i2c bus %d at 0x%2lx, fail to request scl/sda gpio\n",
933 dev_seq(bus), i2c_bus->base);
939 * Pinmux settings are in board file now, until pinmux is supported,
940 * we can set pinmux here in probe function.
943 debug("i2c : controller bus %d at %lu , speed %d: ",
944 dev_seq(bus), i2c_bus->base,
950 /* Sends: S Addr Wr [A|NA] P */
951 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
955 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
957 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
959 debug("%s failed, ret = %d\n", __func__, ret);
963 i2c_imx_stop(i2c_bus);
968 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
970 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
972 ulong base = i2c_bus->base;
973 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
974 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
977 /* Here address len is set to -1 to not send any address at first.
978 * Otherwise i2c_init_transfer will send the chip address with write
979 * mode set. This is wrong if the 1st message is read.
981 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
983 debug("i2c_init_transfer error: %d\n", ret);
987 read_mode = -1; /* So it's always different on the first message */
988 for (; nmsgs > 0; nmsgs--, msg++) {
989 const int msg_is_read = !!(msg->flags & I2C_M_RD);
991 debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
992 msg->len, msg_is_read ? 'R' : 'W');
994 if (msg_is_read != read_mode) {
995 /* Send repeated start if not 1st message */
996 if (read_mode != -1) {
997 debug("i2c_xfer: [RSTART]\n");
998 ret = readb(base + (I2CR << reg_shift));
1000 writeb(ret, base + (I2CR << reg_shift));
1002 debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
1003 msg_is_read ? 'R' : 'W');
1004 ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
1006 debug("i2c_xfer: [STOP]\n");
1007 i2c_imx_stop(i2c_bus);
1010 read_mode = msg_is_read;
1013 if (msg->flags & I2C_M_RD)
1014 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1015 msg->len, nmsgs == 1 ||
1016 (msg->flags & I2C_M_STOP));
1018 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1026 debug("i2c_write: error sending\n");
1028 i2c_imx_stop(i2c_bus);
1033 static const struct dm_i2c_ops mxc_i2c_ops = {
1034 .xfer = mxc_i2c_xfer,
1035 .probe_chip = mxc_i2c_probe_chip,
1036 .set_bus_speed = mxc_i2c_set_bus_speed,
1039 static const struct udevice_id mxc_i2c_ids[] = {
1040 { .compatible = "fsl,imx21-i2c", },
1041 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
1045 U_BOOT_DRIVER(i2c_mxc) = {
1048 .of_match = mxc_i2c_ids,
1049 .probe = mxc_i2c_probe,
1050 .priv_auto = sizeof(struct mxc_i2c_bus),
1051 .ops = &mxc_i2c_ops,
1052 .flags = DM_FLAG_PRE_RELOC,